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2021-03-01sb/intel/bd82x6x: Turn ME PCI register structs into unionsAngel Pons
This allows dropping the `pci_read_dword_ptr` and `pci_write_dword_ptr` wrappers. Change-Id: I7a6916e535fbba9f05451d5302261418f950be83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49993 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01sb/intel/lynxpoint/me_9.x.c: Rename to me.cAngel Pons
This code will eventually support both ME 9.x and ME 10. Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-27sb/intel/ibexpeak: Drop useless bd82x6x pcie.cAngel Pons
The PCIe device IDs for Ibexpeak are not in bd82x6x's pcie.c driver. Thus, the code has always been dead code on Ibexpeak. Drop it. Change-Id: Ide2b4af2a187ecf98f39a9c979646a7ed959c74f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51067 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27sb/intel/ibexpeak: Add all PCI IDs for LPCAngel Pons
Taken from document 322170-028 (5 series specification update). Tested on out-of-tree HP ProBook 6550b (HM57), fixes several issues. Without this patch, EHCI controllers had no IRQ assigned and there were unexpected exceptions about NMIs. With this patch, the issues are gone. Change-Id: Icd31dd89ba49e38a5e4c108a8361dbf636332ab8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51066 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1Angel Pons
Add the missing PM initialization for Lynxpoint-H. There are some small changes to Lynxpoint-LP, since some register writes are common among both PCH variants. This is based on version 1.9.1 of reference code. Remove the `pch_fixups()` function. The DMI configuration is specific to Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI. Tested on Asrock B85M Pro4, still boots. Registers have the new values. Without this patch, nearly all registers don't have the expected values. Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47208 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25sb/intel/lynxpoint/acpi: Add missing USB portsAngel Pons
Broadwell has these devices, so add them to Lynx Point as well. This is done in preparation to have Broadwell boards use Lynx Point ACPI code. Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46959 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25sb/amd/agesa/hudson/lpc: Remove space between function and signaturePaul Menzel
Change-Id: I4dd40014259ac3fd0223f7feb08620b87735f60b Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-25sb/amd/agesa/hudson: Use comment style from style guidePaul Menzel
Change-Id: I73d713ec3aa62ae207640ac7e5550e5407f5afa2 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-23sb/amd/common: Drop dummy variable assigmentKyösti Mälkki
Change-Id: I9b523bda2332859074d2e12c5cb70df68e18063d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-23sb/intel/lynxpoint: Refactor some GNVSKyösti Mälkki
Change-Id: I9524a44f8f4b8e286229d81d10704438f11c4580 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL"Angel Pons
This reverts commit 1a25c9cdfd3fd391328133ba94c63ecd1083e4f8. Reason for revert: No longer necessary. Change-Id: I8adeeebd6e841ef2c878622559dcd15848969842 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46955 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20ACPI: Use common OperationRegion for PCI_MMCONFKyösti Mälkki
Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20sb,soc/amd: Drop OSFL method in ASLKyösti Mälkki
Variable OSVR had a static value of 3 and OSFL() did not actually call _OSI or _OS methods. The conditional in HDA _INI method of OSVR is dropped and use of DMA NoSnoop attribute remains disabled to retain previous behaviour. For soc/amd/picasso a different decision was made in CB:40782 as HDA _INI method was just dropped and default configuration enables use of DMA NoSnoop attribute. Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-20sb/amd/cimx/sb800: Drop OSFL method in ASLKyösti Mälkki
Method only set variable OSRV, which nobody evaluates. Change-Id: Ia21b544eaaa61a8fc634eb568b4c7401a225eb76 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-18southbridge: Ensure common Kconfig gets included lastAngel Pons
Change-Id: Icaa64e664499090fec3e98687b4827ef27cc201b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-18sb/intel/ibexpeak: Drop obsolete SATA register settingsAngel Pons
Code was copy-pasted from older chips and has no effect on ibexpeak. Change-Id: I3c5b2b8e4aa6211975c3e3dc1d64432886ef9352 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47864 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18sb/intel/lynxpoint: Correct read width in RMW cycleAngel Pons
The register is 32 bits wide, so do not read 16 bits out of it. LynxPoint PCH reference code version 1.9.1 always uses 32-bit accesses. Change-Id: I18fbba0603579417e09ae4eb4eb273f7fcd903fc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47098 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16sb/intel: Add missing <types.h>Elyes HAOUAS
Add needed but missing <types.h>. Change-Id: I19d01e1837b1ee946c66d4cc22a5138b64d72078 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50577 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16sb/intel/*/lpc: Remove unused <string.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<' Change-Id: I8f8655853fd1fc1f3679a4549fdaa08702f96c7b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-15sb/amd: Remove unused <console/console.h>Elyes HAOUAS
Change-Id: I8c0a40a14d0a9050b83fe5e9988db70b7f94b81c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50531 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15mb/google/auron/var/buddy: Switch to Lynxpoint GPIO macrosAngel Pons
Prepare to unify Lynxpoint LP and Broadwell GPIO code. Tested with BUILD_TIMELESS=1, Google Buddy remains identical. Change-Id: I6e6256a9cc88c9d0743150bfdf12b1b482fe157d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50070 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15sb/intel/lynxpoint: Clean up lp_gpio.hAngel Pons
Move `mainboard_gpio_map` declaration inside header and reorder some function declarations. This is to align the header with Broadwell. Change-Id: I436d7fdabf8d574e5dd2787fb6097f384cc8e453 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50065 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14sb/amd/cimx/sb800: Move common OSFL method in ASLKyösti Mälkki
We deal with mb/lippert/frontrunner-af later since it currently does not include <cimx/sb800/acpi/fch.asl>. Change-Id: I30b611fc1fb01777223d7222adc96308a247a35c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14ACPI: Move common _PIC methodKyösti Mälkki
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14sb,soc/amd: Drop empty CIRQ call from _PICKyösti Mälkki
Change-Id: Iaa51e0530a3f72456d3d4e7a0c55b768ba63e322 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49904 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14sb/amd/cimx/sb800: Drop CIRQ method from _PICKyösti Mälkki
Change-Id: Ie4aad7b6580100377c12f128905f7f409bdb5295 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50590 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14sb,soc/amd: Move _PIC method to global scopeKyösti Mälkki
Fix regression with commit aa969e887a ACPI: Move PICM declaration. While mentioned in the commit message there already, the default value for AMD boards changed from IOAPIC mode to PIC mode. ACPI 6.3 spec has this text regarding _PIC method: If the platform CPU architecture supports PIC mode and the method is never called, the platform runtime firmware must assume PIC mode. If MADT has IOAPIC entries, OS will want to change to APIC model. But the method _PIC was not in the global scope so it could not be called and therefore _PRT continued to report PIC model interrupt routing. Already fixed for soc/amd/picasso in commit 839f668. Change-Id: I7f3bb0d45946cec315694de1d540fea4d828348e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-13sb/intel/bd82x6x: Clean up early_me.c cosmeticsAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I0dfbaaf4cb17841de109ea6abc08022846b5bd4e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49994 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb/intel/bd82x6x/me_smm.c: Deduplicate finalisation codeAngel Pons
The only difference between ME7 and ME8 is the MKHI message handling. Remove duplicated code, and also clean up includes. Change-Id: Ia44eb29d3509eb4208ba2aed9e0cf7e8f8d2c41a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49992 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb/intel/bd82x6x: Move ME SMM code into a separate fileAngel Pons
This allows dropping some preprocessor usage. The `mkhi_end_of_post` static functions had to be renamed to avoid a name clash. A follow-up will tidy up the code in me_smm.c to reduce some duplication. Change-Id: I6357fed3540be87f42d1fd59534666b9092d0652 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49991 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb/intel/bd82x6x: Relocate some static functionsAngel Pons
This allows us to get rid of the `__unused` attributes. Subsequent commits will separate ramstage and SMM code into separate files. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I1aaef5aa23561bee04f8dd9ddca66738bca91bb4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49990 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb/intel/bd82x6x: Use HPTS() for HPET visibilityKyösti Mälkki
Platforms with bd82x6x do not initialise OSYS, so HPET is always hidden. The two boards lenovo/x201 and packardbell/ms2290 using sb/intel/ibexpeak but still including <bd8x62x/acpi/lpc.asl> initialised OSYS using _OSI() method and showed HPET selectively. Change-Id: I02fffd439be2a5a9d22afd67e68abce888361214 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49486 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13intel/broadwell,lynxpoint: Use HPTS() for HPET visibilityKyösti Mälkki
Platforms do not initialise OSYS so HPET is always hidden. Change-Id: I5f030b156355ea407d37cdb2eda8a3161085436f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-13sb/intel/i82801jx: Use HPTS() for HPET visibilityKyösti Mälkki
Change-Id: I741d94341ed59f5b5fbb8526205e8b502764a15a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50481 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb/intel/i82801gx,ix: Use HPTS() for HPET visibilityKyösti Mälkki
Change-Id: Id38228265ad89e3f96ea6f37bcc0da574a3f8c3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49484 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13sb,soc/intel: Add HPTS() for HPET visibilityKyösti Mälkki
Based on the detected OS the HPET ACPI device needs to be hidden sometimes. Change-Id: I4c6f87f30ea0de5c073b1fcf57794bb9e19d4d91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49483 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12sb/intel/x/lpc.c: Drop commented-out `gpio_init` callAngel Pons
Change-Id: I4255c63f87e8243237204ac86eb85e34b5aaa225 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing`Angel Pons
The southbridge common SPI support already does this. Tested on Asrock B85M Pro4, internal flashing and MRC cache still work. Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12sb/intel/lynxpoint: Do not mask out TCO status bitsAngel Pons
Not all TCO status bits have a corresponding enable bit. Masking out the status register with the enable register causes these events to be lost. Tested on Asrock B85M Pro4, BIOSWR_STS events are now detected. Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-12sb/intel/lynxpoint: Only generate SerialIO SSDT for PCH-LPAngel Pons
Lynxpoint PCH-H does not have SerialIO, so do not generate its SSDT. Change-Id: Ie816ebd470df93a45826498bf21be59ff0a813bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12sb/intel/lynxpoint/pch.h: Guard macro parametersAngel Pons
Guard against unintended operator precedence and associativity issues. Tested on Asrock B85M Pro4, still boots. Change-Id: I2b22af17816e5383c7eb215a773eb6750d4ed9bc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12sb/intel/common: Move named packages out of methodAngel Pons
IASL complains that creation of named objects within a method is highly inefficient. Avoid this by moving these named objects out of the method. Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-11sb/intel/ibexpeak: Drop Global NVS supportAngel Pons
Was copy-pasted from bd82x6x and no mainboard actually needs it. The few globals moved outside the GNVS will be removed, relocated or replaced with acpigen later. Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb/intel/i82801jx: Drop Global NVS supportAngel Pons
Was copy-pasted from i82801ix and no mainboard actually needs it. Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49279 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11ACPI: Move PICM declarationKyösti Mälkki
Variable PICM was not inside GNVS region and can use a static initialisation value. For most AMD platforms PICM default changes from 1 to 0. Fix comments about PICM==0 used to indicate use of i8259 PIC for interrupt delivery. Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb,soc/intel: Drop OSYS from GNVSKyösti Mälkki
The value should be set by OSPM using some combination of _OSI() queris in the \_SB._INI() method. To maintain previous behaviour with this commit, boards where GNVS osys initialisation was removed now do the same in ASL. Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11mainboards: Drop PWRS from GNVSKyösti Mälkki
Initialize variable to 1 to indicate AC power supply. If platform has EC it will set this correctly based on whether plugged on the charger or not. Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespaceElyes HAOUAS
Make it look more like the file under amd/pi/hudson. Change-Id: I5b40dc5b6f54bf68113826e693ca5963fec83d38 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-11sb/intel/common/rtc.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: Ie11fffdf907227ab315bfd4887aaa5de3602bd24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-11sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix commentsAngel Pons
Change-Id: Iff701d8e6d672b3ca97d9d6361ba48736c06c6c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 17:23:58 +0000