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2012-07-26ELOG: Support GSMI in CPT/PPT southbridge SMI handlerDuncan Laurie
In order to support the GSMI interface the SMI handler needs to find and use the state save area from the same CPU that initiated the SMI. In this case it is a synchronous SMI resulting form an IO write to port 0xB2. To find the right CPU state save area iterate over the region until the "IO Misc Info" field reports the expected value and then proceed to use that state save area. This is needed because the coreboot SMI handler only executes on one core, and that core is non-deterministic. It is likely that the core executing the C SMM handler is not the same one that actually did the IO write to 0xB2 and generated the SMI. The GSMI parameter buffer is passed as a pointer to EBX in the tate save area, and the GSMI command is extracted from EAX before it is used as the return value. This interface is tested by enabling CONFIG_GOOGLE_GSMI in the kernel and generating events and verifying that they end up in the event log. 159 | 2012-06-23 16:22:45 | Kernl Event | Clean Shutdown 184 | 2012-06-23 17:14:05 | Kernl Event | Oops 185 | 2012-06-23 17:14:05 | Kernl Event | Panic Change-Id: Ic121ea69e9f50c88467c435e095c3e3629989806 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1317 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25SMM: Skip locking SPI registers in finalize stepDuncan Laurie
This is a temporary workaround so the SPI bus can be accessed at runtime in SMM code until the SPI opcode menu is used properly. Change-Id: I93d188c55b66d8dce49fa91a1de53ee195944b30 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1318 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25ELOG: Log boot-time events found in southbridgeDuncan Laurie
This is called from the SMI handler install because those setup functions clear many of these registers. Ensure that these events show up in the log as appropriate. Example log output: 159 | 2012-06-23 14:31:54 | SUS Power Fail 160 | 2012-06-23 14:31:54 | System Reset 161 | 2012-06-23 14:31:54 | ACPI Wake | S5 Change-Id: I48c423c10ee7e6c2829bcc95f6cfabb4979c25a9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1319 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25SMM: rename tseg_fixup to tseg_relocate and exportDuncan Laurie
This function is exported so it can be used in other places that need similar relocation due to TSEG. Change-Id: I68b78ca32d58d1a414965404e38d71977c3da347 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1310 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-25CougarPoint/PantherPoint: Add HM77 device ID to tableKimarie Hoot
Change-Id: Ic5aada423d8e61abbebfcaaf5cb02ede80dfae02 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/1339 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-07-25bd82x6x: Drop unneeded pci_dev_tStefan Reinauer
This was introduced when porting the SPI driver over from u-boot but it is not needed. Hence drop the extra typedef and use device_t instead. Change-Id: I3ab797a8e482d1c9aa1d004e488e99aeaffcdd8b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1331 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-07-24CPU: Set flex ratio to nominal TDP ratio in bootblockDuncan Laurie
CPUs with configurable TDP will run the TSC at the max non-turbo ratio for the maximum TDP value, which can cause issues if another TDP is desired. To deal with this we set the flex ratio to the nominal TDP ratio early in the boot and then configure the Soft Reset Data registers so the PCH can tell the CPU what frequency to run at after a reset. This is done very early in the bootblock because it is necessary to reset the system after setting a flex ratio. The end result is that the TSC will now increment at the max non-turbo frequency for the nominal TDP. On some system with 1.8GHz CPU ensure that the kernel detects the CPU speed as ~1800mhz rather than ~2300mhz: > dmesg | grep "MHz processor" [ 0.004000] Detected 1795.801 MHz processor. Change-Id: I8436dced9199003b6423186a2b041e3f7b84ab8c Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/1329 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24SMM: Fix state save map for sandybridge and TSEGDuncan Laurie
There are enough differences that it is worth defining the proper map for the sandybridge/ivybridge CPUs. The state save map was not being addressed properly for TSEG and needs to use the right offset instead of pointing in ASEG. To do this properly add a required southbridge export to return the TSEG base and use that where appropriate. Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1309 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24SMM: Add option for SPI driver to be available in SMMDuncan Laurie
- add Kconfig option for CONFIG_SPI_FLASH_SMM - compile subsystem and chip drivers for smm if enabled - change mdelay(1) to udelay(500) since mdelay is not defined in SMM and a 1ms delay is worth avoiding - make flash chip structure non-const so the probe function pointers can be relocated for use in TSEG - Make SMM PCI access possible in southbridge SPI code Change-Id: Icfcbbe8e4e56658769d46af0b5bf6c79a6432641 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1313 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Fix automatic ME detection in finalizeStefan Reinauer
The ME needs to be talked to through the PCIe memory mapped config space. Change-Id: Ic2c5a572a126722a08a82d95df13d11507586c6b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1284 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Cougar/Panther Point: Compile in ME7 and ME8 code at the same timeStefan Reinauer
In the short term there might be devices with Sandy Bridge CPUs on mainboards with Panther Point PCHes. While this configuration option is perfectly valid, coreboot currently ties Sandy Bridge to Cougar Point and Ivy Bridge to Panther Point. One occurence is in the ME handling code. To make coreboot most flexible, compile both ME handlers into coreboot and decide at runtime which one to use. Change-Id: Icffe2930873f67c99c3f73e37e7a967f4f002b88 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1280 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Fix ME hash functions on Panther Point/Cougar PointStefan Reinauer
- On Cougar Point there may have been stack corruption during the ME hash verification - On Panther Point the ME firmware hash was not passed on to the OS Change-Id: I73fc10db63ecff939833fb856a6da1e394155043 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1279 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24Add PCIe port disable debug messageMarc Jones
The PCIe device enable function prints when it disables a device. The PCIe ports(bridges) use a different routine that didn't print the message. Add it to be consistent and to provide better debug output. Change-Id: I8462c48e7f4930db68703f0bfb710c01c9643a98 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1326 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-07-24bd82x6x: Support power-on-after-power-fail betterStefan Reinauer
Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Modelled after http://review.coreboot.org/#/c/444 Change-Id: I2b8461dff1ae085c1ea4b4926084268b4da90321 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1323 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24Fix function generating GPIO state based vectorVadim Bendebury
The function was too eager shifting stuff around, this change corrects the problem. Change-Id: I4c13dbe86cb627835dae05bb74af9867c28e143d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1291 Tested-by: build bot (Jenkins)
2012-07-24Add specific power management init code for PantherPointDuncan Laurie
There are enough subtle differences in the magic values that it is easier to make a separate function. This fixes a reset hang with pantherpoint chipset. Change-Id: I02b03cb37e5fd5ee2fd62067644f0a62dc2cd26a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1322 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-07-24RTC: Enable extended CMOS in the bootblockDuncan Laurie
This makes it available early in romstage without having to worry when the different romstagse enable it. Check for extended CMOS to be enabled in early romstage. This is used by a later commit which uses the extended CMOS region for stoage. Change-Id: I9e026d48499c63d6503c2b020d4cc3047126fa93 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1306 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24bd82x6x: Convert all PCI ID lists to new schemeStefan Reinauer
- Convert all PCI ID lists to new scheme - Unify code (variable names) - add missing PCI IDs for Panther Point PCIe root ports. Change-Id: I6357f6ebce7ddffe45a3ec642b0c594147f6134c Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1301 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24Add support for HM70 and NM70 LPC bridgeStefan Reinauer
This lets the SPI driver and the LPC driver know about HM70 and NM70. Change-Id: Id2f1e0e5586a2f7200b2d24785df3f2be890da98 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1300 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24cs5536: add smbus support in ramstageChristian Gmeiner
With this patch it is possible to use the smbus in ramstage. The biggest part of the patch is a simple code split into a general part (smbus.h) and the concrete users (early_smbus.c and cs5536.c). After the switch from romstage to ramstage the smb base address has changed, but that is no problem as the new base address is stored in bar0 of the ISA bridge. It could also be read via msr, but via PCI it is simpler. I used the following patch as reference on how to readout the new base address: http://lists.laptop.org/pipermail/commits-kernel/2006-November/000178.html Change-Id: I9f86a1e474368c62f9ed3a95edfb3e63117aa156 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/1243 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-24SPI flash layer: remove unused function spi_flash_free()Stefan Reinauer
We don't ever free memory in coreboot, hence drop spi_flash_free() and spi_free_slave() Change-Id: I0ca3f78574ceb4516e7d33c06ab1a58abfb3b0ec Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1273 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-22Trinity wrapper code improvement.zbao
Set the default location of hudson firmware to 3rdparty. Move UMA code from mainboard to northbridge. Change-Id: I11afea0c7fd04aa84a629dc762704c42baf002df Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1241 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-16Define global uma_memory variablesKyösti Mälkki
Use of the uma_memory_base and _size variables is very scattered. Implementation of setup_uma_memory() will appear in each northbridge. It should be possible to do this setup entirely in northbridge code and get rid of the globals in a follow-up. Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-14AGESA F15 wrapper for Hudson.zbao
Hudson code has been integrated from CIMx to AGESA. This patch is about the wrapper. Change-Id: I63d951982140b82a3a77a97eb3d55fc75fc0caa3 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1157 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03Fix AMD S3 block generator on CygwinPatrick Georgi
awk on Cygwin created the UTF-8 value for the 0xff code point, which makes it two bytes wide. This broke the build. Change-Id: I4937ae7ce1136ba7a76d05b42f9dd2771203175d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1164 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-07-03AGESA F15 wrapper for Trinityzbao
The wrapper for Trinity. Support S3. Parme is a example board. Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-06-23i3100: add smbus_write_byte()Sven Schnelle
Required for Supermicro X7DB8, which needs the FBDIMM clock generator setup during romstage. Change-Id: I30ca8354087e851487aee0614595782131d4d9bc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1116 Tested-by: build bot (Jenkins)
2012-06-21i3100: Enable second IOAPIC for PCI-XSven Schnelle
i3100/i5000 have a second IOAPIC which handles IRQs for PCI-X. Add code to enable it. Change-Id: Ib447628f501b152c8adc9c7c89bd09b5615b9e5a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1118 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-06-21Don't use 64-bit constant 0x100000000 in linker scriptsNico Huber
The constant value 0x100000000 is used in linker scripts to calculate offsets from the end of 32-bit-addressed memory. There is nothing wrong with it, but 32-bit versions of ld do the calculation wrong. Change-Id: I4e27c6fd0c864b4d98f686588bf78c7aa48bcba8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1129 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-06-12Update SB800 CIMX FADTMartin Roth
- Add #define to allow the FADT PM Profile to be overridden. - Change the location of the PMA_CNT_BLOCK_ADDRESS to match current documentation. - cst_cnt should be 0 if smi_cmd == 0 - add a couple of default access sizes. - Add a couple of #define values for unsupported C2 & C3 entries. - Add PM Profile override value into amd/persimmon platform. This does not use the #defines in acpi.h so that the files that include this don't all need to start including acpi.h. Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094 Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/1055 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-30Provide functions to access arbitrary GPIO pins and vectorsVadim Bendebury
This change adds utility functions which allow to read any GPIO pin, as well as a vector of GPIO pin values. As presented, these functions will be available to Sandy Bridge and Ivy Bridge systems only. There is no error checking: trying to read GPIO pin number which exceeds actual number of pins will return zero, trying to read GPIO which is not actually configured as such will return unpredictable value. When reading a GPIO pin vector, the pin numbers are passed in an array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass pointer to array of {4, 2, 15, -1}. Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1049 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-30Add support for Panther Point to SPI driverStefan Reinauer
Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1048 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-29Fix compilation with CONFIG_DEBUG_SPI_FLASH enabledStefan Reinauer
Right now coreboot compilation fails when SPI flash debugging is enabled. Fix it by using the right set of memory functions. Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-29Fix full reset for Ivy Bridge platformsVadim Bendebury
Experiments have shown that writing plain value of 6 at byte io address of 0xcf9 causes the systems to reset and reboot reliably. Change-Id: Ie900e4b4014cded868647372b027918b7ff72578 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/1050 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-24cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan
Remove all the repeated sections of code in cbtypes.h and place it in a common location. Add include dir in vendor code's Makefile. Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798 Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Reviewed-on: http://review.coreboot.org/912 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-15Fix fadt legacy free setting.Marc Jones
The fadt legacy free logic was backwards. Change-Id: Ieb21ef335f7514ced70248d0bf8668ddb73cf59f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1030 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2012-05-12Add legacy free setting and override to fadt.cMarc Jones
The FADT iapc_boot_arch indicates the available information for accessing legacy devices. By default, the setting supports legacy. LEGACY_FREE and/or the iapc_boot_arch field may be customized. Change-Id: I5679741e1f8db923d3c00b57f6a5d813550f3a5e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1024 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-05-12Merge sb800 fadt fixes from South Station mainboard to southbridge fadt.Marc Jones
The South Station recieved updates that fix a number of fadt problems. South Station now uses the southbridge fadt. Change-Id: Ib990a69a359a4b7eae3431bb4323acd537acda1d Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2012-05-10Add SPI flash driverStefan Reinauer
This driver is taken from u-boot and adapted to match coreboot. It still contains some hacks and is ICH specific at places. Change-Id: I97dd8096f7db3b62f8f4f4e4d08bdee10d88f689 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/997 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-10Unmark source files as executablesAlec Ari
Change source file modes from 755 to 644 The following files have been grepped for changes: *.c *.h *Kconfig* *Makefile* Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/1023 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-09Move fadt.c to the cimx sb800 southbridge directory to be shared.Marc Jones
The fadt.c is the same across all the platforms using the sb800 cimx southbridge wrapper. Change-Id: Ifbbfc238732aa46aef96297eaa188b77d27151f3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1019 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-09Add simple PMIO & PMIO2 read/write routines to CIMX wrapperMartin Roth
These are the PMIO & PMIO2 read & write routines from src/southbridge/amd/sb800/sb800.c & sb800.h for use in the cimx tree. Currently most platforms using CIMX are calling WritePMIO() directly from the src/vendorcode/amd/cimx/sbX00 directories instead of using a wrapper function. These functions only do byte reads & writes. Change-Id: I881a6e2d4ddbba3dbdf4dd33e06313fe88b3682a Signed-off-by: Martin L Roth <martin@se-eng.com> Reviewed-on: http://review.coreboot.org/981 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-08Some more #if cleanupPatrick Georgi
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} + (manual tweak since it hit a false positive) Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} + Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1006 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-08Clean up #ifsPatrick Georgi
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} + Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} + Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} + Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO: find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} + (and some manual changes to fix false positives) Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1004 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-01Fix issue with PCIe power management setupDuncan Laurie
The current early PM setup that attempts to configure dynamic clock gating relies on PCIe functions to be enabled that may not be. Instead of reading port 0 or 4 directly to determine the link width use the register that refelects the soft strapping options as this will always be available. Also add a clear register assignment and break for port 0 in the switch statement instead of falling through to port 4 as that could end up setting the slot power limit based on port 4 values instead of based on port 0. register 0xE1=0x3f and all other root ports should have 0xE1=0x03. When port 0 and 4 are disabled they will have 0xE1=0x3C before being disabled by the pch enable handler. LUMPY default: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) pci_read8 0 0x1c 0 0xe1 0x3f pci_read8 0 0x1c 3 0xe1 0x03 LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) pci_read8 0 0x1c 0 0xe1 0x3f pci_read8 0 0x1c 1 0xe1 0x03 Change-Id: I33a37b0ec0c8e570cf5d9dda2c06e0225fee135c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/980 Tested-by: build bot (Jenkins)
2012-05-01Add an option to enable PCIe root port coalescingDuncan Laurie
Background: The PCI spec (3.0-3.2.2.3.4) requires that PCI devices implement function 0. The Linux Kernel therefore will not enumerate a PCI device if it does not present a valid config space at function 0. If a board does not have anything connected to root port 0 and it is desired to disable the unused ports in order to save power then this will cause the other downstream PCIe devices to go missing as they will not be enumerated. Intel chipsets provide a way to map root port numbers to different PCI function numbers, thereby avoiding this issue and allowing root port 0 to be turned off. This change adds a new chip config option 'pcie_port_coalesce' that will collapse the enabled root ports into a linear map starting at zero. This option defaults to disabled as it can have a confusing effect on the system as the declared static devicetree may not match what is seen at runtime. This option is also forced on if the static devicetree disables port 0. When each root port is processed in the early enable stage it looks for a lower numbered root port that has been disabled and then swaps the two assigned function numbers. However the mapping register is write-once so it has to keep track of the proposed mapping changes until all ports have been processed before writing out the final map value. At this point it also updates the function numbers in the static device tree so they are consistent with the new layout. There are a few other closely related fixes in this change: 1) There is a power savings opportunity if an entire bank of ports (0-3 or 4-7) are disabled. This was checking the chipset revision to look for CougarPoint B1+ stepping and that was not passing on PantherPoint where this should always be applied. To fix this I added a function to determine the chipset type based on comparing the upper byte of the device ID. 2) Apply the same chipset type check fix to the IOBP programming. 3) There is another power savings opportunity to enable dynamic clock gating on shared PCIe resources which only applies to ports 0 and 4. However if 0 or 4 is disabled then the later check to enable this would fail as that device is already hidden. LUMPY current: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) 01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01) 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) 01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01) 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B Change-Id: I828aa407fdc9c156c1c42eda8e2d893c0aa66eef Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/979 Tested-by: build bot (Jenkins)
2012-05-01Update PCIe Root Port _PRT to handle re-mapped functionsDuncan Laurie
The chipset enforces static-defined interrupt swizzling on PCIe root ports so if a port is remapped to a different function it needs to still report the proper interrupt map to the OS instead of assuming that function number is equivalent to root port number. This change also includes an update to the PCH function disable register which was incorrect for CPT/PPT and would cause unpredictable behavior if used. The kernel command line was changed to add 'nomsi' in order to force PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure that the mapping is correct. LUMPY current: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) 16: 41518 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k 19: 720 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0 LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) 16: 38988 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k 19: 347 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0 Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/978 Tested-by: build bot (Jenkins)
2012-05-01Fix SATA port map to only enable port 0Stefan Reinauer
The sata controller comes up in legacy/normal mode and is currently put into AHCI mode in romstage. If that is removed and the controller is left alone until the ramstage driver (like we do on Stumpy/Lumpy) then the resource allocator will have configured the device for IDE mode with an IO address in BAR5. Then when the ramstage driver puts the controller into AHCI mode it will not have the correct resources to do the rest of the AHCI setup. So the controller mode needs to be changed in the enable stage rather than in the init phase. This same register contains the port map and it is a R/WO (write once) field so the configured port map must be written at the same time. For non-AHCI mode the devicetree map was ignored before but it is used now. Since the port map register is now written at enable step it does not need to be written again during init. With this change the sata port map can be reduced to just port 0 and then U-boot does not have to probe all available ports. Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/977 Tested-by: build bot (Jenkins)
2012-05-01Don't disable ACPI in the S3 resume pathDuncan Laurie
The OS does not re-execute the APMC 'enable ACPI' SMI on resume so this has the potential to leave things in an unknown state. Change-Id: Iaf0fcb99f699e9e0ecacaab3f529026782a95151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/971 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01add new LPC controller device ID valueVadim Bendebury
This adds the PCI device id of the LPC controller identifying the QPRJ/QS stepping of the Panther Point southbridge. Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/968 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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