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2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-09sb/intel/i82801gx: Use 'const' to set pci_devfn_t staticallyElyes HAOUAS
Change-Id: I4b33b42f41c7e34c5eab70edf2f12862816220d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09sb/{bd82x6x,ibexpeak,lynxpoint}/early_smbus: Use macroElyes HAOUAS
Change-Id: If57d785b92f0f09d9def90b8ac87833321e3cfcf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09sb/ibexpeak: Use .device for single PCI IDFelix Singer
Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I40c4447579cfbf2b9c52dcfaa34f34b22f75c89c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39332 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-07sb/intel/bd82x6x/sata: Set values as described in BIOS specFelix Singer
Set some things missed originally because of formatting issues in the BIOS spec. Values were compared with a vendor dump. Change-Id: I27360d6ea5d1f00b1ed350f47ff40a22f19dfb05 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40231 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-07sb/intel/bd82x6x: Drop PCI resource reg overrideFelix Singer
Assignment of PCI resource registers is up to the allocator. Therefore, drop override of the PCI resource register. Change-Id: I184a263c81aa8a434fcd153406b73058914cb2f9 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-04-07sb/intel/bd82x6x/sata: Don't hard-code valuesFelix Singer
The interrupt line registers are configured in a central place, pch_pirq_init() in `lpc.c`, according to the PIRQ configuration. Hardcoding values here makes no sense. Change-Id: Ide5f101b2e5bda84f3c2ff8c8ca636b8233bb948 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-06sb/intel/lynxpoint: Use SPDX headersAngel Pons
All the files are GPL-2.0-only. Change-Id: Ibad9b2b81337483435491f8e6b4079011f2356d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-05sb/intel/i82801gx: Improve code formattingElyes HAOUAS
This mainly updates the formatting for the new 96 characters text width. Change-Id: Ia75c3ca7136b0291b3ae82e6a281cc76b75965ca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40127 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05Drop explicit NULL initializations from `device_operations`Elyes HAOUAS
Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside that, the struct has grown over the years. There are too many optional fields to list them all. Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-04sb/intel/bd82x6x: Use SPDX headersAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I08b4f5f53e493371848f588e6976d349e56b0620 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40019 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-04src/southbridge: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5b00b3e38edda90f35f0679cd4171a3499288f24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-02nb/intel/ibexpeak: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Ibb7898ab4fbbbfcd29b6ba72367cc55a02cd4b1e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02sb/intel/i82801jx: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Iecd8559f660cc748c417ec94b7a822e16603cbd8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02sb/intel/i82801ix: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Remove direct setting of gnvs->ndid in qemu-q35 board since build will otherwise break. Change-Id: Ifbf08f43291c1fff7ccbc85272dc97334207983b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39954 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02sb/intel/i82801gx: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: I51a11e7ed6686ab67dac3f02097457ea9c6a7e6a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02sb/intel/bd82x6x: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Ie7491409681d8c2721dd6d6a16a8d5004cd0cf8a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02sb/intel/lynxpoint: drop IGD-related NVS variablesMatt DeVillier
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Iec3a18871725fd5f5c4c568c2bd771bb56245bc7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31security/vboot: relocate and rename vboot_platform_is_resuming()Bill XIE
After measured boot is decoupled from verified boot in CB:35077, vboot_platform_is_resuming() is never vboot-specific, thus it is renamed to platform_is_resuming() and declared in bootmode.h. Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-24drivers/intel/gma/acpi: Reduce display switching stubsNico Huber
_DCS, _DGS and _DSS are required by specification. However, we never implemented them properly, and no OS driver com- plained yet. So we stub them out and keep the traditional behavior in case an OS driver checks for their existence. The old implementations also only returned static values as there never was any write to their GNVS variables. The TRAP() that was called in one place is actually implemented by some ThinkPad's SMI handler as docking event. However, as the call precedes these SMI handlers in coreboot history, it's most likely an accident. Change-Id: Ib0b9fcdd58df254d3b2290900e3bc206a7abd92d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-23acpi: Change Processor ACPI Name (Intel only)Christian Walter
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here for Intel CPUs only. Tested on: * X11SSH (Kabylake) * CFL Platform * Asus P8Z77-V LX2 and Windows 10 FWTS does not return FAIL anymore on ACPI tests Tested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23src: capitalize 'APIC'Elyes HAOUAS
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-20sb/ibexpeak: Use macros instead of hard-coded IDsFelix Singer
This patch replaces hard-coded PCI IDs with macros from pci_ids.h and adds the related IDs to it. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 322170 Change-Id: I3326f142d483f5008fb2ac878f30c1a3a72f500f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17sb/lynxpoint/gpio: fix interrupt stormMatt DeVillier
On newer kernels (> 4.9 LTS), the GPIO ACPI device's interrupt resource causes an interrupt storm which prevents the CPU from properly idling, significantly increasing power consumption. This was fixed for soc/broadwell (which also supports lynxpoint-lp) by removing the interrupt resource, so apply the same fix here. Original fix: https://chromium-review.googlesource.com/203645 Test: build/boot google/wolf, verify CPU0 idles correctly and power consumption drop via powertop in kernels 4.16.18 and 5.x. Change-Id: Ic4963f2f0225b5f44a7604b0107911640345c855 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons
The code is for Arrandale CPUs, whose System Agent is Ironlake. This change simply replaces `nehalem` with `ironlake` and `NEHALEM` with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as changing some of them would impact the resulting binary. Tested with BUILD_TIMELESS=1 without adding the configuration options into the binary, and packardbell/ms2290 does not change. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06sb/intel/common/firmware/Makefile.inc: use ifdtool --output flagMarcello Sylvester Bauer
Use the ifdtool --output flag to modify coreboot.pre inplace, instead of using the `mv` command to get the same result. In this way the stdout will make more sense in the build context. Change-Id: I6dacc8b39052801c770c02fa2aa1b526747ae496 Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-06Revert "i82371eb: Drop support for older PIIX chips"Patrick Georgi
This reverts commit 2b9004de602f98a404b17584ab3e1451f165c1f4. Reason for revert: QEMU emulates that chipset and with that commit a Linux guest kernel can't find IDE devices anymore. Change-Id: Iad75af4ea9993d6a2ec5433ad30d39900dab874e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Keith Hui <buurin@gmail.com>
2020-03-04src: capitalize 'PCIe'Elyes HAOUAS
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-03sb/lynxpoint: hook up smmstoreMatt DeVillier
Adapted from implementation in sb/intel/common. Test: build/boot variants of google/{beltino,slippy} with Tianocore and SMMSTORE enabled Change-Id: I64f520d17146206b8b9b41fc4f827539c5cfd507 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-03i82371eb: Roll 82093aa init into isa_init()Keith Hui
This allows reuse of dev and reg32 already available, and converting the block from #if to simple if. Change-Id: I7a56f5a170986bbdf3c0c87eb5ead838ad55c659 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-03i82371eb: Drop support for older PIIX chipsKeith Hui
All boards using this code use i82371eb (that shares PCI ID with i82371ab). Dropping the code lightens compressed ramstage by a few dozen bytes. Change-Id: Iab1e83b8f5fff44a33619c7925e5448169a2a87c Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38598 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03sb/intel/i82371eb: Support reconfiguring GPO22/23Keith Hui
XOE# and XDIR# can be used as GPOs 23/22 if X-Bus functionality is not required. Turns out asus/p2b-ls is using them to control termination for the onboard SCSI buses. Add support to allow this reconfiguration. Change-Id: I2dab6fafbd67a98ed1cac1ffcf9352be4a87c3e9 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-03sb/intel/i82371eb: Enable upper NVRAM bankKeith Hui
Change-Id: I9ad127ca4394e27fc055ddf03012a195cb03bd94 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-26treewide: capitalize 'USB'Elyes HAOUAS
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24treewide: Capitalize 'CMOS'Elyes HAOUAS
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11sb/intel/lynxpoint: Don't use_ADR and _HIDElyes HAOUAS
To be compliant with ACPI specification, device object requires either a _HID or _ADR, but not both. Change-Id: I45cf2b8d455aa4d288de1ac53cf9ae801f758a9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38351 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09sb/amd/{agesa,pi}/hudson/Kconfig: Change default SATA mode to AHCIPiotr Kleinschmidt
The attempt to install pfSense on hard disk on PC Engines apu2 board ended up in a SATA driver error. The problem is related only to BSD and didn't occur with Linux kernel. Changing SATA mode from IDE to AHCI solved the problem. Additionally AHCI is faster than IDE so it speeds up the installation. Since AHCI works perfectly with SeaBIOS, Linux and BSD, make it a default choice for all Hudson southbridges. Change-Id: I1b0322392712d797dd5a8931150c8d0ff1b60940 Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35891 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01sb/intel/common/acpi: Add more Windows versionsPeter Lemenkov
For the up-to-date list of Windows versions follow this link: https://docs.microsoft.com/en-us/windows-hardware/drivers/acpi/winacpi-osi Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37943 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28drivers/spi/spi_flash: remove spi flash namesAaron Durbin
The names of each spi flash cause quite a bit of bloat in the text size of each stage/program. Remove the name entirely from spi flash in order to reduce overhead. In order to pack space as closely as possible the previous 32-bit id and mask were split into 2 16-bit ids and masks. On Chrome OS build of Aleena there's a savings of >2.21KiB in each of verstage, romstage, and ramstage. Change-Id: Ie98f7e1c7d116c5d7b4bf78605f62fee89dee0a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-01-22{soc,southbridge}/*/*/acpi: Add possibility to disable S4Wim Vervoorn
Some boards don't support S3 or S4. The S4 state can't be removed from the available sleep states. Add a config item that allows removal of the S4 state from the list of available sleep states. The S4 state can be removed by selecting the item on board level. For the AMD chipsets the SSFG mask is updated to remove the S4 state. BUG=N/A TEST=build Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14sb/intel/i82371eb: Add PIIX4 definitionsKeith Hui
These new definitions will be used by two other changes. Change-Id: I242244c444f36af188c871dce037a7a9250206cd Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38367 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14sb/intel/common: Declare common smbus_base() and enable_smbus()Kyösti Mälkki
This avoids including platform-specific headers with different filenames from common code. Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-14intel/nehalem,ibexpeak: Move enable_smbus() callKyösti Mälkki
Change-Id: I6e43f7696b289ce9e0319afdcc73889ddabd4db1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-01-14intel/sandybridge,bd82x6x: Move enable_smbus() callKyösti Mälkki
Change-Id: Icc6b572fea0c2097a7ed19b3f76c1e658cf32a9a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-01-14intel/{gm45,x4x},i82801{ix|jx}: Move enable_smbus() callKyösti Mälkki
Change-Id: Idc7631abb550b31af722ccf3b69afdc01fdb616e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38268 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14intel/{i945,pineview},i82801gx: Move enable_smbus() callKyösti Mälkki
Change-Id: I7a9e613f9a142e04030672f85ea80c56151be3c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-12intel/e7505,i82801dx: Refactor raminitKyösti Mälkki
Avoid direct enable_smbus() call from northbridge code. Change-Id: I077e455242db9fc0f86432bd1afab75cb6fb6f4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12asus/{p2b-x,p3b-f},intel/i440bx: Move mainboard_romstage_entry()Kyösti Mälkki
Change-Id: I3598f548c2d122906fda09c85b5a1c82b0da993b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38255 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 21:38:16 +0000