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accessible (but not writable), so that reading/loading a payload
from that area can work (for instance).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the new src/southbridge/amd/cs5536 code completely replaces it.
The Artecgroup dbe61 board currently uses it, but that is broken anyway
at the moment. A fix to use the new CS5536 code for it is being worked on.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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setup as the host on USB port4. In client mode the headers remain
available. Also fixes an outb to 0x80 to use the post_code() function.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
-This line, and those below, will be ignored--
M cs5536.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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broke and stopped FILO
from being able to boot.
The fix is a simple one line change plus a comment to
src/mainboard/via/epia/auto.c to write to the IDE
configuration register 0x42 . This has always been done here, however
at some point
something broke it.
The same register was also being set correctly in ide_init(), however
for some reason
this does not work. Possibly the register needs to be set before the IDE
peripheral is enabled
or maybe it is a timing issue.
The section of code in ide_init() (
src/southbridge/via/vt8231/vt8231_ide.c ) that does
write to register 0x42 has been commented out as it is superfluous
and I have added a comment to indicate the reason, should someone at a
future date wonder
why.
I have also changed the default COM speed from 19200 to 115200 in
src/mainboard/via/epia/Options.lb
There has been mention before about the EPIA board not being able to use
115200 but I have seen
no such problems with my board.
Signed-off-by: Ben Hewson <ben@hewson-venieri.com>
This patch worked for me and allowed me to boot Debian kernel
2.5.16-4-486 on an epia 800 mhz system. It is able to consistently get
through the initialization and start init now.
However, after that it crashes at various points in the boot process.
Acked-by: Alex Mauer <hawke@hawkesnest.net>
Note from comitter: I am commiting this, although:
1. it's not the exact right way to fix it up, the chip.h for the sb
should change
2. Alex reports problems, which are almost certainly memory issues.
But it is as close as we've gotten. I can't test it.
Ron Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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AMD GX and LX processors. This aguments the previous code, which was
very specific to the OLPC platform with general purpose support and
better integration with the VSA and CPUs.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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as that is not RAM but used for other stuff.
First try at PCI init added to src/mainboard/tyan/s1846/Config.lb.
Use a real payload (FILO) per default now.
Note: this cannot boot a payload, yet, but it gets a lot further now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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southbridge (with integrated Super-I/O).
Signed-off-by: Corey Osgood <corey_osgood@verizon.net>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey_osgood@verizon.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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that's the same as broadcom/bcm5785.
Signed-off-by: bxshi <bingxunshi@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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2200 (too many names, sounds like a criminal).
1) Linuxbios loads kernel A; kernel A loads kernel B. Everything works
fine.
2) Then I push the reset button.
3) Linuxbios loads kernel A; kernel A loads kernel B. Kernel B complains
about wrong checksum of the mptable and crushes later.
An investigation showed that in 3), short after kernel A (v2.6.19.2)
sets
the Bus Master Enable bit of the nVidia's USB1 controller
(pci_set_master()),
the mptable gets two bytes at physical address 0x80 damaged.
Nothing is plugged to the USB ports. Other two Sun workstations had the
same
behavior. This does not make sense to me unless the controller has a HW
bug.
I believe, this should better be fixed in the kernel USB driver.
For now this patch offers a possibility for linuxbios to reset the USB
controller by setting HostControllerReset bit in HcCommandStatus
Register.
It is enablead by using 'register "usb1_hc_reset"="1"' in 'chip
southbridge/nvidia/ck804' section of the mainboard's Config.lb.
Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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won't compile), and breaks an unnecessary dependency on the usbdebug
code.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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heavily on the code for i82801dbm and i82801er
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Yinghai Lu <yinghai.lu@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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southbridge_intel_i82801dbm_control should be named
southbridge_intel_i82801dbm_ops. Otherwise a compile error occurs if this
device is included in Config.lb of the mainboard.
Closes #62
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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space offset 0x1000, and later is the acpi registers also mapped at 0x1000.
This patch fixes this behavior. Closes #44
Signed-off-by: <chn@virtutech.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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long time and I could not get into the tracker.
These are patches to enable ms9185 support. Abuild passes.
Signed-off-by: bxshi <bxshi@msik.com.cn>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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serengeti_cheeatah
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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cs5536, but I don't want to mess up the OLPC, and we really need the lx
support NOW.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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signed-off-by: Jordan Crouse
Signed-off-by: Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This one actualy works. You cannot just go mucking about with stuff that the VSA
has under its thumb. Bad Things happen. This does it the VSA way.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This should make the USB P4 work as a USB host
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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USB P4 is disabled by default and we need to setup the mux bits proper
to make it work. This is the frame work for that. All thats needed
is the right address values
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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here's a patch which replaces all DOS newlines with Unix newlines, and
removes some useless $Rev$, $Id$, and $Header$ tags.
(part 1)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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read code. SBbus reads to RAM now work. Yah!
- Rename the register constants to something I can look at
more easily.
- Make the logic flow match the flow from V1 assembly
- #if 0 out other SMbus functions that are still broken.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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UART. If the upper banks are enabled, then the Linux 8250 driver knows
how to set baud speeds greater then 115200. This was prompted by David
Woodhouse.
Jordan"
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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add support for NSC pc87351 SuperIO
add Bitworks/IMS manboard config
This is a very basic framework for the i440bx chipset and the
Bitworks IMS board that uses it. Most things are
structure only.
Known issues:
- SMbus reads to the RAM SPD come back
all zero.
- dump_spd_registers() is commented out since it breaks with
the default setting of generic_dump_spd.c where it wants
2 memory controllers.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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disabled.
cs5536: add new entires for SB control etc.
cs5536.c: chip_enabled function moved to chip_init, so it only gets run
once.
IRQ setup improved
gx2def.h: new defines added
vr.h: new file, with new def's for virtual register control.
mainboard config.lb: new entries added for nb and sb control.
chipsetinit.c: new controls added -- I forget all the details :-)
grphinit.c: new function added
northbridge.c: new IRQ control added. FlashChipSetup added, controlled
by chip info setupflash struct member. Currently, if enabled, this hangs
OLPC in linux PCI scan.
chip.h: new struct members added for unwanted device enable, flash setup
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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manage them. Make pci_level_irq global. Add value settings for OLPC
rev_a board. Comment out no-longer-needed code in olpc mainboard.c
-- it is replaced by the settings in Config.lb, and the support
in cs5536.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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