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2020-11-13sb/intel/lynxpoint/acpi/pch.asl: Drop unused FD definitionsAngel Pons
These Function Disable definitions have been copied from Cougar Point, are not used by any mainboard, and may be incorrect. So, remove them. Change-Id: I36f732bce22ec33aab42beababe54c4d88e0205b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46784 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13haswell/lynxpoint: Drop remaining uses of `ISLP` methodAngel Pons
There's no need to dynamically differentiate between traditional and Low Power platforms at runtime, and doing so makes code reuse more complex. Change-Id: Id40f2f5f41db00487af9115eabee8874c2399030 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46785 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi/gpio.asl: Serialize GWAK methodAngel Pons
Commit 576b7c7 (broadwell: gpio.asl: Make GWAK method serialized) made GWAK serialized for Broadwell. This commit follows suit on Lynx Point. The reason to serialize this method is because it creates named objects which depend on input parameters, and thus cannot be created elsewhere. Change-Id: I892700df3bba079e3280008f619017e3954d5a06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46783 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCIAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46782 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi/lpc.asl: Simplify GPIOBASE resourceAngel Pons
LynxPoint-LP handles GPIOs differently, and LynxPoint-H has the same GPIO kind as previous-generation PCHs, such as Cougar Point. Remove some unneeded logic from `_CRS` and declare the GPIOBASE resource statically. The preprocessor allows later ACPI deduplication to remain reproducible. Change-Id: If771d5b6c3a1623da7d015ed50199877615409b2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46781 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi: Statically define _PRW valuesAngel Pons
In order for ACPI deduplication to be reproducible, the `ISLP` method needs to disappear. Replace the _PRW methods with a name and a macro. Change-Id: Id0a46965b66f1a70e8f8868af01a535207c9f5c7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46780 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13sb/intel/lynxpoint/acpi: Clean up cosmeticsAngel Pons
Use ASL 2.0 syntax where possible and uniformize code style to match the IASL disassembly. Some `Store` in gpio.asl change the binary if touched. Also remove outdated comment and remove `LynxPoint` from `serialio.asl`. Tested with BUILD_TIMELESS=1, Google Panther does not change. Change-Id: Ie0994fa546ff54ebb533afcc6205efb36da99a67 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46777 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-11sb/intel/lynxpoint/sata: Simplify RMW operationsAngel Pons
Introduce the `sir_unset_and_set_mask` helper and update the one PCI read-modify-write operation that is somehow not reproducible. Change-Id: I30ad6ef8ad97ee0a8dc2297fba5bbbfe24f00f1c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-10sb/intel/lynxpoint/sata: Always use AHCI modeAngel Pons
The other two modes are not used by any mainboard, and the code seems to be copied from older southbridges. As the code looks incorrect, drop it. Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-07sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabledAngel Pons
Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF. Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2. However, current code doesn't account for this. The result is that register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is OBFF-capable but support is disabled, which makes no sense. Given that reference code and Broadwell both disable OBFF, disable it here too. Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-07sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` functionAngel Pons
Change-Id: I957556bcb3f2d793ed2d9a9c966b2081f9be090c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47042 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07sb/intel/lynxpoint/lpc.c: Correct GPI routing checkAngel Pons
Code does not match comment, but this time the comment is right. Change-Id: I4e277a802c68c8a4e858b2e33e7ec69b41dd9773 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47044 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07sb/intel/lynxpoint: Correct SATA DTLE IOBP registersAngel Pons
Testing shows that these registers are backwards. Use the definitions from Broadwell instead. All affected boards use the same value for both. Change-Id: Ie47c9fddc2e9e15ce4c64821ea3a69356ac31b1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-07sb/intel: Don't set ACPI_EN twiceAngel Pons
It is already done once when enabling PMBASE in early init. Change-Id: I14289c9164ee1488c192fce721d86c89fa5cc736 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-07sb/intel/*/lpc.c: Don't try to write read-only PCICMD bitsAngel Pons
For all these southbridges, the lower nibble of PCICMD is read-only. Tested on Asrock B85M Pro4 (Lynxpoint-H), LPC's PCICMD does not change. Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-06amdfwtool: Use shell command to get depend file listZheng Bao
The amdfwtool is not available at the beginning of the building. So it may have error if it is missing. Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-04sb/intel/lynxpoint/acpi/gpio.asl: Simplify constantsAngel Pons
Only LPT-LP includes this file, so `ISLP` is effectively constant. Thus, eliminate some unnecessary if-blocks, since only one branch gets taken. Change-Id: Ie8ba787bf5c021845e1e47256a6303697aa97fe1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46776 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04sb/intel/lynxpoint: Align LP GPIO ACPI with BroadwellAngel Pons
Move the `GWAK` method into the GPIO device, and have lpc.c include the LP GPIO code. All usages of `GWAK` on mainboards need to be updated. Change-Id: Id6a41f553d133f960de8b232205ed43b832a83d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46775 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04sb/intel/lynxpoint/acpi: Put together LP GPIO codeAngel Pons
Rename `lpt_lp.asl` and place all Lynxpoint-LP GPIO ASL there. It has been named `gpio.asl` to ease diffs between Lynxpoint and Broadwell. Tested with BUILD_TIMELESS=1, Google Panther does not change. Change-Id: I7cc4ab3371014be783761f110542471a8c0157a3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46774 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04sb/intel/*/acpi/lpc.asl: Drop unnecessary RCBA offsetAngel Pons
Nothing should be using this offset. Change-Id: Ia4736471e2ac53bec18bfe073f4aa49e3fc524a8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46765 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04sb/intel/lynxpoint: Expose full LPC device ID in ACPIAngel Pons
This is merely to align ACPI files with Broadwell. It is unused. Change-Id: I8aa297bd3c3734bbd438ff84742aadfc661adcf7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46764 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04sb/intel/common/acpi/pcie.asl: Generalise file commentAngel Pons
This file is no longer specific to 6 and 7 series PCHs. Change-Id: Ib89378bd6ba1d80281b92a79d37b9fdeaaed40fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46762 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04sb/intel/common/acpi/irqlinks.asl: Clean up cosmeticsAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I8562fc3278144380b0ab842d88176114821be823 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46760 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04soc/amd: Change FIRMWARE_LOCATE to FIRMWARE_LOCATIONZheng Bao
Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03sb/intel/lynxpoint/sata.c: Don't enable Bus MasterAngel Pons
Bus Master is not required and reference code does not set it. Tested on Asrock B85M Pro4, still boots from SATA SSD with TianoCore. Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-03sb/intel/bd82x6x/sata.c: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). Given that the existing code gracefully handles null pointers already, it is reasonable to replace these function calls with `probe_resource`. Change-Id: Ibd8f5ebd561cbde22ce5cd83de8270177bad1344 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-02azalia: Use `HDA_GCTL_CRST` macro as unset-maskAngel Pons
The `HDA_GCTL_CRST` corresponds to bit zero, so this is equivalent. Change-Id: I5f4455aa1255f8954ac8b5f1ea5cf8f0874f77a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46728 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02azalia: Treat all negative return values as errorsAngel Pons
Instead of checking whether the return value equals -1, just check if it is negative. Some Azalia implementations already do it, but most do not. Change-Id: I43ce72a01c07eff62d645db28c09584b386532ff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46727 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02sb/intel/lynxpoint: Align with BroadwellAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46726 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02sb/intel/lynxpoint/lpc.c: Simplify PM init sequenceAngel Pons
This sequence used to be an array of reg-and-or triplets, but can be simplified. The resulting sequence is closer to what Broadwell does. Change-Id: I21e79cbc1e995707b87c40187ddf03b872d02058 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46725 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31sb/intel/lynxpoint: Drop unnecessary `UL` suffixAngel Pons
With BUILD_TIMELESS=1, Asrock B85M Pro4 and Google Wolf do not change. Change-Id: I9ba4097cd82c4ff68315a40e1e955e4ed9a43862 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46719 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31sb/intel/lynxpoint: Use common code to generate HPET tableAngel Pons
There's no need to reinvent the wheel. Change-Id: If6b90c9a7a00af0322c6dd15d2c4ecf2c513d0cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46977 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30{soc/amd,sb/amd/hudson}: Fix generating the ACPI mcfgArthur Heymans
The last argument for acpi_fill_mcfg() is the last PCI bus, which is an uint8_t, not the total number of busses, which overflows the argument if CONFIG_MMCONF_BUS_NUMBER is 256. Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-10-30amdfwtool: Take a config file instead of command line parametersZheng Bao
To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-26sb/amd/*/*/pci_devs.h: Reduce the differenceElyes HAOUAS
Also add missing <device/pci_def.h> Change-Id: I227f0c2a4ccb486f1d5560e3f64bc6208a456d68 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-26sb/amd/*/*/smbus.h: Make 'smbus.h' uniformElyes HAOUAS
Reformat 'smbus.h' files and add missing <stdint.h>. Change-Id: If78f483ca8ad2e3cffe60e22948dc8150cce3664 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-10-26src: Include <arch/io.h> when appropriateElyes HAOUAS
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24sb/intel/lynxpoint: Ensure that `dev->chip_info` is not nullAngel Pons
Use either a regular null check or `config_of` to avoid bugs. Change-Id: I36a01b898c3e62423f27c2940b5f875b73e36950 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46665 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24sb/intel/lynxpoint: Use spaces around `|`Angel Pons
Coding style says so. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I72386bbe4b38602a641bf8dc9448d6a3e95d297a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46718 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24sb/intel/lynxpoint/pcie: Fix clock gating routineAngel Pons
The use of `1 < 5` as a bit mask was obviously a typo. Correct it as `1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states. Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45713 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23sb/intel/lynxpoint: Drop space after castsAngel Pons
Casts can be considered unary operators, so drop the space. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ib180c28ff1d7520c82d2b5a5ec79d288ac8b0cf3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-20sb/intel/ibexpeak: Align to coreboot's coding styleAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I30512ef7ff7eb091e1f880c43a0a9ecf8625a710 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46530 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19sb/intel/ibexpeak: Use ARRAY_SIZE macroAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I01730e25ee78a74048f0b93faef00ebaee82ba77 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46529 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-14haswell/lynxpoint: Align cosmetics with BroadwellAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13src: Rename EM100Pro-specific SPI console Kconfig optionAngel Pons
To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this option with `EM100Pro`. Looks like it is not build-tested, however. Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-12sb/intel/i82801gx/acpi: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS
Also remove extra empty lines. It builds same binary for apple/macbook21 using BUILD_TIMELESS=1 Change-Id: Ibf349bb70b1fee31bfcdb4c87ffa5b4b8359e289 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45275 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12sb/intel/lynxpoint/pcie.c: fix typo in commentMatt DeVillier
Change-Id: I741b66e08d977f514f2512d626e3bcf22ce7d46c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-10-12sb/intel/lynxpoint: Set PCIe L1 substates capabilities registerMatt DeVillier
Copied from soc/intel/broadwell. Test: build/boot google/beltino variants, verify L1 PM substates listed under PCIe device capabilities Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46134 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12sb/intel/lynxpoint: Enable/disable AER via KconfigMatt DeVillier
Several changes[1][2] to the Linux kernel now enable ASPM/AER for the rt8169 network driver, for which it was previously disabled. This, coupled with the southbridge enabling AER for all PCIe devices, has resulted in a large amount of AER timeout errors in the kernel log for boards which utilize the rt8169 for on-board Ethernet (e.g., google/beltino). While performance is not impacted, the errors do accumulate. To mitigate this, guard AER enablement via Kconfig, select it by default (as to maintain current default behavior), and allow boards which need to disable it to do so (implemented in subsequent commits). This implementation is derived from that in soc/intel/broadwell. Test: build/boot google/beltino variants with AER disabled (CB:46136), verify dmesg log free of AER timeout errors. [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=671646c151d492c3846e6e6797e72ff757b5d65e [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a99790bf5c7f3d68d8b01e015d3212a98ee7bd57 Change-Id: Ia03ef0d111335892c65122954c1248191ded7cb8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46133 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08lynxpoint/broadwell: Relegate IOBP printk to BIOS_SPEWAngel Pons
There's no need to make so much noise when writing IOBP registers. Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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