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2013-06-12usbdebug: Drop printk within console_init()Kyösti Mälkki
In case with EARLY_CONSOLE, this printk is called before any other console is configured to transmit data. This outputs garbage on CONSOLE_SERIAL as baudrate is not yet programmed. For case without EARLY_CONSOLE, the order in which different console drivers initialize is obscure. Might sometimes work properly. Change-Id: I3792161e0a6dc17e17262048cc9136044dd69dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3384 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12Fix i82801a/b/c/d IOAPICKyösti Mälkki
Setting IRQ delivery to FSB got lost in the rebase process for commit e6143531. I captured following error on dmesg and this patch fixes it for i82801dx. ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 ..MP-BIOS bug: 8254 timer not connected to IO-APIC ...trying to set up timer (IRQ0) through the 8259A ... ..... (found apic 0 pin 2) ... ....... failed. ...trying to set up timer as Virtual Wire IRQ... ..... works. Change-Id: I0768976cc6b0deab213ad9bd4771e0f278de634c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3371 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12intel/*/smi.c: Output correct GPIO in ALT_GP_SMI_STS register dumpKonstantin Aladyshev
Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to GPIO0. Change-Id: I661ce56d9373887270ba3c0518892fbbe6d9de7c Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/3436 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11intel/bd82x6x/Makefile.inc: Revert duplicate addition of `usb_debug.c`Paul Menzel
Currently in Intel BD82x6x southbridge’s `Makefile.inc` the file `usb_debug.c` is added twice to the build. This was introduced in commit 4063ede3fb571110c3e65c321049cc2687cc54fa Author: Ronald G. Minnich <rminnich@google.com> Date: Mon Feb 4 20:31:51 2013 -0800 bd82x6x: Fix compiling with USB debug port support Reviewed-on: http://review.coreboot.org/2784 but was unneeded because it had been already added in the following commit. commit 4141993536039e0d45caeacb745a89d388f0724b Author: Sven Schnelle <svens@stackframe.org> Date: Sat Jul 28 08:52:44 2012 +0200 bd82x6x: Fix CONFIG_USBDEBUG Reviewed-on: http://review.coreboot.org/1376 Therefore basically revert that hunk. There is no policy on how to order these additions, so leave it to a possible separate commit, unifying this. Kyösti Mälkki suspects that these additions were meant for the Intel Lynx Point [1]. [1] http://review.coreboot.org/#/c/3424/ Change-Id: Iaa8de6fcc0d6f3a0a92a28fcb603d7777aa8b24c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3425 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11Fix cycle error in intel southbridges to display GPI statusKonstantin Aladyshev
Fix obvious mistake in cycle that displays GPI status I hope i found all duplicates of it. Change-Id: Ic21ff3ecab85953463e5c23daf808dd5edc82ff8 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/3435 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-10early_smbus: Add early SMBus implementation for VIA chipsetsAlexandru Gagniuc
Add a common implementation of SMBus functionality for early chipsets. Note however, that existing via chipsets are not ported to this code. Porting will require hardware testing to make sure everything is fine. This code is used in the VIA VX900 branch. Change-Id: If5ad8cd0942ac02d358a0139967e7d85d395660f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/144 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-06intel/bd82x6x: Add option to include ethernet firmwareNico Huber
Change-Id: Idf804ed29a67bad732df19e6981f74c8d0c354b5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06intel/bd82x6x: fix building usb debug on SNB/IVBPatrick Georgi
Change-Id: Ica3afbf8277cb025251da7af181f8de0d0036b45 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3389 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-03AMD Geode CS5536: downgrade BIOS_ERRChristian Gmeiner
There is no need to use everywhere BIOS_ERR. Change-Id: If33d72919109244a7c3bd96674a4e386c8d1a19e Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3307 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03Intel Lynx Point: LPC: Unify I/O APIC setupPaul Menzel
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3182 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-03Intel BD82x6x: LPC: Unify I/O APIC setupPaul Menzel
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3183 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-20AMD AGESA Hudson: Include `stdint.h` and `io.h` to fix buildPaul Menzel
Apparently the files `smbus.{h,c}`, where never used and therefore build beforehand. Needing one function in them for the ASUS F2A85-M the build fails as some headers are missing. Including the headers `stdint.h` and `io.h` fixes the following errors. […] CC southbridge/amd/agesa/hudson/smbus.romstage.o In file included from src/southbridge/amd/agesa/hudson/smbus.c:23:0: src/southbridge/amd/agesa/hudson/smbus.h:67:24: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:67:43: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:67:55: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:25: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:44: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:56: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:68:69: error: unknown type name 'u8' src/southbridge/amd/agesa/hudson/smbus.h:69:24: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:69:43: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:70:24: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:70:43: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:70:55: error: unknown type name 'u8' src/southbridge/amd/agesa/hudson/smbus.h:71:20: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:35: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:49: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:59: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:71:69: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:20: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:35: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:49: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:72:59: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:20: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:32: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:44: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.h:73:54: error: unknown type name 'u32' src/southbridge/amd/agesa/hudson/smbus.c: In function 'smbus_delay': src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'outb' [-Werror=implicit-function-declaration] src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'inb' [-Werror=implicit-function-declaration] […] Probably all the (AMD(?)) `smbus.{h,c}` suffer from this and should be fixed. Even better, as these function do not differ between most boards, the file should be moved out from the specific southbridge directories. [1] http://qa.coreboot.org/job/coreboot-gerrit/6168/testReport/junit/(root)/board/i386_asus_f2a85_m/ Change-Id: I285101fa06a365da44fa27b688c536e614d57f50 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3202 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-05-20ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt casePaul Menzel
Currently the code in the if statement if (!byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); only gets executed if `byte == 0x0`, that means only in the default case where RAM voltage is 1.5 Volts. But the RAM voltage should be changed when configured for the non-default case. So negate the predicate to alter the RAM voltage for the non-default cases. To prevent the build error OBJCOPY cbfs/fallback/coreboot_ram.elf coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main': /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte' collect2: error: ld returned 1 exit status make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1 add `southbridge/amd/agesa/hudson/smbus.c` providing the function `do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can actually be used after the needed header files are included in a previous commit. Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6 Reported-by: David Hubbard <david.c.hubbard+coreboot@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3200 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-10Get rid of a number of __GNUC__ checksStefan Reinauer
In the process of streamlining coreboot code and getting rid of unneeded ifdefs, drop a number of unneeded checks for the GNU C compiler. This also cleans up x86emu/types.h significantly by dropping all the duplicate types in there. Change-Id: I0bf289e149ed02e5170751c101adc335b849a410 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3226 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-10Drop prototype guarding for romccStefan Reinauer
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-07Intel 82801Gx: LPC: Unify I/O APIC setupPaul Menzel
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. As commented by Aaron Durbin, a separate `i82801gx_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3181 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-03Intel Lynx Point: Use 2 << 24 to clarify that I/O APIC ID is 2Paul Menzel
Commit »haswell: Add initial support for Haswell platforms« (76c3700f) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/2616 [2] http://review.coreboot.org/3100 Change-Id: I28f9e90856157b4fdd9a1e781472cc4f51d25ece Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3123 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-01AMD Hudson A55E: Remove GEC firmware blob kconfig promptBruce Griffith
The "gigabit ethernet controller" (GEC) block was added to AMD Hudson A55E to integrate ethernet capabilities into an AMD southbridge. The GEC is designed to work with B50610 and B50610M gigabit PHY chips from Broadcom. These parts may not be generally available in small quantities for embedded development. The GEC block requires an opaque firmware blob to function. The GEC blob is controlled by AMD and Broadcom and is not available from coreboot.org. This change removes GEC support from AMD Parmer and AMD Thatcher mainboards since these boards do not have the Broadcom PHY. AMD has requested that the GEC be hidden for Hudson FCH since the PHY parts are not generally available. This Kconfig option can make it appear that this is a viable and supported way to add Ethernet to an embedded board. It is possible to use the Hudson GEC block with other PHYs, but this requires development of a custom GEC blob and a custom Ethernet driver. A custom GEC blob has been developed for a Micrel PHY, but there is no accompanying driver. Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3127 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-26Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2Paul Menzel
Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f5560015ab9905f1ccc2e08c73e0 [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3122 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18AMD/SB800: Define the GPP PCIe lane distributionDave Frodin
Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports. This fix was verified by openvoid on a AsRock E350M1 motherboard. Change-Id: I0116c5f518e0d000be609013446e53da4112f586 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/3104 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2Vladimir Serbinenko
Commit »Add support for Intel Panther Point PCH« (8e073829) [1] used `1 << 25` to set the APIC ID of 2. Using `2 << 24`, which is the same value, instead makes it clear, that the APIC ID is 2. [1] http://review.coreboot.org/853 Change-Id: I5044dc470120cde2d2cdfc6e9ead17ddb47b6453 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3100 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-15Fam14 DSDT: Also return for unrecognized UUID in _OSCMike Loptien
Fixing warnings introduced by the following patches: http://review.coreboot.org/#/c/2684/ http://review.coreboot.org/#/c/2739/ http://review.coreboot.org/#/c/2714/ These patches were meant to fix the dmesg warning about the OSC method not granting control appropriately. These patches then introduced warnings during the coreboot build process which were missed during the patch submission process. These warnings are below: Intel ACPI Component Architecture ASL Optimizing Compiler version 20100528 [Oct 15 2010] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0a dsdt.ramstage.asl 1143: Method(_OSC,4) Warning 1088 - ^ Not all control paths return a value (_OSC) dsdt.ramstage.asl 1143: Method(_OSC,4) Warning 1081 - ^ Reserved method must return a value (Buffer required for _OSC) ASL Input: dsdt.ramstage.asl - 1724 lines, 34917 bytes, 889 keywords AML Output: dsdt.ramstage.aml - 10470 bytes, 409 named objects, 480 executable opcodes Compilation complete. 0 Errors, 2 Warnings, 0 Remarks, 494 Optimizations This patch gives the following compilation status: Intel ACPI Component Architecture ASL Optimizing Compiler version 20100528 [Oct 1 2012] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0a ASL Input: dsdt.ramstage.asl - 1732 lines, 33295 bytes, 941 keywords AML Output: dsdt.ramstage.aml - 10152 bytes, 406 named objects, 535 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 432 Optimizations The fix is simply adding an Else statement to the If which checks for the proper UUID. This way, all outcomes will return a full control package. This patch has no effect on the dmesg output. Change-Id: I8fa246400310b26679ffa3aa278069d2e9507160 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-11AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in commentPaul Menzel
Reading the paste of code in a message to the mailing list [1], a typo was spotted and found in one more place. $ git grep egnoring src/southbridge/amd/rs780/cmn.c: * egnoring the reversal case src/southbridge/amd/sr5650/sr5650.c: * egnoring the reversal case These typos are there since when the code was committed and are now corrected. [1] http://www.coreboot.org/pipermail/coreboot/2013-April/075644.html Change-Id: I55c65f71e4834f209b60d678f0d44bc2f4217099 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3062 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-11Persimmon/Fam14/SB800 DSDT: Split into common areasMike Loptien
Split the Persimmon DSDT into common code areas. For example, split the Southbridge specific code into the Southbridge directory and CPU specific code into the CPU directory. Also adding the superio.asl file to the Persimmon DSDT tree. This file is empty for the moment but will be necessary in the future. I have also emptied the thermal.asl file in the mainboard directory because it does not seem to perform as intended (fan control does not change when it is brought back into the code base) and it has been inside a '#if 0' statement for a long time. Removing it until it is decided that it is actually necessary. This change was verified in three different ways: 1. Visual comparison of the compiled DSDT pulled from the Persimmon after booting into Linux using the ACPI tools acpidump, acpixtract, and iasl. The comparison was done between the DSDT before and after doing the split work. This test is somewhat difficult considering the expanse of the changes. Blocks of code have been moved, and others changed. 2. Linux logs were dumped before and after the DSDT split. Logs dumped and compared include dmesg and lspci -tv. Neither log changed significantly between the two compare points. 3. The test suite FWTS was run on the Coreboot build both before and after doing the DSDT split with the command 'sudo fwts -b -P -u'. The flag -b specifies all batch jobs, -P specifies all power tests, and -u specifies utilities. Interactive jobs were not run as most of them consist of laptop checks. Again, there were no significant changes between the two endpoints. These tests lead me to believe that there was no change in the functionality of the ACPI tables apart from what is known and expected. This patch is the first of a series of patches to split the DSDT. The ASRock patch was merged before this one and breaks the ASROCK E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/). Please be aware of this dependency when pulling these patches. Other patches that depend on this patch are 'AMD Fam14: Split out the AMD Fam14 DSDT' (http://review.coreboot.org/#/c/3051/) and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC' (http://review.coreboot.org/#/c/3052/) Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/3048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-03lynxpoint: Cosmetic cleanupStefan Reinauer
src/southbridge/intel/lynxpoint/pmutil.c was committed with two things that needed fixing. Change-Id: Ib83343a75840aa29847b607b0275971eb8140f12 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3003 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-04-01lynxpoint: Move ACPI NVS into separate CBMEM tableDuncan Laurie
The ACPI NVS region was setup in place and there was a CBMEM table that pointed to it. In order to be able to use NVS earlier the CBMEM region is allocated for NVS itself during the LPC device init and the ACPI tables point to it in CBMEM. The current cbmem region is renamed to ACPI_GNVS_PTR to indicate that it is really a pointer to the GNVS and does not actually contain the GNVS. Change-Id: I31ace432411c7f825d86ca75c63dd79cd658e891 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2970 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01lynxpoint: Basic configuration of SerialIO devicesDuncan Laurie
This adds configuration of SerialIO devices in the Lynxpoint-LP chipset. This includes DMA, I2C, SPI, UART, and SDIO controllers. There is assorted magic setup necessary for the devices and while it is similar for each device there are subtle differences in some register settings. These devices must be put into "ACPI Mode" in order to take advantage of S0ix. When in ACPI mode the allocated PCI BARs must be passed to ACPI so it can be relayed to the OS. When the devices are in ACPI mode BAR0+BAR1 is saved into ACPI NVS and then updated and returned when the OS calls _CRS. Note that is is not entirely complete yet. We need to update the IASL compiler in our build environment to support ACPI 5.0 in order to be able to pass the FixedDMA entries to the kernel. There are also no ACPI methods defined yet to do D0->D3->D0 transitions for actually entering/exiting S0ix states. This is hard to test right now because our kernel does not support any of these devices in ACPI mode. I was able to build and test the upstream bleeding-edge branch of the linux-pm git tree. With that tree I was able to enumerate and load the driver for the DesignWare I2C driver and attempt to probe the I2C bus -- although there are no devices attatched. I am also able to see the resources from ACPI in /proc/iomem get reserved properly in the kernel. Change-Id: Ie311addd6a25f3b7edf3388fe68c1cd691a0a500 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2971 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01lynxpoint: Fix LP clock gating setup for LPCDuncan Laurie
This bit offset is incorrect and should only be set based on another bit in a different register. Change-Id: I6037534236e3a4a5d15e15011ed9b5040b435eaf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2973 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01lynxpoint: fix enable_pm1() functionAaron Durbin
The new enable_pm1() function was doing 2 things wrong: 1. It was doing a RMW of the pm1 register. This means we were keeping around the enables from the OS during S3 resume. This is bad in the face of the RTC alarm waking us up because it would cause an infinite stream of SMIs. 2. The register size of PM1_EN is 16-bits. However, the previous implementation was accessing it as a 32-bit register. The PM1 enables should only be set to what we expect to handle in the firmware before the OS changes to ACPI mode. Change-Id: Ib1d3caf6c84a1670d9456ed159420c6cb64f555e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2978 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01lynxpoint: split clearing and enabling of smmAaron Durbin
Previously southbridge_smm_init() was provided that did both the clearing of the SMM state and enabling SMIs. This is troublesome in how haswell machines bring up the APs. The BSP enters SMM once to determine if parallel SMM relocation is possible. If it is possible the BSP releases the APs to do SMM relocation. Normally, after the APs complete the SMM relocation, the BSP would then re-enter the relocation handler to relocate its own SMM space. However, because SMIs were previously enabled it is possible for an SMI event to occur before the APs are complete or have entered the relocation handler. This is bad because the BSP will turn off parallel SMM save state. Additionally, this is a problem because the relocation handler is not written to handle regular SMIs which can cause an SMI storm which effectively looks like a hung machine. Correct these issues by turning on SMIs after all the SMM relocation has occurred. Change-Id: Id4f07553b110b9664d51d2e670a14e6617591500 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2977 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01AMD hudson & SB800 - Fix issues with mawkMartin Roth
When calculating the offsets of the various binary blobs within the coreboot.rom file, we noticed that using mawk as the awk tool instead of using gawk led to build issues. This was finally traced to the maximum value of the unsigned long variables within mawk - 0x7fff_ffff. Because we were doing calculations on values up in the 0xffxxxxxx range, these numbers would either be turned into floating point values and printed using scientific notation, or truncated at 0x7fff_ffff. To fix this, we print the values out as floating point, with no decimal digits. This works in gawk, mawk, and original-awk and as the testing below show, seems to be the best way to do this. printf %u 0xFFFFFFFF | awk '{printf("%.0f %u %d", $1 , $1 , $1 )}' mawk: 4294967295 2147483647 2147483647 original-awk: 4294967295 2147483648 4294967295 gawk: 4294967295 4294967295 4294967295 The issue of %d not matching gawk and original-awk has been reported to ubuntu. In the future, I'd recommend that whenever awk is used, a format is specified. It doesn't seem that we can count on the representation being the same between the different versions. Change-Id: I7b6b821c8ab13ad11f72e674ac726a98e8678710 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2628 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-01lynxpoint: Rework ACPI NVS to add new SerialIO variablesDuncan Laurie
This reclaims space in ACPI NVS by removing unused fields and adds new fields for SerialIO BARs which will be used to communicate the allocated resources to ACPI. Change-Id: I002bf396cf7b495bc5b7e54b741527e507aff716 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2969 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-29AMD CIMx SB800: Update Kconfig help texts to new SATA mode defaultPaul Menzel
In the following commit commit ee5c111755ac4acc6dfb6e10a4e271211e149a39 Author: Paul Menzel <paulepanter@users.sourceforge.net> Date: Tue Mar 12 12:41:40 2013 +0100 AMD CIMx SB800: Enable AHCI mode for SATA controller by default Reviewed-on: http://review.coreboot.org/2661 I forgot to update the help texts to the new SATA mode default. Do so now. Additionally note that help texts for `choice` do not seem to be shown. Change-Id: I17f401633a2136efca2b21a621482e0724ff9f04 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2936 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22Unify setting i82801e LPCKyösti Mälkki
Make it more similar to i82801d LPC init. Change-Id: I7b32747ee8012c220c8628994d749999c144b716 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2545 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-22Fix compilation of Intel LynxPoint based boardsStefan Reinauer
The haswell patches that verified correctly were not yet submitted, but verified correctly. However they still used romcc_io.h which was dropped in another patch earlier today. With a lot of development happening in parallel, this is unfortunately nothing that the gerrit 2.6 Rebase If Necessary submit type could have fixed. Change-Id: Ifef9ae05b22c408e78d6cff37defd68e4ed91ed9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2876 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-03-22romstage: add support for vboot firmware selectionAaron Durbin
This patch implements support for vboot firmware selection. The vboot support is comprised of the following pieces: 1. vboot_loader.c - this file contains the entry point, vboot_verify_firmware(), for romstage to call in order to perform vboot selection. The loader sets up all the data for the wrapper to use. 2. vboot_wrapper.c - this file contains the implementation calling the vboot API. It calls VbInit() and VbSelectFirmware() with the data supplied by the loader. The vboot wrapper is compiled and linked as an rmodule and placed in cbfs as 'fallback/vboot'. It's loaded into memory and relocated just like the way ramstage would be. After being loaded the loader calls into wrapper. When the wrapper sees that a given piece of firmware has been selected it parses firmware component information for a predetermined number of components. Vboot result information is passed to downstream users by way of the vboot_handoff structure. This structure lives in cbmem and contains the shared data, selected firmware, VbInitParams, and parsed firwmare components. During ramstage there are only 2 changes: 1. Copy the shared vboot data from vboot_handoff to the chromeos acpi table. 2. If a firmware selection was made in romstage the boot loader component is used for the payload. Noteable Information: - no vboot path for S3. - assumes that all RW firmware contains a book keeping header for the components that comprise the signed firmware area. - As sanity check there is a limit to the number of firmware components contained in a signed firmware area. That's so that an errant value doesn't cause the size calculation to erroneously read memory it shouldn't. - RO normal path isn't supported. It's assumed that firmware will always load the verified RW on all boots but recovery. - If vboot requests memory to be cleared it is assumed that the boot loader will take care of that by looking at the out flags in VbInitParams. Built and booted. Noted firmware select worked on an image with RW firmware support. Also checked that recovery mode worked as well by choosing the RO path. Change-Id: I45de725c44ee5b766f866692a20881c42ee11fa8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Fix up handling for LynxPoint-LP chipsetsDuncan Laurie
This configures power management registers according to the 1.2.0 reference code drop. There are many inconsistencies with the documentation and I tried to note those with ?. This does not do the same for LynxPoint-H yet. Change-Id: I9b8f5c24a8b0931075a44398571c9b0d54cce6a6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2819 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Change sata.c to get rid of #ifDuncan Laurie
This uses the new helper function added earlier. Change-Id: Icdb5d5c51f70eeb7e39e11062276ceb3eb3d9473 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2818 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Fix ELOG logging of power management eventsDuncan Laurie
This is updated to handle LynxPoint-H and LynxPoint-LP and a new wake event is added for the power button. Boot, suspend/resume, reboot, etc on WTM2 and then check the event log to see if expected events have been added. Change-Id: I15cbc3901d81f4fd77cc04de37ff5fa048f9d3e8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2817 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21haswell/lynxpoint: Use new PCH/PM helper functionsDuncan Laurie
This makes use of the new functions from pmutil.c that take care of the differences between -H and -LP chipsets. It also adds support for the LynxPoint-LP GPE0 register block and the SMI/SCI routing differences. The FADT is updated to report the new 256 byte GPE0 block on wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address block so that part is zeroed to prevent IASL and the kernel from complaining about a mismatch. This was tested on WTM2. Unfortunately I am still unable to get an SCI delivered from the EC but I suspect that is due to a magic command needed to put the EC in ACPI mode. Instead I verified that all of the power management and GPIO registers were set to expected values. I also tested transitions into S3 and S5 from both the kernel and by pressing the power button at the developer mode screen and they all function as expected. Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2816 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Fix GPIO and PM base reservationsDuncan Laurie
The kernel ACPI was not happy with the Add inside a ResourceTemplate (or perhaps within the IO declaration) Instead make a buffer of IO reservations and turn _CRS into a method that updates the buffer depending on the chipset type. This adds an \ISLP() method that checks the chipset LPC device ID to see if it is -LP or -H. It also increases the PM base reservation to 256 bytes and moves both GPIO and PM base to above 0x1000 on -LP chipsets. Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2815 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: remove DEBUG_PERIODIC_SMISDuncan Laurie
This was put in for debugging and experimentation on i945 and has been copied around since. Drop it from lynxpoint. Change-Id: I0b53f4e1362cd3ce703625ef2b4988139c48b989 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2814 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Add power management helper functionsDuncan Laurie
There are subtle yet significant differences in some of the registers in the power management region between LynxPoint-H and LynxPoint-LP. In order to reduce code that is accessing these registers and would need special cases this adds a number of helper functions that can be used in both ramstage and SMM. This commit just adds the new functions, subsequent commits will start to use them. Change-Id: I411da75da519f5b3198a408078cbf3114e426992 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2813 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Add helper functions for reading PM and GPIO baseDuncan Laurie
These base addresses are used in several places and it is helpful to have one location that is reading it. Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2812 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Add function for checking for LP chipsetDuncan Laurie
Add a helper function pch_is_lp() that will return 1 if the current chipset is of the new "low power" variant used with Haswell ULT. Additionally these functions are added to SMM so it can be used there. Change-Id: I9acdea2c56076cd8d9627aba66cf0844c56a38fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2811 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: Enable EC IO ports 0x62/0x66Duncan Laurie
In order to be able to talk to an EC via standard path. Change-Id: I3fe76882dec9a0596cbc1c844afa2ddb03ed771c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2810 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21lynxpoint: update MBP give up routineAaron Durbin
I'm not sure if I screwed this up originally or the Intel docs changed (I didn't bother to go back and check). According to ME BWG 1.1.0 the give up bit is in the host general status #2 register. Change-Id: Ieaaf524b93e9eb9806173121dda63d0133278c2d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2808 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-21LynxPoint: Move RCBA helper function to its own fileDuncan Laurie
So it can get used in both romstage and ramstage. Change-Id: Ief9eaafdd91df2a7b668de1a9b83aea3af3ff894 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2802 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-19lynxpoint: Add cbfs_load_payload() implementationAaron Durbin
SPI accesses can be slow depending on the setup and the access pattern. The current SPI hardware setup to cache and prefetch. The alternative cbfs_load_payload() function takes advantage of the caching in the CPU because the ROM is cached as write protected as well as the SPI's hardware's caching/prefetching implementation. The CPU will fetch consecutive aligned cachelines which will hit the ROM as cacheline-aligned addresses. Once the payload is mirrored into RAM the segment loading can take place by reading RAM instead of ROM. With the alternative cbfs_load_payload() the boot time on a baskingridge board saves ~100ms. This savings is observed using cbmem.py after performing warm reboots and looking at TS_SELFBOOT_JUMP (99) entries. This is booting with a depthcharge payload whose payload file fits within the SMM_DEFAULT_SIZE (0x10000 bytes). Datapoints with TS_LOAD_PAYLOAD (90) & TS_SELFBOOT_JUMP (99) cbmem entries: Baseline Alt -------- -------- 90:3,859,310 (473) 90:3,863,647 (454) 99:3,989,578 (130,268) 99:3,888,709 (25,062) 90:3,899,450 (477) 90:3,860,926 (463) 99:4,029,459 (130,008) 99:3,890,583 (29,657) 90:3,834,600 (466) 90:3,890,564 (465) 99:3,964,535 (129,934) 99:3,920,213 (29,649) Booted baskingridge many times and observed 100ms reduction in TS_SELFBOOT_JUMP times (time to load payload). Change-Id: I27b2dec59ecd469a4906b4179b39928e9201db81 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2783 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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