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2012-02-02i3100: configure pci irqsSven Schnelle
without it, you can't boot from PCI devices like scsi controllers which require an interrupt set. So preconfigure all pci devices. Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/603 Tested-by: build bot (Jenkins)
2012-02-02CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dirKerry Sheh
AGESA and CIMX build changed from commit 2a830d0b, sb800 and sb900 CIMX dir already traversed in vendorcode Makefile. Change-Id: I5101b22e140725337bf5074b9170e582c8e3bf40 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/602 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-01-31i3100: add sata_ports_implemented optionSven Schnelle
BIOS needs to set the bit mask which ports are iplemented on the board. Without setting this option, seabios fails to boot from SATA. Change-Id: I21de3fde3a9cff7c590226f70fa549274f36e2a8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/601 Tested-by: build bot (Jenkins)
2012-01-31i3100: Add init sequenceSven Schnelle
i3100 misses the magic SATA init sequence, which makes all requests fail. Captured from the vendor BIOS, which writes those bits on all configurations. Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/600 Tested-by: build bot (Jenkins)
2012-01-18Add subsystem callbacks for VT8237x and VT890 family of chipsetsRudolf Marek
Change-Id: Id34615f0c229d276d72cdf984cf82ea8cc1a85bb Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/523 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-18Unify ID_SECTION_OFFSET and mark it deprecatedPatrick Georgi
We used to put the id section at -0x10, with some boards overriding this to avoid collisions with romstraps. Hardcode the location at -0x80, at the possible expense of some space (0x70 bytes). This also makes the section easier to find in a binary image. At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option is moved to src/Kconfig.deprecated_options. Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/549 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-01-10Add missing HAVE_HARD_RESETSven Schnelle
Change-Id: I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/531 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-01-08rs780: correct comment in switching_gpp_configurations()Jonathan A. Kollasch
Change-Id: I6417a92523eea7307d080669fbc4e16ee28c8a6c Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/524 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-05rs780: use bitwise rather than boolean notJonathan A. Kollasch
Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/518 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-01-05rs780: power down GPPSB SB lane pads in correct PCIe coreJonathan A. Kollasch
Change-Id: I059d5b155cae051f31cc2495f8a47d53e01af808 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/519 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-21Persimmon audio codec verb patch.Marc Jones
Verb data is required for the HDA audio codec in the sb800 southbridge. Verb data is not required for mainboards that use G-Series HDMI. It is also a setting the may be boards specific. This fixes issues with Windows audio on Persimmon. Change-Id: I067506871e92078d122cf79872363d8937d47e50 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/490 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-06Fix AMD 8132 and 8151 southbridge buildsKyösti Mälkki
Untested, changes ramstage build for boards: supermicro/h8qme_fam10 amd/serengeti_cheetah amd/serengeti_cheetah_fam10 AMD 8132 was not built for any mainboard due to a typo. AMD Serengeti Cheetah: Chip 8151 is referenced in devicetree.cb but was not built. AMD Serengeti Cheetah Family10: There are indications the board has 8151, but it is not listed in the devicetree.cb. The 8151 chip is not added in the build. Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/471 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-12-05RS780: print the vgainfoDenis 'GNUtoo' Carikli
With this commit the vgainfo is printed and looks like that on the serial console: vgainfo: ulBootUpEngineClock:50000 ulBootUpUMAClock:66700 ulBootUpSidePortClock:0 ulMinSidePortClock:0 ulSystemConfig:0 ulBootUpReqDisplayVector:0 ulOtherDisplayMisc:0 ulDDISlot1Config:0 ulDDISlot2Config:0 ucMemoryType:0 ucUMAChannelNumber:1 ucDockingPinBit:0 ucDockingPinPolarity:0 ulDockingPinCFGInfo:0 ulCPUCapInfo: 2 usNumberOfCyclesInPeriod:0 usMaxNBVoltage:0 usMinNBVoltage:0 usBootUpNBVoltage:0 ulHTLinkFreq:20000 usMinHTLinkWidth:8 usMaxHTLinkWidth:8 usUMASyncStartDelay:100 usUMADataReturnTime:300 usLinkStatusZeroTime:600 ulHighVoltageHTLinkFreq:20000 ulLowVoltageHTLinkFreq:20000 usMaxUpStreamHTLinkWidth:8 usMaxDownStreamHTLinkWidth:8 usMinUpStreamHTLinkWidth:8 usMinDownStreamHTLinkWidth:8 Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/456 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02make GPIOs and misc configurable via devicetreeFlorian Zumbiehl
Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/387 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02make INT[EFGH]# of vt8237 configurable as gpio via devicetreeFlorian Zumbiehl
Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/386 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02some black magic for initializing the old version of the k8t800Florian Zumbiehl
Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/388 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02implement usb2 termination and dpll delay setting for vt8237rFlorian Zumbiehl
Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/385 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02i3100: Add HAVE_HARD_RESETSven Schnelle
and remove it from mainboard/intel/mtarvon, as this function is implemented in the southbridge code. Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-24vt8237: add support for setting the power state after loss of powerFlorian Zumbiehl
Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/437 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-10compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLDFlorian Zumbiehl
make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/374 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-10support for different location of HT registers in old version of K8T800Florian Zumbiehl
Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/373 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-08move function from header file to .c fileStefan Reinauer
http://review.coreboot.org/#change,378 introduced a function in k8x8xx.h move this function to ctrl.c and add a prototype to the header file instead. Change-Id: I0919ffb2030c53669b95f58b649d4a160f660923 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/429 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-07rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessibleFlorian Zumbiehl
Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/379 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-07factor out common config for k8x8xx's dram_enable() and vt8237r_cfg()Florian Zumbiehl
Instead of writing to config registers in k8x8xx's dram_enable() and reading those back in vt8237r_cfg(), factor out generation of the values and reuse that in both places. Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/378 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-07add support for 1106:3188 (host controller of the old version of k8t800)Florian Zumbiehl
Change-Id: Id61678f03e1f7d964f7180a062dd6a689852d4ac Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/401 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-07in vt8237r_enable(), write function enables only to ISA bridge config spaceFlorian Zumbiehl
vt8237r_enable() so far wrote the function enable values to the same offset in the config space of every one of the vt8237's functions, even though the register is located in the ISA bridge only. Change-Id: I639586dc238132f5b8d2f320b794948718281b9c Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/368 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-04Revert "add support for 1106:3188 (host controller of the old version of ↵Patrick Georgi
k8t800)" due to dependency issues. This reverts commit 68c554550f59bd96caace96260ae2e30ed55ceb4 Change-Id: I353bd36b008f489a972c7c656d7ad07416f01387 Reviewed-on: http://review.coreboot.org/398 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-03add support for writing to SMBus with vt8237Florian Zumbiehl
Change-Id: I70fe072f8f3447d0be7b7ac64508a954fe47091d Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/372 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-03add support for 1106:3188 (host controller of the old version of k8t800)Florian Zumbiehl
Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/381 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-31Fix usb debug dongle supportSven Schnelle
- move enable_usbdebug() declaration to usbdebug.h - reinitialize debug driver in ramstage, as copying the data structure from romstage doesn't work right now. This way of copying data from romstage to ramstage is really board/cpu specific, and is likely to break often. So don't do it. Change-Id: I394678ded6679c1803e29eb691b926182bdcab68 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/355 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-30Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.Stefan Reinauer
Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/360 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28sb600: Implement EHCI workaroundPatrick Georgi
Linux implements it itself, but older Linuxes and other systems might not. Without this, the host controller might not respond to drivers. Change-Id: I4ff0e3683c02e7aa00d188428847c64c4c5d589d Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/345 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27Added smbus block read/write for amd8111Oskar Enoksson
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc Reviewed-on: http://review.coreboot.org/281 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27i82801gx: Fix port status in AHCI modeSven Schnelle
The code used PCI register 0x92 to enable sata ports, which is wrong. The ICH7 documentation states: "This register is only used in systems that do not support AHCI. In AHCI enabled systems, bits[3:0] must always be set (ICH7R only) / bits[2,0] must always be set (Mobile only), and the status of the port is controlled through AHCI memory space." Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write 0x0f for both variants. This patch makes sata_ahci work on my Thinkpad T60 and X60s. Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/340 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25i82801gx: Add setting for C4onC3 modeSven Schnelle
If this bit is set, ich7 will enter C4 mode if possible instead of C3. See ich7 specification (LPC controller, Power management control registers) for more details. Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25i82801gx: Add write and read/write block functionsSven Schnelle
Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/326 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-23i82801gx: Don't set I/O base address to static valueSven Schnelle
Doing it this way will break all subsequent smbus calls, because the smbus code still uses res->base, which points to the old base address. Fix this by allocating a proper resource. Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/325 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2011-10-23SB800: Hide unused gpp portsKerry Sheh
Add configure option SB_GPP_UNHIDE_PORTS for mainboard to hide/unhide the unused sb800 gpp ports. Certain gpp port should be hidden, if no device was detected and hotplug feature is disabled for such port. Hidden unused ports makes lspci -vvv get more accurate information under Linux. Test on avalue/eax-785e mainboard. Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-21sch: strip quotes around cmc.bin filenamePatrick Georgi
This was mentioned several times already, how about we get it in? It avoids cbfstool to fail because path/to/"file" doesn't work. Change-Id: Ia01acbd78f81a5db890fd1573a2f3cbe1450562f Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/305 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-20i82801dx: Replace romstage printk'sKyösti Mälkki
Patch is required to compile this with romcc. Change-Id: I5c4c0f5b32e5edeb8c48d8455b3493ca79f8b452 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/291 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-15AMD CPU and chipset fixes for compilation with gcc 4.6Stefan Reinauer
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/266 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15use acpi.h include instead of manually adding acpi_slp_type.Stefan Reinauer
Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/276 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6Stefan Reinauer
Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/268 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-13Use default table creator macro for all SSDTsStefan Reinauer
Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/262 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13amd/sb600: Enable COM2 at all times in early setupPatrick Georgi
Otherwise with a coreboot log on COM2 (which doesn't work) the boot process takes eons. Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/241 Reviewed-by: Marc Jones <marcj303@gmail.com> Tested-by: build bot (Jenkins)
2011-10-12SB800 RAID: add kconfig option RAID_MISC_ROM_POSITIONKerry Sheh
SB800 RAID ROM require to put the misc ROM to specific position, this patch enable user to put the RAID misc ROM to the right place in the coreboot image. Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1 Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/249 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12SB800: Sata Enable bus master and enable ahci for AHCI/RAID modeKerry Sheh
In order to make sure AHCI/RAID ROM works correctly For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should enable bus master and the ahci also should be enabled. Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200 Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/248 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12sb800: Add Kconfig option ENABLE_IDE_COMBINED_MODEKerry Sheh
Add this option to enable/disable SATA IDE Combined Mode feature Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/231 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
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