Age | Commit message (Expand) | Author |
2016-08-08 | chromeos chipsets: select RTC usage | Aaron Durbin |
2016-08-04 | sb/amd/sb700: Do not reset fifo after skipping the sent bytes | Timothy Pearson |
2016-08-03 | sb/amd/sb[6|7|8]00: Initialize PIC | Timothy Pearson |
2016-08-02 | intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano | Prabal Saha |
2016-08-01 | Remove non-ascii & unprintable characters | Martin Roth |
2016-08-01 | Add newlines at the end of all coreboot files | Martin Roth |
2016-07-31 | sis/sis966: fix typo | Patrick Georgi |
2016-07-31 | sis/sis966: don't store a 32bit value in a 16bit variable | Patrick Georgi |
2016-07-31 | src/southbridge: Capitalize CPU, RAM and ROM | Elyes HAOUAS |
2016-07-31 | Remove extra newlines from the end of all coreboot files. | Martin Roth |
2016-07-30 | chromeos mainboards: remove chromeos.asl | Aaron Durbin |
2016-07-28 | bootmode: Get rid of CONFIG_BOOTMODE_STRAPS | Furquan Shaikh |
2016-07-21 | timestamp: Drop duplicate TS_END_ROMSTAGE entries | Kyösti Mälkki |
2016-07-15 | southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitions | Aaron Durbin |
2016-07-15 | southbridge/intel/fsp_i89xx: use common Intel ACPI hardware definitions | Aaron Durbin |
2016-07-15 | southbridge/intel/fsp_rangeley: use common Intel ACPI hardware definitions | Aaron Durbin |
2016-07-15 | southbridge/intel/i82801gx: use common Intel ACPI hardware definitions | Aaron Durbin |
2016-07-15 | southbridge/intel/i82801dx: use common Intel ACPI hardware definitions | Aaron Durbin |
2016-07-15 | southbridge/intel/ibexpeak: use common Intel ACPI hardware definitions | Aaron Durbin |
2016-07-15 | southbridge/intel/lynxpoint: use common Intel ACPI hardware definitions | Aaron Durbin |
2016-07-15 | southbridge/intel/bd82x6x: use common Intel ACPI hardware definitions | Aaron Durbin |
2016-07-12 | Documentation: Fix doxygen errors | Martin Roth |
2016-07-06 | PCI: Use PCI_DEVFN macro instead of DEV_FUNC | Werner Zeh |
2016-06-29 | intel romstage: Use run_ramstage() | Kyösti Mälkki |
2016-06-01 | drivers/lenovo: Add hybrid graphics driver | Patrick Rudolph |
2016-05-30 | AMD/spi: Do not reset fifo after skipping the sent bytes | zbao |
2016-05-18 | AGESA vendorcode: Build a common amdlib | Kyösti Mälkki |
2016-05-17 | intel/sch: Merge northbridge and southbridge in src/soc | Stefan Reinauer |
2016-05-09 | drivers/uart: Use uart_platform_refclk for all UART models | Lee Leahy |
2016-05-05 | rdc/r8610: Move to src/soc | Stefan Reinauer |
2016-05-05 | dmp/vortex86ex: Merge northbridge and southbridge into soc | Stefan Reinauer |
2016-05-03 | southbridge/amd: Drop HUDSON_FWM_INSIDE_CBFS | Patrick Georgi |
2016-04-22 | intel/i82801ax: Fix IDE setup console log | Patrick Georgi |
2016-04-13 | southbridge/via: Update license headers | Martin Roth |
2016-04-13 | southbridge/ti: Update license headers | Martin Roth |
2016-04-13 | southbridge/ricoh: Update license headers | Martin Roth |
2016-04-13 | southbridge/nvidia: Update license headers | Martin Roth |
2016-04-11 | sb/amd/sp5100: Apply Sx State Settings per RPR v3.02 | Timothy Pearson |
2016-04-11 | sb/amd/sp5100: Enable CPU reset timing option per RPR v3.02 | Timothy Pearson |
2016-04-11 | sb/amd/sp5100: Disable ASF legacy sensor support per RPR v3.02 | Timothy Pearson |
2016-04-08 | sb/amd/sb700: Add sb7xx_51xx_decode_last_reset() | Timothy Pearson |
2016-04-07 | sb/amd/sb700: Enable reset on sync flood | Timothy Pearson |
2016-04-05 | sb/amd/sp5100: Add ehci_async_data_cache CMOS option | Timothy Pearson |
2016-03-29 | nvidia/ck804/sata: Remove space before newline in debug output | Paul Menzel |
2016-02-23 | southbridge/intel/ibexpeak: Use common gpio.c | Patrick Rudolph |
2016-02-23 | southbridge/intel/lynxpoint: Use common gpio.c | Patrick Rudolph |
2016-02-18 | southbridge/intel/bd82x6x/acpi: Fix IRQ warnings | Patrick Rudolph |
2016-02-18 | southbridge/intel/bd82x6x: Use common gpio.c | Patrick Rudolph |
2016-02-16 | southbridge/intel/common: Add common gpio.c | Patrick Rudolph |
2016-02-12 | Make MRC vs native a config rather than making a separate chipset for it. | Vladimir Serbinenko |