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2019-01-14mb/lenovo/[xtz]60: Introduce and use RCBA64 macroPeter Lemenkov
Change-Id: I85ca631dfb01acb92dd1ac38dff07215114cab8c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/30802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-14sb/intel: Use common RCBA MACROsPeter Lemenkov
This commit follows up on commit 2e464cf3 with Change-Id I61fb3b01ff15ba2da2ee938addfa630c282c9870. Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/29236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-14AGESA binaryPI: Consolidate ACPI for IMCKyösti Mälkki
Change-Id: Ieff6041f3c9ad02f9cebae0ec83d0898abb0d601 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/18538 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14binaryPI: Remove ACPI for IMC we don't runKyösti Mälkki
IMC is used on some of the AMD reference designs, so do not touch them yet. Change-Id: I6a58ab53d4a800d4c0c2026e50826122ece2c59f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/21190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-01-14AGESA: Remove ACPI for IMC we don't runKyösti Mälkki
IMC is used on some of the AMD reference designs, so do not touch them yet. Change-Id: Iae21e0294f0155f07fb4f4348ebc5b3120d50fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/18536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-14AGESA/PI: replace HUDSON_DISABLE_IMC with HUDSON_IMC_ENABLEMike Banon
Only a few boards are using IMC for the onboard fan control, so regarding the availability of IMC selection it should be opt-in, not opt-out. Also, select HUDSON_IMC_ENABLE for Gizmo 2 because Gizmo 2 could use IMC for the onboard fan control. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I3590b13c3b155405d61e373daf1bd82ca8e3bd16 Reviewed-on: https://review.coreboot.org/c/30756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13sb/intel: Check for NULL-return of pcidev_on_root()Nico Huber
In these cases we have to expect a NULL pointer because the IGD device 0:2.0 may be disabled. The behaviour still differs from using dev_find_slot(), which may return a disabled device. Though, if you'd try to read its config space you'd only read garbage (0xff) and in cases where we filled ACPI data with devicetree information, the information shouldn't be interpreted by the OS because of the disabled device. Change-Id: I1bab8fa3a82daca71d03453315cdd69d8951fc24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30879 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCKKyösti Mälkki
This board is the only user of these ancient chipsets, so we'll do all in one go. Also wipe out some extra headers. Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-10sb/nvidia/mcp55: Avoid confusion with PCI_ADDR()Kyösti Mälkki
What you see in the table are not the PCI devices that will be written to. Use a helper MCP55_DEV() to make you look twice what is actually done. Change-Id: I1349af9f734aaabb576d1370ae29a56c91569a7c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10sb/nvidia/ck804: Avoid confusion with PCI_ADDR()Kyösti Mälkki
What you see in the table are not the PCI devices that will be written to. Use a helper CK804_DEV() to make you look twice what is actually done. Change-Id: I0ee244dacd6bbd0a88a5e6a5c634f381b0cf713d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10sb/intel/common: Show "Add EC firmware" only for boards that need itJan Tatje
Most boards currently do not use EC firmware from SPI flash in the IFD, this hides this option by default and shows it only for boards that need it. A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to enable this option for boards that need it. The following list of boards requiring this was provided by Lijian Zhao: 1. intel/cannonlake_rvp 2. intel/coffeelake_rvp 3. intel/icelake_rvp 4. google/sarien 5. google/hatch Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/30697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-10sb/amd/{cimx,sb{7,8}00}: Use PCI_DEVFN()Elyes HAOUAS
Change-Id: I731fd4ecfab679cd3d830a89bc82c56cf9008bc4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-10southbridge/amd/cimx: Drop unused functionsKyösti Mälkki
Leftovers from attempts of using these with native (non-AGESA) amdfam10/15 support code. Change-Id: I8eaed338438e1de5baee462376e339e1439f72f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09southbridge/nvidia/ck804: Drop leftover codeKyösti Mälkki
Code was for romcc romstage. Change-Id: If368610651ce950169ef71d9ed768a509c2a5c5c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09cpu/intel: Use the common code to initialize the romstage timestampsArthur Heymans
The initial timestamps are now pushed on the stack when entering the romstage C code. Tested on Asus P5QC. Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08sb/intel/i82801gx: Autodisable functions based on devicetreeArthur Heymans
This removes the need to synchronize the devicetree and the romstage writing to FD. Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30244 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07intel/lynxpoint: Fix spellingKyösti Mälkki
Change-Id: I684e1962a9d4312ee9fad4ada70323b02ca3ae48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-07sb/intel/fsp_rangeley: Fix typo in GPIO LevelElyes HAOUAS
Change-Id: I83886820b8c1acceb2007b694361fe8c30c34f7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Guckian
2019-01-07sb/intel/bd82x6x: Fix typo in GPIO LevelArthur Heymans
Change-Id: I5e24120ca788ace8b61f8a7aee177c7247d30de2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-07src: Use "foo **bar" instead of "foo ** bar"Elyes HAOUAS
Change-Id: I8260424ee243c06827f2b5939e1568e52539b282 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-01-07src: Move constant to the right side of comparisonElyes HAOUAS
Change-Id: I76d35a3643600f81a6da7e0af99c935ebd1c2fc7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/27015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-06Kconfig: Unify power-after-failure optionsNico Huber
The newest and most useful incarnation was hiding in soc/intel/common/. We move it into the Mainboard menu and extend it with various flags to be selected to control the default and which options are visible. Also add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the boolean to int conversion into Kconfig: 0 - S5 1 - S0 2 - previous state This patch focuses on the Kconfig code. The C code could be unified as well, e.g. starting with a common enum and safe wrapper around the get_option() call. TEST=Did what-jenkins-does with and without this commit and compared binaries. Nothing changed for the default configurations. Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06usbdebug: Make the EHCI debug console work in the bootblockArthur Heymans
Currently this needlessly initializes the hardware in the both the romstage and the bootblock, but it works. Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the use better, related support files can be built to pre-ram stages regardless of usbdebug being enabled or not. Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK). Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-06usbdebug: Refactor init callsKyösti Mälkki
Expose the function that can unconditionally re-initialise EHCI debug host and gadget. Given the missing header in soc/intel files that prevented building with USBDEBUG_IN_ROMSTAGE=y, it is not actually known if those SOCs work at all for usbdebug. Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-06device: Use pcidev_path_behind()Kyösti Mälkki
Change-Id: Iac16f9412d0e6aac908d873c61a4de3935e5318a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26518 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06device: Use pcidev_path_on_root()Kyösti Mälkki
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06device: Use pcidev_on_root()Kyösti Mälkki
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-04AGESA: Use pcidev_on_root()Kyösti Mälkki
We have constant CONFIG_CBB==0, replace ill dev_find_slot() with safe pcidev_on_root(); Change-Id: Ieb2030fa3d77a9f49fc5faf12b92b5f00f49d354 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26482 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04binaryPI: Use pcidev_on_root()Kyösti Mälkki
We have constant CONFIG_CBB==0, replace ill dev_find_slot() with safe pcidev_on_root(); Change-Id: If536adf11aacef8faa3455692285552f97531df9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26483 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04amdfam10 boards: Drop AMD_SB_CIMXKyösti Mälkki
Copy-paste, boards do not set this. Change-Id: I4c0795a483948b1e357388a5ad639c3f1950bbc8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04device: Replace ugly cases of dev_find_slot()Kyösti Mälkki
These few cases lacked a proper devfn parameter in the form of PCI_DEVFN(dev, fn). Change-Id: Iad0b214df12dee65360d07e887a960b0c73a3e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/26481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-01-03sb/intel/*: Use common files for PCIe ACPIArthur Heymans
The result is that i82801{g,i,j}x now use the correct _PRT table for their root port number. Change-Id: I92bba3c669f3e6a44a42e19a88a33dfcfc2b9b42 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-03sb/intel/bd82x6x: Move pcie ACPI code to a common placeArthur Heymans
Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-03sb/intel/lynxpoint/pcie.c: Add more checks for NULL pointersTristan Corrick
If PCIe root port `n` is disabled, then `rpc.ports[n - 1]` remains NULL. The existing Lynx Point systems probably don't end up dereferencing NULL pointers this way. However, it might occur on a system using Flexible I/O to remap PCIe root ports to other functions. Tested on an ASRock H81M-HDS and an Acer C720 (Google Peppy). No issues presented themselves. Change-Id: I2c22fa36217766c2c4d6e8046f99989063066b16 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30079 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03sb/intel/lynxpoint: Remove incomplete SATA ACPI codeTristan Corrick
The existing SATA ACPI code for Lynx Point implements some methods and devices, but not completely. These methods are optional and only used in IDE mode. The code was likely copied from bd82x6x, where it has since been removed. As a result, many remarks produced by iasl about unreferenced objects are eliminated. Tested on an ASRock H81M-HDS and an Acer C720. No issues with SATA were observed. Change-Id: I808a9dff7b9ba34239ffd95fa4cb9b39b10c4b62 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30149 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-30soc/intel: Fix ugly preprocessor macroKyösti Mälkki
Macro hides that dev_find_slot() takes two arguments. Change-Id: I639af31b9d4a2d702dfd2baebddbb8352e8bf9b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-29sb/intel/bd828x6x: Make CONFIG_ELOG=y compileArthur Heymans
The function pch_log_state() was overlooked when making the smi relocation code common. Change-Id: I878772f1a93105b828e50f37e105d04988ba0bdf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-28sb/intel/lynxpoint: Handle H81 only having 6 PCIe root portsTristan Corrick
The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root ports, all others have 8 [1]. The existing PCIe code assumed that all non-LP chipsets had 8 root ports, which meant that port 6 would not be considered the last root port on H81, so `root_port_commit_config()` would not run. Ultimately, while PCIe still worked on H81, all the root ports would remain enabled, even if disabled in the devicetree. Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they are unused, and the MAX constant is incorrect. Interestingly, this fixes an issue where GRUB is unable to halt the system. Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree do indeed end up disabled. [1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904. Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30077 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-24sb/amd/cimx/sb800/ramtop: Fix coding style issuesPaul Menzel
Let GNU indent 2.2.11 fix the coding style issue with `indent -linux …`. Change-Id: Ia2d48906bbeb5ec2f3bea6a93fd2a06aa76b29d9 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/c/19458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-12-21cpu/amd/geode_lx: Drop supportArthur Heymans
These chips are still using LATE_CBMEM which was agreed upon to be removed after release 4.7. It is now more than 1 year later and they still linger around. The work and review to bring this code up to date can happen on the 4.9 branch and then squashed together and merged back into mainline when done. Change-Id: I11290a5e92397b9b7e7e5a19b029278e728671a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-19sb/intel/lynxpoint: Don't force state keep after power failTristan Corrick
The deleted line crept in with commit 562db3bb3fa1 ("libpayload: find source of input characters"). Tested on an ASRock H81M-HDS with `power_on_after_fail` set to `Disable` via CMOS. After this patch, the system no longer powers on as soon as power is restored after a power failure. Change-Id: Ie9d9dab9885b285db1c5094c2c8d62aae551f1e7 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-19southbridge: Remove useless include <device/pci_ids.h>Elyes HAOUAS
Change-Id: Ia640131479d4221ccd84613033f28de3932b8bff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-12-18southbridge: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Ic3f7d4d570cb5e343a9cf616e6e71935f9522b0a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18Fix typos involving "the the"Jonathan Neuschäfer
Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-07sb/amd/pi/hudson: Fix UART address mathMarshall Dawson
Correct a build error that occurs when HUDSON_UART is selected. Replace sizeof() of a nonexistent variable with the intended type. This was introduced in bd48b23 "southbridge//hudson: Get rid of void pointer math". BUG=b:118484178 TEST=Build Bettong with Chipset/"UART controller for Kern" Change-Id: Icc0ff9d80c3f5cab9ab837cf1cd0cd8eb0753284 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/30072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-07sb/intel/lynxpoint/pcie.c: Fix a mistake in a commentTristan Corrick
The code annotated by the comment is dealing with root port 7, so update the comment to reflect that. It looks like the comment was copied from the root port 3 case, but not updated. Change-Id: I0e27e4453f4c3b2b1b9dffb0c89b71373c6b303e Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-07src/southbridge: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ib4db9c263ff156966926f9576eed7e3cfb02e78a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-05sb/intel: Fix pointer castsPatrick Rudolph
Fix some compiler warnings due to pointer to integer conversions with different size. Required for 64bit ramstage. Change-Id: Ibfb3cacf25adfb4a242d38e4ea290fdc3929a684 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-05sb/intel/i82801{g,j}x: Remove unused smi.c filesArthur Heymans
Now that all targets featuring these southbridges use SMM_TSEG these files are unused. Change-Id: Ic3a1d790f3595e98a8d33e6e8274cb72ad356a89 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30018 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-05elog: make elog's SMM handler code follow everything elsePatrick Georgi
Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in cpu/x86/smm.h Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30022 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 03:54:12 +0000