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2008-08-01coding style fixes (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-12There was a programming error which made most USB port4 setup wrong. This ↵Marc Jones
patch uses byte pointer and the MMIO read and write functions. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-20Extend the VIA vt8237r southbridge decode range for the ROM to 1MB.Bari Ari
Signed-off-by: Bari Ari <bari@onelabs.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07Implement GPIO configuration routines for the Intel 3100 southbridge,Ed Swierk
allowing you to specify per-mainboard GPIO settings. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only ↵Marc Jones
doing a pci_write_config8. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-30By default, the Intel 3100 LPC interface enables only I/O range 0x3f8Ed Swierk
for both serial ports, making it challenging to use COM2 for the early console. Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23This patch fixes the 3 broken sata ports on the Tyan s2891 (primary port onWard Vandewege
secondary controller was ok). There were two problems: the master sata controller was not being initialized, and the irqs for the secondary ports on both controllers were not being set in the mptable. Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem. While all ports work reliably under a recent kernel (2.6.24), sata is about half as fast as under the proprietary bios, according to bonnie++. That still needs fixing... Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-06This patch halts the tco timer early in the boot process on all ICH series ↵Joseph Smith
southbridges. It also keeps the boot processes from rebooting through out the coreboot process. Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01Setting an integrated southbridge device (like SATA or USB2.0) toEd Swierk
"off" in Config.lb should cause the PCI device not to respond to configuration requests. Replace the existing code that I naively copied from esb6300 with something that actually works on the 3100. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01Remove i82801DB files that I meant to delete in r3206.Joseph Smith
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01Tiny style fix for consistency (trivial).Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01Removal of i82801DB (ICH4)Joseph Smith
There are no boards that use the i82801DB (ICH4). The code does NOT work. Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01The early init code of several Intel southbridge chipsets callsEd Swierk
pci_locate_device() to locate the SMBus controller and LPC bridge devices on the PCI bus. Since these devices are always located at a fixed PCI bus:device:function, the code can be simplified by hardcoding the devices. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-30Like other Intel chipsets, the Intel 3100 has a TCO timer that rebootsEd Swierk
the system automatically unless software resets the timer periodically. The extra reboot extends boot time by several seconds. The attached patch adds a function to the Intel 3100 southbridge code that halts the TCO timer, thus preventing this extra reboot, and calls the function early in the boot process on the Mt. Arvon board. It also fixes a bug in the LPC device initialization -- the ACPI BAR enable flag is bit 7, not bit 4. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29Now coreboot performs IRQ routing for some boards.Nikolay Petukhov
You can see this by executing commands like this: grep -r pci_assign_irqs coreboot/src/* This basically AMD/LX based boards: pcengines/alix1c, digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800. Also for AMD/GX1 based boards need a patch [http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch] for the right IRQ setup. AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320, bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p. I have two ideas. 1. Delete duplicate code from AMD/LX based boards. 2. Add IRQ routing for AMD/GX1 boards in coreboot. The pirq.patch for IRQ routing logically consist from of two parts: First part of pirq.patch independent from type chipsets and assign IRQ for ever PCI device. It part based on AMD/LX write_pirq_routing_table() function. Second part of pirq.patch depends of type chipset and set PIRQx lines in interrupt router. This part supports only CS5530/5536 interrupt routers. IRQ routing functionality is included through PIRQ_ROUTE in Config.lb. Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on TeleVideo TC7020, see http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20Following patch adds K8M890 support. It initializes the AGP and graphics UMA.Rudolf Marek
The V-link setup and HT bridge is redone, because VT8237A has it in another device. So far following combination of chipsets should now work: K8T890CE + VT8237R K8M890(CE) + VT8237R VIA PC1 brige moved to NB code (vt8237r_bridge.c -> k8t890_bridge.c) and notes about K8M890 support were added. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-19Following patch will setup KT890 HT automatically. It will find theRudolf Marek
max width of the link and also it will take the frequency of K8 HT already done coreboot (and checks if t can run on it). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16Here is an updated patch addressing most of Uwe's and Peter's ↵Ed Swierk
comments. Ripping out the ehci/uhci_init() code doesn't seem to have done any harm, and I got rid of a bunch of unused junk in i3100_smbus.h I left the *_set_subsystem() arguments unsigned, as that's how the function is declared in include/device/pci.h. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15Following patch extends the ROM decoding to last 1MB, allowing to use largerRudolf Marek
flashes such as SST49LF080A: 1024K x8 (8 Mbit) Tested on my system, the flash is found and if I use coreboot in second half it works too. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15Following patch fixes the retrain/reset sequence which caused problem with someRudolf Marek
nVidia cards. The enable link should be enough, retrain is done there. Tested on my system. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-25This trivial patch removes an unused local variable, thus getting rid ofRonald Hoogenboom
a compiler warning. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-20Route device IRQ through PCI bridge instead in mptable.Yinghai Lu
Don't enable pin0 for ioapic of io-4. 1. apic error in kernel for MB with mcp55+io55 2. some pcie-cards could have pci bridge there, so need to put entries for device under them in mptable. Signed-off-by: Yinghai Lu <yinghailu@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19Additional early AMD8111 southbridge support for Barcelona platforms.Marc Jones
Check that the SMBus controller is found and stop on an error. Clean up and add additional path through the 8111 reset functions. Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-30Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s):Uwe Hermann
- Implement ISA related support: - Initialize the RTC - Enable access to all BIOS regions (but _not_ write access to ROM) - Enable ISA (not EIO) support - Without the *_isa.c file, the Super I/O init is never performed - Improve IDE support: - Add config option to enable Ultra DMA/33 for each disk - Add config option to enable legacy IDE port access - Implement hard reset support - Implement USB controller support - Various code cleanups and improvements The code partially supports southbridges other than the 82371EB (but which are very similar), more complete support will follow. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29Restructure/rename/comment a few 82371XX-related PCI IDs (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-201. Fix pirq routing table setting for GA-2761GXDK.Morgan Tsai
2. Southbridge PCIe slots are working correctly now. 3. Disable keyboard & mouse ports for GA-2761GXDK. Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-15Various cosmetic fixes and improvements (trivial).Uwe Hermann
- Use 'static' where appropriate. - Use 'const' where appropriate. - Indentation fixes. - Add comment wrt init code which is only valid for VT8237R. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14* Maintaining SiS south bridge device IDs.Morgan Tsai
* Strip unnecessary driver modules. Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13Add support for FID/VID changes messages.Rudolf Marek
Upon incoming SMAF message from CPU (C3 or FID/VID change), the SB will assert SLP# which is connected to LDTSTOP_L on K8 CPUs. Question is for how long. Imho for 100us. Which is more than plenty (2us required) I will try to justify this once I know what bios to set in SB. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13Fine-tune the V-link bus between K8T890 and VT8237R and setRudolf Marek
it to 8X transfer rate (up to 1066 MB/s) similar code placed here would be needed for VT8237A/S etc. Using VIA recommended values despite they are for K8T890CF, this is K8T890CE (still dont know what is exactly different). This patch enables the parity error reporting on V-Link, so it enables NMI generation for the SERR# errors. The NMI may not be generated, maybe port 61h needs some tuning too. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07Add initial support for all known ICH* southbridges to theUwe Hermann
i82801xx code for the following parts: - AC97 audio/modem - Onboard network interface cards (NICs) - USB 1.1 controllers - SMBus controllers Some other parts are still missing and will be added later. Use PCI ID #defines from pci_ids.h everywhere. Constify various structs. Also, fix some random cosmetic issues in the code. All of this is relatively trivial and tested by manually building all boards which currently use the i82801xx code. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2951 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07This patch masks the function prototypes in stdlib.h from ROMCC, so thatCorey Osgood
ARRAY_SIZE() can be used on ROMCC-dependent systems. Also adds stdlib.h to vt8237r_early_smbus.c, so it'll build on those systems. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-07Add PCI IDs for most Intel southbridges of the 82801 seriesUwe Hermann
(ICH/ICH0 up to the ICH9 family) in preparation for further code improvements for the i82801xx southbridge code. Small fixes in the 6300ESB PCI IDs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-05* Change one PCI vendor ID from Nvidia to SiSCarl-Daniel Hailfinger
* Remove dead code * Remove unused variables * Fix bug where array was one element too small * Fix error value truncation, the old code never entered the error path * Remove warnings Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04Various cosmetics, coding style fixes, constifications (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-04Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up toUwe Hermann
ICH5/ICH5R (more to follow) in preparation of further 82801xx improvements. Use human-readable names for the PCI ID #defines. Rename *_ISA to *_LPC as per datasheet. The 82801DBM only has 3 (not 4) USB devices, looks like a copy-paste error. The fixes in southbridge code are only to keep the build working for now, any real improvements will only go into the 82801xx code in future. This is abuild-tested so it shouldn't break anything. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-03This patch is some small changes to the vt8237r to prepare it forCorey Osgood
the Jetway J7F2 patch that should be coming soon, and also moves most defines into vt8237r.h. I've changed some of the values from u32 to u8, because that's all they should ever need to be. Also includes doxygenized comments! Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02remaining part of the patch.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02Delete a file no longer used by the SiS implementationJordan Crouse
No functional code changes. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-021. vgabios removed, will go to extra repositoryMorgan Tsai
2. Rename sisnb.c to sis761.c 3. Delete many mis-definition for sis device in src/include/device/pci_ids.h 4. Trim trailing spaces for all files Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-02trivial fix for the .data problemStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30Various fixes and improvements of the 82801xx code.Joseph Smith
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30Add support for the VIA VT8237R southbridge.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: <corey.osgood@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30fix the readwrite/readonly clashes for the pci_driver structs in the sisStefan Reinauer
code. This is trivial, I did it for the other components before. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-29Thanks to the great efforts of Morgan Tsai of SiS we support the SiS966Morgan Tsai
southbridge now: From: Morgan Tsai <my_tsai@sis.com> It supports SiS761GX / SiS966 chipset, only for AMD K8 platform so far. Due to integrated VGA sharing system memory, some code in southbridge folder have to init northbridge. Copyright (C) 2007 Morgan Tsai <my_tsai@sis.com> Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) Change Log: Newly support GIGABYTE GA-2761GXDK CPU type: AMD AM2 socket Northbridge: SiS 761GX Southbridge: SiS 966 SuperIO: ITE8716F Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24smaller changes to silence build warnings. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24Ever wondered where those "setting incorrect section attributes forStefan Reinauer
rodata.pci_driver" warnings are coming from? We were packing those structures into a read-only segment, but forgot to mark them const. Despite its size, this is a fairly trivial patch created by a simple search/replace Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22This patch adds support for K8T890CE northbridge.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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