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2014-08-18southbridge/intel/fsp_rangeley: fix to include irqroute.h twiceMartin Roth
This matches what was done on baytrail in commit bfca984b - soc/intel/fsp_baytrail: set up for including irqroute.h twice irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Change-Id: I709f9370ce7db1b3ffac2297aeaba5cc670ec20c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-13southbridge/amd/cimx/sb800: Uninitialized variables in config funcEdward O'Callaghan
Both 'SbSpiSpeedSupport' and 'UsbRxMode' are uninitiated upon return from a 'sb800_cimx_config()' call. Change-Id: I32237ff97fafc3e69627d427e54268dcb039e12c Found-by: Coverity Scan Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12gm45: Move S3 detection to enable stage.Vladimir Serbinenko
Also move it to NB to be in line with other. Change-Id: Ibd961d60dcd686899f34f6a494c14ff9d65e618b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12i82801ix: Make RP04 optionally hotpluggable.Vladimir Serbinenko
Change-Id: I34a1ae4bff22db6ee55fa511de39bdfd5dd92c7e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-11i82801ix: Declare gen decode registers.Vladimir Serbinenko
Change-Id: I999818833c9040eb4f4e19c313b5e9be216ffd86 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-10lynxpoint: Add interrupt for GPIO controller in ACPI deviceDuncan Laurie
The GPIO controller uses IRQ14 as an active high level triggered source for GPIOs that are configured to trigger shared interrupt. This was also tested on bolt by configuring the touchscreen to use a shared GPIO interrupt: localhost ~ $ grep atmel_mxt_ts /proc/interrupts 54: 24 188 93 124 LP-GPIO-demux atmel_mxt_ts Change-Id: I3765120112bae11407e5b2020399d0d0b8e3cef8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171901 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 63a0c80ce5a19410d0608fede5a9fe0ec1c8e5c1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6541 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-10southbridge/ricoh,ti: Remove trailing whitespace in debug outputPaul Menzel
Change-Id: If58854c35dce83bf6db7a84a8cb441cc3e60d6d4 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6529 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-10intel/fsp_bd82x6x: Fix cycle error some morePatrick Georgi
As a follow up to #6479 (63e1948643fcbd763c83b6baa6cd9a077d49f1fc), fix the remaining faulty loop. Change-Id: I2c77efe620c71e939f4d74e48f90a166c782e5f5 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6569 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-09southbridge/amd/cs5536: Trivial style fix for trailing commentEdward O'Callaghan
Change-Id: Ia3a846497c220866e950a4b0bb53cb05c0e0cee2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6557 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-03intel/fsp_bd82x6x: Fix cycle errorPatrick Georgi
Some copy-pasta snuck in that reintroduced an error already fixed in #3435 (62f8083dfdf0c5e0046efe297b2bf88474928071) Change-Id: I47db23e88fa09c73b4cf3e99fe2d0ed2ac30fd80 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6479 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-01i82801ix: Provide ramstage smbus functions.Vladimir Serbinenko
Change-Id: Idc62e382a4002274abe6c23d76fe0874c62846c5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6433 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30southbridge/intel: Add fsp_rangeley supportMartin Roth
This adds the southbridge initialization pieces for Intel's Atom C2000 processor (formerly Rangeley). It is intended to be used with the Intel Atom C2000 FSP and does not contain all of the pieces that would otherwise be required for initialization. Change-Id: I416e85bd6e9c9dcf79f97785074135902fdd18b7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/6370 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30i82801ix: Allow configuration of SATA mode in CMOS.Vladimir Serbinenko
Change-Id: Ice0f0273b16a946143c038a90b61978269c1c56e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6409 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-30model_fxx/processor_name.c, hudson/lpc.c: add missing break statementsDaniele Forsi
Found by Cppcheck 1.65. Fixes: (warning) Variable 'processor_name_string' is reassigned a value before the old one has been used. 'break;' missing? (warning) Variable 'rsize' is reassigned a value before the old one has been used. 'break;' missing? Change-Id: I4a5c947fd5cc5797eb026475ec7036bc5eaf58db Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6372 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30i82801ix: Enable usbdebug options.Vladimir Serbinenko
Needed to be able to choose convenient usbdebug port. Change-Id: I84b304f0f8fa79cc8d4a136ee6d78dc7659601c9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6410 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-29Uniformly spell frequency unit symbol as HzElyes HAOUAS
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6384 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-29sandy/ivybridge: Native raminit (lint clean)Edward O'Callaghan
Remove some trailing whitespaces and add header guards for code introduced in: 7686a56 sandy/ivybridge: Native raminit Change-Id: Ifc9a785ea3a43cfe1f406b57eeba9b5f94f36711 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6393 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2014-07-29sandy/ivybridge: Native raminit.Vladimir Serbinenko
Based on damo22's work and my X230 tracing. Works for my X230 in a variety of RAM configs. Also-By: Damien Zammit <damien@zamaudio.com> Change-Id: I1aa024c55a8416fc53b25e7123037df0e55a2769 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/5786 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28dmp/vortex86ex/southbridge.c: Do not access arrays out of boundDaniele Forsi
Found by Cppcheck 1.65. Fixes: [src/southbridge/dmp/vortex86ex/southbridge.c:498]: (error) Array 'rtc[7]' accessed at index 7, which is out of bounds. [src/southbridge/dmp/vortex86ex/southbridge.c:498]: (error) Array 'bin_rtc[7]' accessed at index 7, which is out of bounds. Change-Id: I8939fe1b326202bbe2784639b0e591f8ee470eeb Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6375 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Andrew Wu <arw@dmp.com.tw>
2014-07-25AGESA f15tn f16kb: Fix HUDSON_XHCI_ENABLEKyösti Mälkki
Control for XHCI was split to handle AMD_INIT_RESET in agesawrapper while AMD_INIT_ENV was already handled as part of BiosCallouts. OEM configuration is supposed to be implemented as part of BiosCallouts, leaving agesawrapper agnostic of platform details. TODO: S3 resume for XHCI1. Change-Id: Id5e9c25a227db4d821f1be4b176470547ca4ea84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6241 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-07-24southbridge/via: Remove trailing whitespaceElyes HAOUAS
Change-Id: I28deda21a7070ea6f14f973b66fd5dd119bc6225 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6345 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24southbridge/amd: Remove trailing whitespaceElyes HAOUAS
Change-Id: I25cdfe6b3c8067793620677c62251e78704f7851 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6334 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-23src/.../Kconfig: various small fixes to textsDaniele Forsi
Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-17intel/lynxpoint/Kconfig: Remove duplicate option `IFD_BIN_PATH`Paul Menzel
Currently `IFD_BIN_PATH` is shown twice. Commit 5218e616 (intel/lynxpoint: Allow building without IFD (descripter.bin)) [1] accidentally added the option another time. So fix up the commit and remove one of the two options `IFD_BIN_PATH`. Keep the one which depends on `!HAVE_IFD_BIN` and is around the IFD options. [1] http://review.coreboot.org/6046 Change-Id: Id46f01ab8ee2e752e337e687a2ef0dfa374f44a5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6269 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-07-17southbridge,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ied03e8814ea13f0e677a1d34da19efe6dfebf72f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6288 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17southbridge,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I8ef5f1571ad14ead2d4cc0d61b6b7133d7fc8550 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6293 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-15southbridge/intel/bd82x6x/me_8.x.c: Trivial - space to tab fixEdward O'Callaghan
Change-Id: I5b6d0a1f5f96a8d6cfc5a14baaa0f9267339b072 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-15AGESA hudson: Fix SPI writesKyösti Mälkki
Only yangtze has longer FIFO in SPI controller. This was overlooked in commit 9f0a2be AMD SPI: Optimise for longer writes which broke SPI writes and caused CBFS errors with fam15tn. Change-Id: I821e3f1fa186d2383b30eab9c5d52797c2ef22c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6273 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-14AGESA fam15: Fix entry to cimx/sb900Kyösti Mälkki
Move SB900 call to match comments and changes already made for family14 et al. Change-Id: I22aa0bbeeabf9cff929c49c23014005bc3d53ccb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6238 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA CIMx: Move late init out of get_bus_conf()Kyösti Mälkki
Followup deals further with Fam15 case. For unknown reasons calls were commented out for amd/dinar and they remain that way. Change-Id: Ie0a25fbb6f5378019fbf0f19a02acf024d79817e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6237 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AMD SPI: Optimise for longer writesKyösti Mälkki
Leave it to the implementation of flash->write() to split the writes to match SPI controller and SPI flash part restrictions. This allows for some optimisation for auto-address-increment (AAI) commands. Kconfig AMD_SB_SPI_TX_LEN can be kept as local. Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6164 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14SPI: Split writes using spi_crop_chunk()Kyösti Mälkki
SPI controllers in Intel and AMD bridges have a slightly different restriction on how long transactions they can handle. Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6163 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-12libpayload: find source of input charactersLuigi Semenzato
This change makes it possible for vboot to avoid an exploit that could cause involuntary switch to dev mode. It gives depthcharge/vboot some information on the type of input device that generated a key. BUG=chrome-os-partner:21729 TEST=manually tested for panther BRANCH=none CQ-DEPEND=CL:182420,CL:182241,CL:182946 Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/182357 Reviewed-by: Luigi Semenzato <semenzato@chromium.org> Tested-by: Luigi Semenzato <semenzato@chromium.org> Commit-Queue: Luigi Semenzato <semenzato@chromium.org> Reviewed-on: http://review.coreboot.org/6003 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11intel/lynxpoint: Allow to always route USB3 ports to XHCIStefan Reinauer
This will make USB keyboards connected to USB3 ports work in libpayload on Beltino. BUG=chrome-os-partner:23396 BRANCH=none TEST=Use USB keyboard on Beltino in dev mode screen Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/173640 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6018 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11intel/lynxpoint: Work around XHCI resume issuesDuncan Laurie
When USB3 devices are attached while in suspend, or two USB3 devices that are both plugged in are switched to the other port while in suspend the kernel does not seem to notice this -- despite the cold attach status bit. This results in the devices showing up in the USB list at the old enumerated device numbers and higher layers continuing to think they are present but not reseponding. With the kernel workaround to deal with devices that are logically disconnected it is possible for firmware to send a warm port reset to devices that are in this state and then the kernel will see them disappear and handle it properly. This same issue exists in the EFI firmware on the Whitetip Mountain 2 reference board so it is not specifically a coreboot bug. If this behavior is fixed in the kernel then this workaround could be removed since it is in RW firmware. BUG=chrome-os-partner:22818 BRANCH=falco,peppy,wolf,leon TEST=manual: 1) attach two USB3 devices 2) suspend system 3) switch the ports that the USB3 devices are attatched to 4) resume system 5) confirm that the devices are re-enumerated and come up properly Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4) Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170579 [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6017 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11intel/lynxpoint: xhci: Revert suspend/resume changesDuncan Laurie
I have been attempting to work around USB3 issues that appear in the kernel with hacks in the firmware, but this is resulting in more headaches in the kernel. Instead remove all the work that was being done at resume time and undo the change that was issuing a warm reset to all ports at suspend time. The bad device behavior will be dealt with at the kernel level to handle devices that get stuck in polling state after enable/disable sequence. BUG=chrome-os-partner:22754 BRANCH=falco,peppy,wolf,leon TEST=manual: suspend/resume with several misbehaving devices: Kingston USB3 Media Reader Transcend USB3 Media Reader Various ADATA USB3 drives Various Kingston USB3 sticks Original-Change-Id: I0894454af42d2ced456fe0da921d74c9e74902d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170107 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c2abb4d0dad6ed00e1e230d604c4c0a76eb4eef7) Change-Id: Ib215d9c230f90a1c9f34bf29254bb9feec28c67e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170578 [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6016 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-11southbridge/amd/rsXY0/cmn.c: Trivial - Style fixesEdward O'Callaghan
Remove some ASCII art past 80 columns. Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-10AGESA Hudson: Fix build without HAVE_ACPI_RESUMEKyösti Mälkki
If one commented out HAVE_ACPI_RESUME in Kconfig file for a board using agesa/hudson the build failed. Change-Id: Ifbad8f6e23ce4b5431e596bf67e6ab108fedb4ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6253 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
2014-07-08southbridge: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I5484ebb665453777cc3b2561be6e50c787f1a257 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6209 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-05spi: Change spi_xfer to work in units of bytes instead of bits.Gabe Black
Whenever spi_xfer is called and whenver it's implemented, the natural unit for the amount of data being transfered is bytes. The API expected things to be expressed in bits, however, which led to a lot of multiplying and dividing by eight, and checkes to make sure things were multiples of eight. All of that can now be removed. BUG=None TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI errors in the firmware log. Built for rambi. BRANCH=None Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192049 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6175 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black
The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6174 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05intel/lynxpoint: Build intermediate step to add Lynx Point ME imageDuncan Laurie
This is needed to successfully build fox_wtm2 from external repo. BUG=chrome-os-partner:18638 BRANCH=none TEST=manual: successfully compile coreboot for fox_wtm2 and create an image with chromeos-bootimage/cros_bundle_firmware Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4132 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05intel/lynxpoint: xhci: Port reset changes on suspend/resumeDuncan Laurie
Some USB3 devices are not showing up after suspend/resume cycles. In particular if a device uses a lower power state like U2 it may take longer to come up and the firmware needs to wait after sending a warm port reset. In addition skipping port reset to connected ports in the way into suspend was causing problems so instead send all ports a reset before suspend. BUG=chrome-os-partner:22402 BRANCH=falco,peppy,leon,wolf TEST=manual: Suspend/resume with ADATA HE720 HDD (and other devices) both connected at suspend and connecting while in suspend and ensure that the devices always show up in the kernel. Change-Id: Ib7b15dc65792742b4ceb7dcfc4b2c83192eafcc2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169548 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6015 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05intel/lynxpoint: Export pch_enable_lpc() for Super I/O systemsStefan Reinauer
In order to enable a Super I/O in non Chrome EC systems we need to make pch_enable_lpc() available to the mainboard romstage.c BUG=none BRANCH=none TEST=boot ChromeOS on Beltino Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172180 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6019 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-04intel/lynxpoint: Add SATA DEVSLP disable optionMarc Jones
Add the chip option to disable SATA DEVSLP. This disables the SDS bit in the SATA CAP2 register. BUG=chrome-os-partner:23186 BRANCH=leon TEST=Manual: System runs without SATA failure for more than 10 hours Original-Change-Id: I8baa40935421769aeee341a78441fb19ecaa3206 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: https://chromium-review.googlesource.com/174648 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 49d25812b04a983d687a53a39530559ba99fd9b4) Change-Id: Iac0b32f80958f5ffb571733484dc931bee216f55 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: https://chromium-review.googlesource.com/176352 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/6013 Tested-by: build bot (Jenkins)
2014-07-04intel/lynxpoint: Add CONFIG_LOCK_MANAGEMENT_ENGINE entry to KconfigDuncan Laurie
This was missing from lynxpoint. BUG=chrome-os-partner:21796 BRANCH=falco,peppy TEST=emerge-falco chromeos-coreboot-falco Change-Id: Id1b261a5310ce1482f11c8c032c13f49046742fc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66669 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6012 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-04intel/lynxpoint: Use separate SMI callback for USB XHCI routingDuncan Laurie
This will allow the legacy mode boot path to leave USB ports routed to EHCI so they can be used by SeaBIOS. BUG=chrome-os-partner:22085 BRANCH=falco,peppy TEST=manual: Build and boot from USB and SeaBIOS on falco Change-Id: I46870eccd1b846dc8a7f8d7948969c8e623e18cd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6011 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-04intel/lynxpoint: Make inclusion of Intel ME optionalPaul Menzel
Current build configuration always wants to include an Intel Management Engine (ME) firmware (`me.bin`) on Intel Lynx Point systems. However, we can have a working coreboot without it, as long as the factory delivered ME firmware is kept untouched in the flash ROM. So let the user decide if a ME firmware will be included in the build by introducing the Kconfig option `HAVE_ME_BIN`. The same was done in commit 99fd30e4 (sandybridge: Make inclusion of me.bin optional) [1] for Intel Sandy Bridge (BD82x6x). [1] http://review.coreboot.org/3522 Change-Id: I7c6048fd0f56288769ad90acbfb67b908ac8d824 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6047 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-04intel/lynxpoint: Allow building without IFD (descripter.bin)Paul Menzel
On newer Intel systems, like Intel Lynx Point, the flash ROM is shared between the host processor (BIOS), its Management Engine (ME) and an integrated Ethernet controller (GbE). The layout of the flash ROM (and other information) is kept in the so called Intel Firmware Descriptor (IFD). If we only want to build coreboot to update the BIOS section, all we need is the flash layout. So add the option to specify the flash layout in the mainboard’s Kconfig, and thus, to build without the real IFD. However, with such a build, one has to make sure that the IFD section on the flash ROM will not be written over (nor any other section that has not been included by coreboot). A patch to write selected sections of a flash ROM with IFD has been sent to the flashrom mailing list [2]. The same was done in commit a15cd66b [1] (sandybridge: Make build possible without descriptor.bin) for Intel Sandy Bridge (BD82x6x). [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html [PATCH] Add option to read ROM layout from IFD [2] http://review.coreboot.org/3524 Change-Id: I26a604446cdf37a6bbcee2b14a107b7ccf417d5c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6046 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-03AGESA: Clean separation of SPI flashKyösti Mälkki
To be precise, wakeup from S3 does not involve SPI writing, while preparing for it on cold power-ons currently does. For S3DataTypeMtrr storage is changed such that the first 4 bytes is the length of data stored like with the other two S3DataType. Change-Id: Id920650474530d4191075da4ef70daa66c904c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6085 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 02:09:08 +0000