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2009-05-26ops can not be const because of the pci conf1/conf2 hackery we do. trivialStefan Reinauer
patch, just removes the warnings like coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ac97.c:73: warning: initialization discards qualifiers from pointer target type Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-13Oops forgot small part. Set up PIRQs in mainboard Config.lb for IP1000 and ↵Joseph Smith
RM4100 instead of using the ones in i82801xx_lpc.c. Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-11This patch adds high table support to qemu. It was already added toMyles Watson
src/northbridge/intel/i440bx/ but not to src/cpu/emulation/qemu-x86/northbridge.c It also adds a driver for the ISA device that is found when using 0.9.1 If you look in a log without this patch you won't find the RTC init lines. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02Assign PIRQs in mainboard Config.lb or use the default ones listed in ↵Joseph Smith
i82801xx_lpc.c. Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02Run dos2unix on all files:Stefan Reinauer
find . -type f| grep -v svn | xargs dos2unix Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02Trivial, update email address. Joseph Smith
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-01This is a patch to use another IRQ besides IRQ12 to fix conflicts with i8042 ↵Joseph Smith
- PS/2 Mouse. Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30Remove warnings from compilation of the s2892 with and without CBFS.Myles Watson
I didn't try to remove "defined but not used" warnings because there are too many ifdefs to be sure I wouldn't break something. For shadowed variable declarations I renamed the inner-most variable. The one in src/pc80/keyboard.c might need help. I didn't change the functionality but it looks like a bug. I boot tested it on s2892 and abuild tested it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-28fix warning: no return statement in function returning non-voidStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22This patch adds support for the BCM21000 (aka HT-2100)Mondrian nuessle
PCIe bridge. Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de> Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13Fix the build. This error was introduced by change in acpi.c, the ↵Rudolf Marek
acpi_slp_type exists only conditionally. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13Following patch adds support for resume on VT8237 based motherboards. The NBRudolf Marek
part of this patch adds support for resume well NVRAM. In which DQS values are stored. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06(trivial) fix some warningsStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-05two more totalimpact briq fixes. Gets us back to the romfs breakage on PPCStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04fix this warning for the embedded planet ep405pcStefan Reinauer
/tmp/ccilLWBf.s: Assembler messages: /tmp/ccilLWBf.s:144: Warning: setting incorrect section attributes for .rodata.pci_driver Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-21To make use of HAVE_HIGH_TABLES following patch is needed. Also, it movesRudolf Marek
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13This, ladies and gentlement, is commit #4000.Stefan Reinauer
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few include files and missing prototypes. Also, fix up the Config-abuild.lb files to properly work for cross compiling. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13ACPI implementation for i945, ICH7, Kontron 986LCD-MStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11This patch contains some significant updates to the i82801gx component and willStefan Reinauer
be required for a series of later patches. Roughly it contains: * fixed SMBus driver (was not compiled in before) * fixed S-ATA/P-ATA combination * Added warnings to drivers being called with a NULL dev->chip_info * Set subsystem ids for those boards that have none specified in Options.lb * Fix license headers. The code was originally released under GPL v2 but some files sneaked in with a v2 or later header. * some attempts to fix azalia/Intel HDA.. not working yet * clean up and fix pci bridge handling code * Add Config based GPI handling to LPC driver * Add HPET enable function * Enable clock gating where appropriate * first attempt at USB debug console support (not working yet) * Add required options to kontron board * many other minor changes Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10This patch adds common elements for ck804-based boards.Myles Watson
changes by file: src/northbridge/amd/amdk8/northbridge.c: Add high tables code ala Stefan's code for the i945. src/southbridge/nvidia/ck804/ck804_lpc.c: Enable High Precision Event Timers. Add pm_base for ACPI. src/southbridge/nvidia/ck804/ck804_fadt.c: Since fadt is only dependent on the Southbridge, add it here. src/southbridge/nvidia/ck804/Config.lb: Compile in ck804_fadt.c Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06* fix a minor power state issue in the ich7 smm handlerStefan Reinauer
* move mainboard dependent code into a mainboard SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06use include file for i8259 where appropriate (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-04I just went on a bugfix frenzy and fixed all printk format warningsCarl-Daniel Hailfinger
triggered by the AMD 690/SB600 targets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3Stefan Reinauer
a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-15- Fix up amd pistachio and dbm690t.Stefan Reinauer
- make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs on some platforms. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12This patch converts __FUNCTION__ to __func__, since __func__ is standard.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-09Remove some warnings, mainly from format strings which didn't match theMyles Watson
arguments. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-05Use the correct device for switching on HDA.Dan Lykowski
Reorder HDA (HD Audio) init: The reordering was based on what order things happen in the BIOS Developers guide, RPR, and SATA driver. I fixed the order of the devices that didn't matter to clean up the change log. 1. Enable the Chip 2. Setup the SMBus registers 3. Setup the Device Registers 4. Look for Codec 5. Init Codec The codec init was changed to match the description in the RRG pg 235. Mem Reg: Base + 08h Bit 0. There were unneeded things happening. Added 1ms delay to match the BKDG while waiting for BAR+0xe to set its bits. Signed-off-by: Dan Lykowski <lykowdk@gmail.com> Tested on AMD DBM690T and AMD Pistachio by Maggie Li. Works. Tested on Asus M2A-VM by Carl-Daniel Hailfinger. Improves the situation, but some warnings remain. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-23Fix rs690 bug about GPPSB configuration.Maggie Li
Signed-off-by: Maggie Li <maggie.li@amd.com> Reviewed-by: Zheng Bao <Zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20forgot to svn addStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20Update Kontron boardStefan Reinauer
- use new features of the ich7 update - move rambase above 1M to avoid memory trashing through SMM relocation - enable superio HWM Update ICH7 driver - minor smi cosmetics (in progress) - add real ac97 driver - add real azalia driver - fix some interrupt issues - fix some sata issues - include Patrick's fix for _lpc.c Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-19First shot at factoring SMM code into generic parts and southbridge specificStefan Reinauer
parts. This should help to reduce the code duplication for Rudolf's K8/VIA SMM implementation... Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15Adds a retry/faildown to SB600 SATA detection logic.Dan Lykowski
SATA port status kept returning 0x1: BAR5+po+28h 1h = Device presence detected but Phy communication not established This patch adds logic to force 1.5g if the drive fails to communicate at 3.0g. Signed-off-by: Dan Lykowski <lykowdk@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-29The SB600 RPR documentation does not mention what to do if SATA_BAR0+6Carl-Daniel Hailfinger
is no longer 0xA0 or 0xB0. It simply assumes that will never happen. My 500 GB Seagate Barracuda ST3500820AS triggers that corner case on the first init after poweron. The current code hangs forever with my drive. Fix this by rerunning the init sequence after SATA_BAR0+6 is no longer 0xA0 or 0xB0. Add support for SATA port 2-4 (Primary Slave, Secondary Master, Secondary Slave). If only the 2nd SATA port is connected and the hardware acts strangely (contrary to documentation), it will print the error message below and continue anyway. The official AMD asm code behaves the same way. SATA port 0 status = 0 No Primary Master SATA drive on Slot0 SATA port 1 status = 23 0x6=7f, 0x7=7f drive no longer selected after 0 ms, retrying init [8 repetitions] 0x6=7f, 0x7=7f drive no longer selected after 0 ms, retrying init Primary Slave device is not ready after 10 tries Activate and improve debug messages for SPEW log level. Fix some comments. New log messages look like this: PCI: 00:12.0 init sata_bar0=3020 sata_bar1=3060 sata_bar2=3030 sata_bar3=3070 sata_bar4=3000 sata_bar5=fc309000 SATA port 0 status = 23 0x6=a0, 0x7=80 drive detection not yet completed, waiting... 0x6=a0, 0x7=80 drive detection not yet completed, waiting... [... 281 repetitions ...] 0x6=0, 0x7=50 drive no longer selected after 2820 ms, retrying init drive detection done after 0 ms Primary Master device is ready after 2 tries SATA port 1 status = 23 drive detection done after 0 ms Primary Slave device is ready after 1 tries SATA port 2 status = 0 No Secondary Master SATA drive on Slot2 SATA port 3 status = 0 No Secondary Slave SATA drive on Slot3 With this patch, my Asus M2A-VM boots into Linux without problems. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23Handle RS690 quirks for 1 GHz noncoherent HyperTransport.Carl-Daniel Hailfinger
The RS690 chipset has a problem where it will not work with 1 GHz HT speed unless NB_CFG_Q_F1000_800 bit 0 is set. Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Bao, Zheng says: As a matter of fact, both 600Mhz and 1Ghz have their own specific setting. This patch has been tested on dbm690t which HT link works on 800Mhz. Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23Fix implicit declarations of pci_read_config32 and pci_write_config32 inMaggie Li
the SB600 code. Signed-off-by: Maggie Li <Maggie.li@amd.com> Reviewed-by: Zheng bao <Zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22Fix implicit udelay src/southbridge/nvidia/mcp55/mcp55_aza.cCarl-Daniel Hailfinger
Fix imlicit mdelay in src/southbridge/nvidia/mcp55/mcp55_nic.c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19Fix a LOT of implicit function declarations before they become errors.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18Fix implicit declaration in cn700/vt8237 codeCorey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18This patch gets rid of all the implicit definition warnings for serengeti ↵Myles Watson
except get_nodes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-17Add 690G and 690(MT) internal graphics support.Zheng Bao
The device ID of 690G is 0x791E, while the ID of 690M and 690T is 0x791F This fixes booting on 690G. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-13Move mainboard specific changes to the coreboot memory table into theStefan Reinauer
mainboard specific code. (And add a hook to allow other mainboards do a similar thing if required) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-12Improve comments in early SB600 setup, handle non-LPC strapping andCarl-Daniel Hailfinger
document verification against the data sheets. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Maggie Li <maggie.li@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04The patch changes the LDTSTOP length as well mostly default content of 0xec,Rudolf Marek
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong. Furthermore this fix for powernow may not work on CPUs hit by errata #181. Workaround should be implemented. The powernow may not work on pre-A2 revisions of VT8237S silicon, revision reg is unknown. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01Add AMD rs690 VID DID reporting and some minor cleanups.Joe Bao
Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01Add AMD sb600 HPET setup and some minor cleanups.Joe Bao
Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-14drop dead code in sb600 hdaStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06Drop #defines for registers that are not existant on the ICH7.Uwe Hermann
Also, fix BIOS_CNTL, which is 0xdc on ICH7. Build-tested with kontron/986lcd-m. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06The enable_hpet() code in intel/i82801gx will not work with theUwe Hermann
ICH7 southbridge (but it might work with ICH4/ICH5 or so). The ICH7 needs a different init code. Drop the non-working code for now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02Trim down the list of southbridges supported by the i82801xx driverUwe Hermann
to only a set of reasonably similar ones, namely (for now) ICH0* - ICH6*, and C-ICH. All later ICH* southbridges (ICH7-ICH10) are _very_ different and were surely not working with this driver anyway (and there's no chance to support them reasonably with this driver without ending up in #ifdef hell). ICH7 now has an extra driver in svn, whether ICH8-ICH10 are similar enough to be supported by that ICH7 driver remains to be seen. This patch was informally acked by Stefan Reinauer <stepan@coresystems.de> on IRC. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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