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2008-12-04The patch changes the LDTSTOP length as well mostly default content of 0xec,Rudolf Marek
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong. Furthermore this fix for powernow may not work on CPUs hit by errata #181. Workaround should be implemented. The powernow may not work on pre-A2 revisions of VT8237S silicon, revision reg is unknown. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01Add AMD rs690 VID DID reporting and some minor cleanups.Joe Bao
Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01Add AMD sb600 HPET setup and some minor cleanups.Joe Bao
Signed-off-by: Joe Bao <zheng.bao@amd.com> Reviewed-by: Maggie Li <maggie.li@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-14drop dead code in sb600 hdaStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06Drop #defines for registers that are not existant on the ICH7.Uwe Hermann
Also, fix BIOS_CNTL, which is 0xdc on ICH7. Build-tested with kontron/986lcd-m. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06The enable_hpet() code in intel/i82801gx will not work with theUwe Hermann
ICH7 southbridge (but it might work with ICH4/ICH5 or so). The ICH7 needs a different init code. Drop the non-working code for now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02Trim down the list of southbridges supported by the i82801xx driverUwe Hermann
to only a set of reasonably similar ones, namely (for now) ICH0* - ICH6*, and C-ICH. All later ICH* southbridges (ICH7-ICH10) are _very_ different and were surely not working with this driver anyway (and there's no chance to support them reasonably with this driver without ending up in #ifdef hell). ICH7 now has an extra driver in svn, whether ICH8-ICH10 are similar enough to be supported by that ICH7 driver remains to be seen. This patch was informally acked by Stefan Reinauer <stepan@coresystems.de> on IRC. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines.Uwe Hermann
Build-tested on kontron_986lcd_m. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29i945/ICH7: Use #defines from pci_ids.h (trivial).Uwe Hermann
Build-tested with the kontron/986lcd-m target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for the Intel ICH7 southbridge.Stefan Reinauer
This includes an early SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21I/O ports are 16bit, so change 'unsigned long port_base' to 'u16 port_base'.Uwe Hermann
Also, use more readable #defines instead of hardcoded config ports for PM/PM2 related functions, and simplify them a bit. Build-tested with the AMD dbm690t target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21Add missing license header.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-17Final fix for C7 boards, which are still using ROMCC, to be able toCorey Osgood
build. As far as I know, no C7 boards currently in the tree use SPI flash. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-17ROMCC chokes on vt8237_early_network_init(). Since that function is onlyCarl-Daniel Hailfinger
called from one target and that target is compiled with GCC, make the function dependent on GCC. ROMCC also chokes on the ULL suffix for integer constants. Change the affected ones to UL for ROMCC compiled code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-16Revision 3567 introduced __attribute__((packed)) for a structured whichCarl-Daniel Hailfinger
is also visible to ROMCC and ROMCC doesn't understand that. The fix is to use __attribute__((packed)) only for gcc compiled code. This has been unfixed for too long. There are more problems remaining, but at least this one is solvable easily. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-13Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be.Uwe Hermann
Build-tested with the AMD dbm690t board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-12Remove an extra bracket left by the vt8237r cleanup patch (trivial)Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-12VIA VT8237R cleanups (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-09Added comment about sb600 wideio setting for clarity and a minor witespace ↵Marc Jones
cleanup. (trivial) Signed-off-by: Marc Jones <marcj.jones@amd.com> Acked-by: Marc Jones <marcj.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-07[PATCH] coreboot: Don't loop forever waiting for HDA codecsJordan Crouse
We shouldn't assume the presence of a working HDA codec, so put in a reasonable timeout of 50usecs (timeout value borrowed from the kernel). This makes SimNow work, since apparently though the codec is present in Simnow, it is non functional. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-03Ron has been doing really good work over in v3. The problem is that the work ↵Marc Jones
got checked into v2. This should get us back to where we were. (trivial) Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02CK804 coding-style fixed based on an 'indent' run (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-02This is so that people can see it. This is the sb600 for v3. It almost Ronald G. Minnich
certainly won't build -- that comes later. I am hoping to get some eyeballs on it for simple errors. rs690 is next. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots ofCarl-Daniel Hailfinger
code to use it. That makes the code more readable and also less error-prone. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22Patch for AMD SB600 chipset.Michael Xie
Most of the functions in SB600 are enabled except power management. Signed-off-by: Michael Xie <Michael.Xie@amd.com> Reviewed-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22Patch for AMD RS690 chipset.Michael Xie
All the PCIe slots are enabled in this patch except power management. Signed-off-by: Michael Xie <Michael.Xie@amd.com> Reviewed-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-19Attached patch fixes at least one issue ;) During the PCI BAR sizing must ↵Rudolf Marek
be the D1F0 bridge without activated I/O and MEM resources, otherwise it will hang whole PCI bus. U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why does we not. Second small change just changes a bit which controls the PSTATECTL logic. Third change deals with the integrated VGA, which needs to be enabled early, so the VGA_EN is set along the bridges, and PCI K8 resource maps are set correctly. Finally the CPU accessible framebuffer is now disabled as it is not needed. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18ck804 whitespace fixesMyles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-05This patch adds support for the VIA VT8237S south bridge. The VT8237R ↵Rudolf Marek
programming remains unchanged (tested on mine desktop) except of reverting the small change introduced by Bari (gpio/inta setup reg 0x5b). This should go for some board specific file. The change would broke at least mine board. But seems to be needed for jakllsch. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Bari Ari <bari@onelabs.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-03Tidy up identifiers, per Uwe's suggestion. Trivial.Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-01This patch gets the Epia-CN working without ACPI or APIC.Bari Ari
All devices work, no irq storms. Enjoy. Signed-off-by: Bari Ari <bari@onelabs.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,Ed Swierk
and renames some existing macros for clarity. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25This patch modifies the Intel 3100 southbridge code to recognize theEd Swierk
integrated LPC, SMBus, USB and SATA devices of the Intel EP80579 Integrated Processor. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01coding style fixes (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-12There was a programming error which made most USB port4 setup wrong. This ↵Marc Jones
patch uses byte pointer and the MMIO read and write functions. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-20Extend the VIA vt8237r southbridge decode range for the ROM to 1MB.Bari Ari
Signed-off-by: Bari Ari <bari@onelabs.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07Implement GPIO configuration routines for the Intel 3100 southbridge,Ed Swierk
allowing you to specify per-mainboard GPIO settings. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only ↵Marc Jones
doing a pci_write_config8. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-30By default, the Intel 3100 LPC interface enables only I/O range 0x3f8Ed Swierk
for both serial ports, making it challenging to use COM2 for the early console. Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23This patch fixes the 3 broken sata ports on the Tyan s2891 (primary port onWard Vandewege
secondary controller was ok). There were two problems: the master sata controller was not being initialized, and the irqs for the secondary ports on both controllers were not being set in the mptable. Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem. While all ports work reliably under a recent kernel (2.6.24), sata is about half as fast as under the proprietary bios, according to bonnie++. That still needs fixing... Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-06This patch halts the tco timer early in the boot process on all ICH series ↵Joseph Smith
southbridges. It also keeps the boot processes from rebooting through out the coreboot process. Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01Setting an integrated southbridge device (like SATA or USB2.0) toEd Swierk
"off" in Config.lb should cause the PCI device not to respond to configuration requests. Replace the existing code that I naively copied from esb6300 with something that actually works on the 3100. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01Remove i82801DB files that I meant to delete in r3206.Joseph Smith
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01Tiny style fix for consistency (trivial).Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01Removal of i82801DB (ICH4)Joseph Smith
There are no boards that use the i82801DB (ICH4). The code does NOT work. Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-01The early init code of several Intel southbridge chipsets callsEd Swierk
pci_locate_device() to locate the SMBus controller and LPC bridge devices on the PCI bus. Since these devices are always located at a fixed PCI bus:device:function, the code can be simplified by hardcoding the devices. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-30Like other Intel chipsets, the Intel 3100 has a TCO timer that rebootsEd Swierk
the system automatically unless software resets the timer periodically. The extra reboot extends boot time by several seconds. The attached patch adds a function to the Intel 3100 southbridge code that halts the TCO timer, thus preventing this extra reboot, and calls the function early in the boot process on the Mt. Arvon board. It also fixes a bug in the LPC device initialization -- the ACPI BAR enable flag is bit 7, not bit 4. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29Now coreboot performs IRQ routing for some boards.Nikolay Petukhov
You can see this by executing commands like this: grep -r pci_assign_irqs coreboot/src/* This basically AMD/LX based boards: pcengines/alix1c, digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800. Also for AMD/GX1 based boards need a patch [http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch] for the right IRQ setup. AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320, bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p. I have two ideas. 1. Delete duplicate code from AMD/LX based boards. 2. Add IRQ routing for AMD/GX1 boards in coreboot. The pirq.patch for IRQ routing logically consist from of two parts: First part of pirq.patch independent from type chipsets and assign IRQ for ever PCI device. It part based on AMD/LX write_pirq_routing_table() function. Second part of pirq.patch depends of type chipset and set PIRQx lines in interrupt router. This part supports only CS5530/5536 interrupt routers. IRQ routing functionality is included through PIRQ_ROUTE in Config.lb. Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on TeleVideo TC7020, see http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-20Following patch adds K8M890 support. It initializes the AGP and graphics UMA.Rudolf Marek
The V-link setup and HT bridge is redone, because VT8237A has it in another device. So far following combination of chipsets should now work: K8T890CE + VT8237R K8M890(CE) + VT8237R VIA PC1 brige moved to NB code (vt8237r_bridge.c -> k8t890_bridge.c) and notes about K8M890 support were added. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-19Following patch will setup KT890 HT automatically. It will find theRudolf Marek
max width of the link and also it will take the frequency of K8 HT already done coreboot (and checks if t can run on it). Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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