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2018-05-04superio/ite/common: Add options to enable beepsVagiz Trakhanov
Add device tree options to enable beeps when exceeding temperature, voltage, and fan limits. As of this commit, setting voltage and fan limits is not implemented. Change-Id: I57ce622ee4498b75f00e678c2e6d72e499925bce Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/22141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-15Intel i3100 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-07superio/ite/it8623e: add support for SIO chip ITE IT8623EGergely Kiss
This change adds basic support for the SuperIO chip ITE IT8623E. Due to the lack of a datasheet, defaults are shown as "not available (NA)" in superiotool's register dump. LDNs defined in it8623e.h are definitely correct and working as expected. Change-Id: I05832c4db7ab59541337f11200640316376e792e Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/23001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07superio/f71869ad: Add temperature sensor typeRenze Nicolai
This patch makes it possible to set the "Temperature Sensor Type Register" at index 6Bh from the devicetree, allowing the use of thermistors instead of BJT type sensors. Register documentation (from page 60 of the F71869 datasheet): 6.6.25 Temperature Sensor Type Register - Index 6Bh Bit 7-4: reserved Bit 3: T3_MODE (0: thermistor, 1: BJT [default]) Bit 2: T2_MODE (0: thermistor, 1: BJT [default]) Bit 1: T1_MODE (0: thermistor, 1: BJT [default]) Bit 0: reserved Change-Id: I6af0d93061ec49aec7a9181cdf7affd60fbdca73 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/22935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07nuvoton/nct6776: Add ACPI declarationsTobias Diedrich
Add ACPI declarations to be incorporated into ACPI tables for mainboards with this super I/O. Tested on Intel NUC DCP847SKE, Linux 4.13.14. Change-Id: Idb76b2e99e90a213e2695efc1afd4fa9069c134f Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-06superio/ite: add missing pnp_conf_mode fields in ops structFelix Held
This fixes the bug that the LDNs on the affected SIO chips didn't get configured, since the config mode wasn't entered. Change-Id: Ic468847571e164e4e1280428f08fc067b724464e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/23004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-02winbond/w83977tf: Add ACPI declarationsKeith Hui
Add ACPI declarations to be incorporated into ACPI tables for mainboards with this super I/O. Change-Id: If113807901619bc0f4250607546be415f9e5e45b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-30nuvoton/nct5572d: Disable mouse controller also during resumePaul Menzel
Currently, having a keyboard connected to the PS/2 controller of the ASRock E350M1, after suspending and resuming the system, the keyboard does not work anymore. A similar problem is documented in commit 448e3863 (drivers/pc80: Add PS/2 mouse presence detect) [1]. There is no reason to not disable the controller during resume. Also, that way, the PS2 ASL method does not need to be overriden. [1] https://review.coreboot.org/13165 TEST=Resume system, and notice PS/2 keyboard works. Change-Id: I51dc446861120f80bc9ffc4cc54b86e317d99689 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-11-30superio: Log if mouse controller is disabledPaul Menzel
It’s useful to know, if the mouse controller is disabled or not, so convert the comment to a log message. Change-Id: Ic3f7d5b7b98cf8c258a6a601f4a44ce403f4a576 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-10-25superio/acpi/pnp.asl: Fix PNP_READ_DMA/PNP_WRITE_DMA macrosKeith Hui
These macros, broken since day one, should CreateByteField instead of CreateWordField. Without the fix, any ASLs that try to use it will fail to compile with a "ResourceTag smaller than Field" warning. Change-Id: Ieeb509aece8836785998b23fdc805a747d40a77a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22superio/ite/common: Make PECI a thermal modeVagiz Trakhanov
Instead of setting "peci_tmpin" in the devicetree, THERMAL_PECI is now a mode of TMPIN like THERMAL_RESISTOR and THERMAL_DIODE. Since the logic to set temperature offsets and limits is in the function that sets thermal modes, it makes sense to treat PECI as yet another mode. As of this commit, there are no boards that actually use peci_tmpin from ite/common. There are three boards that have a similar device tree option, but those boards use it8772f, which implements all superio functions on its own. The first user will probably be Gigabyte GA-Z77-DS3H. Change-Id: I39da50c124ad767f8681302733cf004622975e81 Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/22076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22superio/ite/common: Add temperature limitsVagiz Trakhanov
Add devicetree options to set temperature limits that are used to alarm user when temperature exceeds defined values. Audio alerts by superio are not implemented yet, but since limits are visible to userland, some software might use them as is. For instance, lm-sensors displays "ALERT" when temperature exceeds limits. Change-Id: I56e041fb78f518d6a9640dc2b3985459991242b9 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-22superio/ite/common: Add temperature offsetVagiz Trakhanov
Add a devicetree option to set temperature adjustment registers required for thermal diode sensors and PECI. However, this commit does not have the code needed to make PECI interface actually use these registers. It only applies to diodes. As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3". PECI, apparently, takes precedence over diode, so the adjustment register will be set and PECI activated. Or simply use the followup patch, which makes THERMAL_PECI a mode like THERMAL_DIODE. I don't have hardware to test THERMAL_DIODE mode, but in case of PECI, without this patch I had about -60°C on idle. Now, with offset 97, which was taken from vendor bios, PECI readings became reasonable 35°C. TEST=Set a temperature offset, then ensure that the value you set is reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4 Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/21843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-21winbond/w83627hf: Drop early_init.cKeith Hui
Once w83627hf_set_clksel_48() is unified into winbond/common/early_init.c by /c/21331 (Unify w*_set_clksel_48()), this file is no longer needed and can be dropped. Build tested on select affected mainboards. Change-Id: I6a5e27fdd48c6e002c3a39dc92fef77e85aea209 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-21winbond/w83697hf: Drop early_serial.cKeith Hui
It is already using winbond_enable_serial(). Once w83697hf_set_clksel_48() is unified into winbond/common/early_init.c, this file is no longer needed and can be dropped. Change-Id: I7424233b5d70e143721038493f194760f07346a1 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-21superio/winbond/*: Unify w*_set_clksel_48()Keith Hui
This function is identical throughout all Winbond superios in the tree, so move it into superio/winbond/common/early_init.c, renamed from early_serial.c because it now does more than just early serial. Change all affected mainboards to use the unified function. Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21superio/winbond/w83627*: Remove deprecated codeKeith Hui
Early serial for W83627[HF|EHG] superios are handled by superio/winbond/common/early_serial.c. Remove code thus deprecated. Build tested on select affected mainboards. Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-15superio/winbond/w83977tf: Drop early_serial.cKeith Hui
Early serial init on this superio is done by superio/winbond/common/early_serial.c and no board currently references this instance anymore. Change-Id: Iab8dd93663fc78ed0d8c6a5313bb6a1884d1a043 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/20978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-06sio/smsc/kbc1100: Fix some style issuesArthur Heymans
This fixes indentation and whitespaces before opening parentheses. Change-Id: I8940f712c0161419ee0c383b7bc9eb581967366e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-07-08superio/ite/it8716f: Update init_ecMartin Roth
This is a follow-on to the superio IS_ENABLED() patch: https://review.coreboot.org/#/c/20351/1 Change-Id: I7d070e3964609947959de60e2686dfe59fe77e1c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-07src/superio: add IS_ENABLED() around Kconfig symbol referencesMartin Roth
Change-Id: Ie9a7127b50db8dc9a2b543843ca4d815afe3d07e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-13device/pnp: remove struct io_infoSamuel Holland
The 'set' field was not used anywhere. Replace the struct with a simple integer representing the mask. initializer updates performed with: sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \ src/ec/*/*/ec.c sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \ src/ec/*/*/ec_lpc.c \ src/superio/*/*/superio.c \ src/superio/smsc/fdc37n972/fdc37n972.c \ src/superio/smsc/sio10n268/sio10n268.c \ src/superio/via/vt1211/vt1211.c src/ec/kontron/it8516e/ec.c was manually updated. The previous value for IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and had a zero bit in the middle of the mask. Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Myles Watson <mylesgw@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-12superio/ite/it8720f: add new IT8720F Super I/OSamuel Holland
This device is extremely similar to the IT8718F, so support is based on existing support for the IT8718F. The CIR device is only detected by Linux/Windows from the ACPI tables, so ACPI support is extended from the IT8783E/F (for ACPI). This Super I/O is used on the Foxconn G41S-K. Tested, working: * Serial port 1 * Environment controller - Temperature monitoring - Voltage monitoring - Fan control (automatic and manual) * PS/2 keyboard and mouse Appears, OS driver loads, but otherwise untested: * Serial port 2 * Consumer IR Untested: * Floppy controller * Parallel port * GPIO Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-12superio/ite/it8728f: remove unused headerSamuel Holland
Change-Id: Ifcbf95ffd6d13cae4e6864e0320ce6ce1cf3ae4d Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-12superio/ite/common: fix prototype to match othersSamuel Holland
Change-Id: Id4a079d868c5c806c769b5559833566e8a6a8a71 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-12superio/acpi: allow custom HID on generic deviceSamuel Holland
Some Super I/O PnP devices are detected by string matching the hardware ID. Allow providing a custom HID to override the default generic one. Change-Id: I7793b7d53c9d94667675f9dee63358521ac8c4be Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-12superio/acpi: allow 3 I/O ranges on generic deviceSamuel Holland
Some Super I/O logical devices have three I/O port ranges, such as the GPIO on the IT8720F. Allow specifying a third I/O range. While here, fix a typo in the I/O range description. Change-Id: Idad03f3881e0fbf2135562316d177972f931afec Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-06-04superio/winbond/*/header: Include <arch/io.h>Arthur Heymans
Include <arch/io.h> since functions use types defined in there. Change-Id: Iba6bcea4377359c15e3148062458186ee222b8e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-05-11superio/nuvoton: Make SuperIO config functions externally availableArthur Heymans
Change-Id: I05f768c67542770e65279a562c05225b84edca40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-05-09superio/ite/it8728f: Hook up common environment-controller driverTobias Diedrich
This replaces the custom environment controller handling in the it8728 driver with the common library. It also updates the two existing boards with hwm register settings in their devicetree config so they better match their vendor BIOS fan control settings. Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/19293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-03-27superio/fintek: Add support for Fintek F71808ANicola Corna
This chip is similar to the Fintek F71869AD. Change-Id: Iba3f3dadf2b15071981f52d0b08da7847354bd23 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/18563 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-12-13sio/ite/it8783ef: Return (0) in ACPI _PSC methodsNico Huber
Current ACPI code for UARTs uses the PNP_DEFAULT_PSC macro for _PSC (current power state) methods. Override it to `Return (0)` (i.e. cur- rent state is D0) as the IT8783E/F doesn't have power management. Change-Id: I3c858dde287dbf7e5fc0c20abb1fd374887acdde Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17791 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-07sio/ite/it8783ef: New super i/o chipNico Huber
This will be used by new Roda boards. Four UARTs and PS/2 keyboard and mouse are exposed to ACPI. Since our boards only use the environment controller part, most of the usual pnp interfaces are untested. Change-Id: Ifeb0327ad115759411716f82585ace5ce55b8464 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17287 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07sio/acpi: Add more magic bytes to ENTER/EXIT_CONFIG_MODENico Huber
ITE super-i/o chips need a fourth byte and have a special register to exit config mode. Change-Id: Ic40873649d567b87d3a937f2bf068649e67715de Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17286 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-07sio/ite/common: Export pnp_enter/exit_conf_state()Nico Huber
Change-Id: I8cbfe49516e685c1b3e150b23f9fcac513f1f3dc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17285 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-28sio/nuvoton: Include generic nuvoton driver in bootblock stageTeo Boon Tiong
The purpose of this change is to enable serial output in bootblock stage Change-Id: I8e075f1e70d1a6598dfdc34931218f5af9637178 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17359 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-28common Ite EC driver: Enable PWM smoothing via devicetreeArthur Heymans
The devicetree parameter already existed without being used in the code. Change-Id: I99dd8bc7a9b2f3509a115a130062d462a62e33fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17614 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-28sio/it8718f: Hook up common environment-controller driverArthur Heymans
Change-Id: I25019c6323b6e9de2e0ce19325266bf3e8f2e309 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17581 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-21smscsuperio: map interrupt in smscsuperio_enable_serial()Jonathan A. Kollasch
This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the interrupt is unmapped at reset, but for whatever reason the chip is inaccessible in smscsuperio/superio.c::enable_dev() and thus the devicetree.cb IRQ information is not applied in ramstage and then serial console output fails to work for more than the UART FIFO depth in the OS. Change-Id: I00998088975569516f7caeb7f4098b48fe437889 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: https://review.coreboot.org/10807 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-11-18sio/it8772f: add GPIO blink definition needed by google/trickyMatt DeVillier
Change-Id: I597ba3a03bd42c64d03137b10a3758d86b129029 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17452 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17sio/ite/common: Add generic environment-controller driverNico Huber
The environment-controller entity is shared by many ITE super-i/o chips. There are some differences between the chips, though. To cover that, the super-i/o chip should select Kconfig options of this driver accordingly. The current implementation isn't exhaustive: It covers only those parts that are connected on boards I could test, plus those that are currently used by the IT8772F. The latter could be ported to use this driver if somebody minds to test it. Change-Id: I7a40f677f667d103ce1d09a3e468915729067803 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/17284 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-19winbond/w83627ehg: Remove unnecessary valueElyes HAOUAS
Change-Id: I5f88f34d1c040ac6ed413cfaf8ceb45a358c117c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-01sio/winbond/w83627dhg: Add ACPI function to control suspend LEDNico Huber
Change-Id: Ie2062672233141b6f34625e59cbb50238be0b5fa Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16726 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01superio/nuvoton: Add back Nuvoton NCT6776 supportTeo Boon Tiong
Revert commit 53552cc0 (Drop SuperIO nuvoton/nct6776), removing the code as no other mainboard uses it. The board Intel Saddle Brook uses this device, so add the code back with minor adaptations. Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/16519 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-20src/superio: Add space around operatorsElyes HAOUAS
Change-Id: Ibeab5e7fe0a9005e96934b3b43cfb247ef2e2340 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16615 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-05src/superio: Improve code formattingElyes HAOUAS
Change-Id: I8597d205ca84bee0171c3d45549a28b58a050529 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16433 Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-09-02Fix newlines at the end of filesMartin Roth
All but ga-g41m-es2l/cmos.default had multiple final newlines. ga-g41m-es2l/cmos.default had no final newline. Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16361 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-08-09superio/*: Relocate Kconfig to chip folder.Omar Pakker
This moves the Kconfig from the Super I/O manufacturer folder to the chip folder instead. This makes new chip commits self-contained unit as edits to the central Kconfig file are no longer required. Change-Id: I7aee07919f2ae9204850c669e0ed3cb17d4de8cd Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/15973 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2016-08-02superio/fintek/f81866d: Add support for UART 3/4Fabian Kunkel
Pins for UART 3/4 are by default GPIO pins. This patch sets the pins in UART mode. Since UART 1/3 and 2/4 share the same interrupt line, the patch needs to enable also shared interrupts. Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15564 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31superio/nuvoton: Add Nuvoton NCT6791DOmar Pakker
This adds support for Nuvoton NCT6791D Super I/O chips. Makes use of the common Nuvoton early_serial.c. Based on the Datasheet supplied by Nuvoton. Datasheet Version: January 8th, 2016 Revision 1.11 Change-Id: I027d33b85f0dc6ee50deebdccaecc74487eecb40 Signed-off-by: Omar Pakker <omarpakker+coreboot@gmail.com> Reviewed-on: https://review.coreboot.org/15967 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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