Age | Commit message (Collapse) | Author |
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Move the floppy drive enumeration from _INI() and PROB(),
which stored the enumeration results into _FDE into _FDE().
_INI is called by any ACPI-capable OS on boot while _FDE
is rarely used. So it's better to run the enumeration when
requested rather than unconditionally.
Change-Id: Icf1e2a551806592faa8ba8d80fa8d02681602007
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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The parallel port of the W83627HF can be configured on any port
between 0x100 and 0xFFC with 4 byte alignment for traditional modes
and 8 byte alignment for EPP mode. As the ACPI specification says
that the maximum acceptable starting address has to be a multiple
of the alignment granularity, correct the maximum starting address
from 0xFFC to 0xFF8.
Change-Id: I272e09d091149791f2867b1d06e4fc27bc1bb2cd
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/2942
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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As Nico noticed for the W83627DHG, the power management bits to power down
individual logical devices on Winbond superios are named counterintuitively
and need to be set when the logical device should be powered.
This corrects the power management methods for the W83627HF.
Change-Id: I98bccd550a0513c62bfa9480275f88c566691bc8
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3605
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This is the first of a series of patches to provide support
for a new mainboard, Gigabyte GA-B75M-D3V.
This patch provides early serial for the superio and has been
tested on this mainboard. The code is based on IT8718F superio.
Change-Id: I5636199b49314166ed3b81e60b41131964dd44ff
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/3794
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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The enumeration results are stored as five DWORDs in one 20 byte buffer.
Bytes 3, 7, 11 and 15 were used to set the lowest bit of each DWORD.
ACPI uses little endian, so 1, 4, 8 and 12 are the correct indices.
Change-Id: I793225cb1bb62fd148ecfa1e61e02f5d7be62cdb
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3602
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The PnP's logical device activation normally resides at 0x30. This might
have been overlooked as 0x29 looks very close to 0x30 in human eyes.
Change-Id: Id5d5a92f2683ebe1808b943f686c062151d216da
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The enumeration method tried to evaluate an one-byte OperationRegion
instead of a field in this OperationRegion, which resulted in an
AE_TYPE error at runtime.
Indexing the OperationRegion with a single field fixes this error.
Change-Id: I15dd7aa6ecafb3a215d165d2b721003446815025
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3603
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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The W83627DHG has some power managements bits to power down individual
logical devices. These are called `* Power Down`. Counterintuitively and
in contrast to `Immediate Power Down` (bit to power down the whole chip),
these bits are set when the respective logical device is powered.
Unfortunately, our ACPI code set them wrong which led to disabled
devices after a S3 suspend/resume. Adding an option how to set the PM
bits and setting them to zero for the W83627DHG, corrects it.
Tested with kontron/ktqm77.
Change-Id: I8a472d480d4277721bd17c9f7c2ce44fa84e8ae2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3590
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Implement some common default functions to enter and exit the
configuration state. Also provide default pnp_mode_ops for common
enter()/exit() function pairs.
The following cocci ensures their use:
@ mode_match @
identifier enter, exit, ops;
@@
struct pnp_mode_ops ops = {
.enter_conf_mode = enter,
.exit_conf_mode = exit,
};
@ enter_match_8787 @
identifier mode_match.enter, dev;
@@
enter(...)
{
outb(0x87, dev->path.pnp.port);
outb(0x87, dev->path.pnp.port);
}
@ depends on enter_match_8787 @
identifier mode_match.enter, mode_match.ops;
@@
struct pnp_mode_ops ops = {
- .enter_conf_mode = enter,
+ .enter_conf_mode = pnp_enter_conf_mode_8787,
};
@ enter_match_55 @
identifier mode_match.enter, dev;
@@
enter(...)
{
outb(0x55, dev->path.pnp.port);
}
@ depends on enter_match_55 @
identifier mode_match.enter, mode_match.ops;
@@
struct pnp_mode_ops ops = {
- .enter_conf_mode = enter,
+ .enter_conf_mode = pnp_enter_conf_mode_55,
};
@ depends on enter_match_8787 || enter_match_55 @
identifier mode_match.enter;
@@
-enter(...) {...}
@ exit_match_aa @
identifier mode_match.exit, dev;
@@
exit(...)
{
outb(0xaa, dev->path.pnp.port);
}
@ depends on exit_match_aa @
identifier mode_match.exit, mode_match.ops;
@@
struct pnp_mode_ops ops = {
- .exit_conf_mode = exit,
+ .exit_conf_mode = pnp_exit_conf_mode_aa,
};
@ depends on exit_match_aa @
identifier mode_match.exit;
@@
-exit(...) {...}
@ depends on enter_match_8787 || enter_match_55 || exit_match_aa @
@@
#include <device/pnp.h>
+#include <superio/conf_mode.h>
@ mode_match_55_aa @
identifier ops;
@@
struct pnp_mode_ops ops = {
.enter_conf_mode = pnp_enter_conf_mode_55,
.exit_conf_mode = pnp_exit_conf_mode_aa,
};
@@
identifier mode_match_55_aa.ops;
@@
-struct pnp_mode_ops ops = {...};
@@
identifier mode_match_55_aa.ops, devops;
@@
struct device_operations devops = {
- .ops_pnp_mode = &ops,
+ .ops_pnp_mode = &pnp_conf_mode_55_aa,
};
@ mode_match_8787_aa @
identifier ops;
@@
struct pnp_mode_ops ops = {
.enter_conf_mode = pnp_enter_conf_mode_8787,
.exit_conf_mode = pnp_exit_conf_mode_aa,
};
@@
identifier mode_match_8787_aa.ops;
@@
-struct pnp_mode_ops ops = {...};
@@
identifier mode_match_8787_aa.ops, devops;
@@
struct device_operations devops = {
- .ops_pnp_mode = &ops,
+ .ops_pnp_mode = &pnp_conf_mode_8787_aa,
};
Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3484
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Add comments in PAR0._PRS explaining which dependent resource
descriptor puts the parallel port into EPP or SPP mode.
Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3495
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
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The SPI logical device on the W83627DHG uses the second i/o port
register pair but not the first one. So we have to also set `io1`
(the second io_info struct) and not `io0` in the pnp_info structure.
Setting the PNP_IO1 flag without a mask in `io1` caused coreboot to
hang in pnp_enable_devices() until commit aeead274 which added a
check for an unset mask.
Change-Id: I027d279b4641fecd88afb14d40fbe1c0bfbf81bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3391
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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After removing the enter()/exit() functions for configuration mode,
most wrappers for our standard PnP functions just call the underlying
default implementation.
Remove those with a little cocci:
@ op_match @
identifier op;
identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
type device_t;
identifier dev;
@@
static void op(device_t dev) { pnp_op(dev); }
@@
identifier op_match.op;
@@
-op(...) {...}
/* Three rules to match the alignment, hmmp... */
@@
identifier op_match.op, op_match.pnp_op;
identifier ops;
@@
struct device_operations ops = {
- .set_resources = op,
+ .set_resources = pnp_op,
};
@@
identifier op_match.op, op_match.pnp_op;
identifier ops;
@@
struct device_operations ops = {
- .enable_resources = op,
+ .enable_resources = pnp_op,
};
@@
identifier op_match.op, op_match.pnp_op;
identifier ops;
@@
struct device_operations ops = {
- .enable = op,
+ .enable = pnp_op,
};
Change-Id: Idc0e52c7e3600a01f3b6a4e17763557b271b481e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3483
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Find all the (ramstage) implementations of enter()/exit() functions
for the configuration state, register and call them through the new
struct pnp_mode_ops. As our standard PnP functions are aware of the
pnp_mode_ops, it's not necessary to call enter()/exit() around them
anymore.
Patch generated with the cocci below. It's not perfect. The movement
of the enter()/exit() calls is somehow fragile. So I checked the
remaining calls for sense, and changed some empty lines. Also a
duplicate insertion of pnp_conf_mode_ops had to be removed.
/* Try to find enter and exit functions by their outb() structure and
their usage around calls to our standard pnp functions: */
@ enter_match @
identifier enter;
identifier dev;
type device_t;
@@
void enter(device_t dev)
{
<...
outb(..., dev->path.pnp.port);
...>
}
@ exit_match @
identifier exit;
identifier dev;
type device_t;
@@
void exit(device_t dev)
{
<...
outb(..., dev->path.pnp.port);
...>
}
@ pnp_match @
identifier op;
identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
identifier enter_match.enter, exit_match.exit;
type device_t;
identifier dev;
@@
void op(device_t dev)
{
...
enter(dev);
...
pnp_op(dev);
...
exit(dev);
...
}
/* Now add enter/exit to a pnp_mode_ops structure: */
@ depends on pnp_match @
identifier enter_match.enter;
identifier exit_match.exit;
identifier ops;
@@
+static const struct pnp_mode_ops pnp_conf_mode_ops = {
+ .enter_conf_mode = enter,
+ .exit_conf_mode = exit,
+};
+
struct device_operations ops = {
...,
+ .ops_pnp_mode = &pnp_conf_mode_ops,
};
/* Match against the new structure as we change the code and the above
matches might not work anymore: */
@ mode_match @
identifier enter, exit, ops;
@@
struct pnp_mode_ops ops = {
.enter_conf_mode = enter,
.exit_conf_mode = exit,
};
/* Replace enter()/enter() calls with new standard calls (e.g.
pnp_enter_conf_mode()): */
@@
identifier mode_match.enter;
expression e;
@@
-enter(e)
+pnp_enter_conf_mode(e)
@@
identifier mode_match.exit;
expression e;
@@
-exit(e)
+pnp_exit_conf_mode(e)
/* If there are calls to standard PnP functions, (re)move the
enter()/exit() calls around them: */
@@
identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
expression e;
@@
-pnp_enter_conf_mode(e);
pnp_op(e);
+pnp_enter_conf_mode(e);
...
pnp_exit_conf_mode(e);
@@
identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
expression e;
@@
pnp_enter_conf_mode(e);
...
+pnp_exit_conf_mode(e);
pnp_op(e);
-pnp_exit_conf_mode(e);
@@
expression e;
@@
-pnp_enter_conf_mode(e);
-pnp_exit_conf_mode(e);
Change-Id: I5c04b0c6a8f01a30bc25fe195797c02e75b6c276
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3482
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The current default implementation of pnp_enable() only disables devices
- if set so in the devicetree - but does not enable them. Enablement takes
place in pnp_enable_resources(). Yet, many PnP chips implement their own
version of pnp_enable() which also enables devices if set in the devicetree.
It's arguable, if enabling those devices makes sense, before they get
resources assigned. Maybe we can't write the resource registers if not,
who knows? The least we can do is providing a common implementation for
this behavior, and get rid of some code duplication.
Used the following cocci:
@@
expression e;
@@
+pnp_alt_enable(e);
-pnp_set_logical_device(e);
(
-pnp_set_enable(e, !!e->enabled);
|
-(e->enabled) ? pnp_set_enable(e, 1) : pnp_set_enable(e, 0);
|
-if (e->enabled) { pnp_set_enable(e, 1); }
-else { pnp_set_enable(e, 0); }
)
Change-Id: I8d695e8fcd3cf8b847b1aa99326b51a554700bc4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3480
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Most PnP drivers align the initialization of their `device_operations`
with spaces. Unify this, so next autogenerated patches always match the
alignment.
Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3479
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This is loosely based on Christoph Grenz' ACPI code for the W83627HF
and makes use of the PnP super i/o ACPI framework.
Change-Id: I5e1cd09b83c0041f440562d2a1b73e4560589cb7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3288
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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I'm trying to make writing ACPI code for super i/o devices more
comfortable.
pnp.asl hosts some general cpp macros.
The other four files are to be included in dsdt trees. They are
controlled by cpp macros which should be defined/undefined before
inclusion.
Work was inspired by Christoph Grenz' ACPI code for the W83627HF.
Change-Id: Idb55332ba9bc788c98964d30a450e0d734cf28ec
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3286
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1]
made romcc not choke on function prototypes anymore. This
allows us to get rid of a lot of ifdefs guarding __ROMCC__ .
[1] http://review.coreboot.org/2424
Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3216
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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- Added in new support for Nuvoton NCT5104D LPC device.
Change-Id: I0af8c5e3e46fdd0a549475b30917897ae9e144a7
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/3072
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Put the ASL snippet for inclusion in the DSDT under the `acpi/`
folder as it is done for the other Super I/O devices.
$ find src/superio/ -name *asl
src/superio/ite/it8772f/acpi/superio.asl
src/superio/smsc/mec1308/acpi/superio.asl
src/superio/smsc/sio1007/acpi/superio.asl
src/superio/winbond/w83627hf/devtree.asl
As there are no users of this file yet, no other adaptations need
to be made.
Change-Id: Id10cd8897592b780c9fd3bd6b45ada4cf1fcf33e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2937
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.
Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.
Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Pins 78-85 are set to GPIO after power on or reset. To enable
UART B the pins must be redirected to it.
Look at W83627DHG databook version 1.4 page 185 Chip
(global) Control Register CR2C.
Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845
Signed-off-by: Wolfgang Kamp <wmkamp@datakamp.de>
Reviewed-on: http://review.coreboot.org/2626
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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The power up default for the 14M_25M_48M_OSC switchable clock output ball of
the SB800 chipset is 14 MHz. sb800/bootblock.c changes this to 48 MHz,
which is the correct value for almost all SIOs. However, not for
'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not
configurable for other clock speeds. A wrong SIO clock supply results in
funny RS232 output (wrong bit speed) and non-working PS/2.
We could switch back to 14 MHz in the mainboard's romstage.c, but then the
clock frequency would change twice. The resulting short 48 MHz burst causes
a handful of rubbish characters on RS232 on every boot until the SIO clock
has stabilized again.
This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz.
This does not affect any boards currently in the repository (yet).
Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2454
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
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In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.
Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
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This is the smallest possible change to make early_serial.c
compile when included from romstage.c.
early_serial could be reworked to be built as separate unit
(romstage-y), but that should be done for all SuperIOs,
not some individual outlier.
Change-Id: I90ee66b43c9677b86b1b5d6fcc8febfbe58d80dd
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1686
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Also deletes files not included in build:
src/southbridge/amd/cimx/sb700/chip_name.c
src/southbridge/amd/cimx/sb800/chip_name.c
src/southbridge/amd/cimx/sb900/chip_name.c
Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1473
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
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this function is used on serial output of tyan s8226
Change-Id: I5f7fa535b922b224e381886f1bea64623fa549ef
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1494
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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The name is derived directly from the device path.
Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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Change-Id: Id5756f1bb748ae7bec0bcdc21804f5338e850baa
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1402
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Not all users use both functions, so add __attribute__((unused))
to prevent compiler errors.
Change-Id: I8485bb9150b04d1f9fdc231152a43bcd6fc713a7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1193
Tested-by: build bot (Jenkins)
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Change source file modes from 755 to 644
The following files have been grepped for changes:
*.c
*.h
*Kconfig*
*Makefile*
Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/1023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
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Newer versions of IASL didn't like our IO constructs. Use
FixedIO instead, it's also shorter.
Change-Id: I9364d993ecb71ffd84c0313ca1e2f870af59eb24
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/934
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: If7921a66bab35f72c8455d5f0befc32a514ab417
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/825
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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early_serial and some ACPI needed for compilation
Change-Id: I5dd970676488697156e0630392884f31149ac85b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/824
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This includes only early serial support for now.
Change-Id: I9a2a439e1d17a989428033fdb4a4b813553dab6d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/823
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I8e80c22eb0f3cb68f2457be6b2e7894df60ed632
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/822
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/563
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/562
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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1. Stop include c file.
2. W83627dhg Pin 89, Pin 90 are multi function pins,
add support to select them to I2C function.
Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/565
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Compile Nuvoton WPCM450 early_init.c when CONFIG_SUPERIO_NUVOTON_WPCM450
Change-Id: Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/566
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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When CONFIG_EXPERT is set, compilation fails with:
src/superio/winbond/w83627hf/superio.c:61:13: error: ‘w83627hf_16_bit_addr_qual’ defined but not used [-Werror=unused-function]
cc1: all warnings being treated as errors
This function isn't used in the code, so just remove it.
Change-Id: I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/533
Tested-by: build bot (Jenkins)
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Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/384
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
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make w83697hf_set_clksel_48() non-static and add a prototype so as to
get rid of warnings about it being unused
Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I984404dd1df50b3ba423ac610283b9bf8bca5a31
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/412
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Fix multiple copy&paste errors and some other bugs in
devtree.asl. Redesign ENCM method to enter configuration mode
and set LDN by parameter. Reordered and commented some
statements to make the code a bit more readable. Add an ifdef
to enable never showing the keyboard controller as disabled,
which seems to cause bugs at least with some Linux kernels.
Remove keyboard controller IO regions from PS/2 mouse device
as e.g. Linux infers them from the keyboard controller device.
Change-Id: I44611339fabe31a8a584a3e6bd225082bfdd0b8e
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/357
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Drop explicit Scope(\_SB) from devtree.asl as it forces the SuperIO
to appear as child of the root device.
devtree.asl then needs to be included at a reasonable position inside
the \_SB device tree.
Change-Id: I72a57eddc5ec5f9763fdf789094a7be042758256
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/298
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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Add a method WAKS to devtree.asl which returns the wake-up source register
to simplify retrieving the wake source e.g. in \_WAK.
Change-Id: Ia258f8fc9ff79b18391c55464da73863889e2255
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/297
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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