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2014-04-26superio/ite/it8673f: Remove poor implementationEdward O'Callaghan
Following the reasoning of: HASH superio/ite/it8705f: Remove poor implementation Change-Id: Ic0722116b84acf4f3c3ef4b18b961a56f0f50718 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5568 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26superio/ite/it8705f: Remove poor implementationEdward O'Callaghan
This super io support is poorly implemented and would not work for all boards since it hardcodes values. Since there are no users of it, remove for now pending a fresh reimplementation from scratch. Change-Id: I818a9f4d2ab106b989824e49cee49d79acd6041a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5566 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26superio/ite/it8716f: Rewrite from hardcoded base addrEdward O'Callaghan
Following the same reasoning as: HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr Removing hard coded magics and expose sio pnp api in romstage. Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5565 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26superio/ite/it8721f: Rewrite from hardcoded base addrEdward O'Callaghan
Rewrite early_serial.c implementation to honour a passed base address in device_t, removing any hard coding of values. We also expose early sio init functions as romstage symbols to avoid falsely #including "early_serial.c" in romstage.c of board support. Change-Id: I521b8f7cf85173345b90745c6f2ab66e25429f5d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5561 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-15superio/ite/it8728f: Fix headers and prototype locationEdward O'Callaghan
Try to conform to some kind of standard/consensus for prototype location. Correct headers while here. Change-Id: Ie99b1801fa42ddefb9f25d54f326ba7131bd7089 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5499 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09uart: Redefine Kconfig optionsKyösti Mälkki
Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5311 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06superio/winbond/w83627thg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I1f7c20ac7841874125b6bfcd9f9db25d96355881 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5449 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06superio/nuvoton/nct5104d: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I14c438968bfed917977862efd8a393ec48cb04c9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5446 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06superio/winbond/w83627ehg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ib3a12fb8160729008bdaa8026365675a11325da0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5448 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02superio/fintek/f71859: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I3577ca3f761fb699dc51141a02e1f853bf1f1a21 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5417 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02superio/fintek/f71889: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Id8a1a2e8c87add636af1506598c2669d72dc3238 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5437 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02superio/fintek/f71872: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia021229154dc90b830a314f3adc2a0dd444bd68d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5436 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02superio/fintek/f71863fg: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: I863c16634873224c17e43100271e9b91419724d0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5435 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02superio/fintek/f71805f: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5434 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-31superio/fintek/f81865f: Avoid .c includesEdward O'Callaghan
We should not be #include .c files, instead link early_serial into romstage and provide a prototype. Change-Id: Ia9277169ce1592e1fc72f8849f0982741daec567 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5416 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-13superio/fintek: Document Fintek F71869AD code.Edward O'Callaghan
Change-Id: I156077bf5571764d0e4bc044be80c8ab94556de4 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5178 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-13Eliminate some ASL warningsOskar Enoksson
The ASL compiler warned about "Control Method should be made Serialized (due to creation of named objects within)". This commit eliminates the warnings by changing those NonSerialized into Serialized. Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5189 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-12winbond/w83627hf/acpi: Fix some ASL warningsOskar Enoksson
There were ASL compiler warnings about "Size mismatch". This commit eliminates the warnings by changing the ASL declarations of those fields. Change-Id: If851ed4892ef6c96acbff861abd7001ab67d9d66 Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5190 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-06uart8250: Drop includes in superioKyösti Mälkki
Change-Id: If723896cc31da75dbb3a63d5dc959764e96fded1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-27superio/fintek: Add initial support for Fintek F71869AD.Edward O'Callaghan
Change-Id: I41f1ee20517dd179a4dee914ab7f6332739e326e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/4784 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-03superio: Uncomment the w83627uhg UART clock source initializationDave Frodin
The asrock/imb-a180 mainboard is the first mainboard to use this w83627uhg/nct6627UD sio. The default h/w clock setting is 0. Adding the SIO in the mainboard Kconfig made the builder complain that the set_uart_clock_source() wasn't being used. So the calls to that function were uncommented. Change-Id: Iedba035237c5c0fa230b02ff4799bb8c1b7bbd4a Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/4573 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-11-10sio1007: Properly build '.c' filesMarc Jones
Properly build the super i/o .c files. This prevents including the .c file directly in romstage, which is generally bad practice. Adding a Makefile and a .h file to include. Change-Id: I0be66e94d3062a2c4a445cee2f12ec249598dc8b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4014 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-08-15w83627hf/acpi: Move floppy drive enumeration from _INI into _FDE.Christoph Grenz
Move the floppy drive enumeration from _INI() and PROB(), which stored the enumeration results into _FDE into _FDE(). _INI is called by any ACPI-capable OS on boot while _FDE is rarely used. So it's better to run the enumeration when requested rather than unconditionally. Change-Id: Icf1e2a551806592faa8ba8d80fa8d02681602007 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3604 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15w83627hf/acpi: Make `AddressMax` a multiple of `AddressAlignment`Christoph Grenz
The parallel port of the W83627HF can be configured on any port between 0x100 and 0xFFC with 4 byte alignment for traditional modes and 8 byte alignment for EPP mode. As the ACPI specification says that the maximum acceptable starting address has to be a multiple of the alignment granularity, correct the maximum starting address from 0xFFC to 0xFF8. Change-Id: I272e09d091149791f2867b1d06e4fc27bc1bb2cd Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/2942 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15w83627hf/acpi: Fix logical device power down in ACPIChristoph Grenz
As Nico noticed for the W83627DHG, the power management bits to power down individual logical devices on Winbond superios are named counterintuitively and need to be set when the logical device should be powered. This corrects the power management methods for the W83627HF. Change-Id: I98bccd550a0513c62bfa9480275f88c566691bc8 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3605 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-20it8728f: Add ITE IT8728F superio early serial support.Damien Zammit
This is the first of a series of patches to provide support for a new mainboard, Gigabyte GA-B75M-D3V. This patch provides early serial for the superio and has been tested on this mainboard. The code is based on IT8718F superio. Change-Id: I5636199b49314166ed3b81e60b41131964dd44ff Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/3794 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-07-10w83627hf/acpi: Fix endianess error in floppy drive enumeration codeChristoph Grenz
The enumeration results are stored as five DWORDs in one 20 byte buffer. Bytes 3, 7, 11 and 15 were used to set the lowest bit of each DWORD. ACPI uses little endian, so 1, 4, 8 and 12 are the correct indices. Change-Id: I793225cb1bb62fd148ecfa1e61e02f5d7be62cdb Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3602 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04w83627hf/acpi: Fix offset of logical device activationNico Huber
The PnP's logical device activation normally resides at 0x30. This might have been overlooked as 0x29 looks very close to 0x30 in human eyes. Change-Id: Id5d5a92f2683ebe1808b943f686c062151d216da Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3592 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-04w83627hf/acpi: Fix type error in floppy drive enumeration codeChristoph Grenz
The enumeration method tried to evaluate an one-byte OperationRegion instead of a field in this OperationRegion, which resulted in an AE_TYPE error at runtime. Indexing the OperationRegion with a single field fixes this error. Change-Id: I15dd7aa6ecafb3a215d165d2b721003446815025 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3603 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03winbond/w83627dhg: Fix logical device power down in ACPINico Huber
The W83627DHG has some power managements bits to power down individual logical devices. These are called `* Power Down`. Counterintuitively and in contrast to `Immediate Power Down` (bit to power down the whole chip), these bits are set when the respective logical device is powered. Unfortunately, our ACPI code set them wrong which led to disabled devices after a S3 suspend/resume. Adding an option how to set the PM bits and setting them to zero for the W83627DHG, corrects it. Tested with kontron/ktqm77. Change-Id: I8a472d480d4277721bd17c9f7c2ce44fa84e8ae2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3590 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03pnp: Add some default functions to enter/exit config stateNico Huber
Implement some common default functions to enter and exit the configuration state. Also provide default pnp_mode_ops for common enter()/exit() function pairs. The following cocci ensures their use: @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; @ enter_match_8787 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } @ depends on enter_match_8787 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_8787, }; @ enter_match_55 @ identifier mode_match.enter, dev; @@ enter(...) { outb(0x55, dev->path.pnp.port); } @ depends on enter_match_55 @ identifier mode_match.enter, mode_match.ops; @@ struct pnp_mode_ops ops = { - .enter_conf_mode = enter, + .enter_conf_mode = pnp_enter_conf_mode_55, }; @ depends on enter_match_8787 || enter_match_55 @ identifier mode_match.enter; @@ -enter(...) {...} @ exit_match_aa @ identifier mode_match.exit, dev; @@ exit(...) { outb(0xaa, dev->path.pnp.port); } @ depends on exit_match_aa @ identifier mode_match.exit, mode_match.ops; @@ struct pnp_mode_ops ops = { - .exit_conf_mode = exit, + .exit_conf_mode = pnp_exit_conf_mode_aa, }; @ depends on exit_match_aa @ identifier mode_match.exit; @@ -exit(...) {...} @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @ @@ #include <device/pnp.h> +#include <superio/conf_mode.h> @ mode_match_55_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_55, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_55_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_55_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_55_aa, }; @ mode_match_8787_aa @ identifier ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, }; @@ identifier mode_match_8787_aa.ops; @@ -struct pnp_mode_ops ops = {...}; @@ identifier mode_match_8787_aa.ops, devops; @@ struct device_operations devops = { - .ops_pnp_mode = &ops, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3484 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-01w83627hf: Add comments about parallel port modes in superio.aslChristoph Grenz
Add comments in PAR0._PRS explaining which dependent resource descriptor puts the parallel port into EPP or SPP mode. Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/3495 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-18winbond/w83627dhg: Correct resource setting for SPI (LDN6)Nico Huber
The SPI logical device on the W83627DHG uses the second i/o port register pair but not the first one. So we have to also set `io1` (the second io_info struct) and not `io0` in the pnp_info structure. Setting the PNP_IO1 flag without a mask in `io1` caused coreboot to hang in pnp_enable_devices() until commit aeead274 which added a check for an unset mask. Change-Id: I027d279b4641fecd88afb14d40fbe1c0bfbf81bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3391 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-17pnp: Remove now plain wrappers for default PnP functionsNico Huber
After removing the enter()/exit() functions for configuration mode, most wrappers for our standard PnP functions just call the underlying default implementation. Remove those with a little cocci: @ op_match @ identifier op; identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; type device_t; identifier dev; @@ static void op(device_t dev) { pnp_op(dev); } @@ identifier op_match.op; @@ -op(...) {...} /* Three rules to match the alignment, hmmp... */ @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .set_resources = op, + .set_resources = pnp_op, }; @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .enable_resources = op, + .enable_resources = pnp_op, }; @@ identifier op_match.op, op_match.pnp_op; identifier ops; @@ struct device_operations ops = { - .enable = op, + .enable = pnp_op, }; Change-Id: Idc0e52c7e3600a01f3b6a4e17763557b271b481e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3483 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17pnp: Register implementations of enter/exit config stateNico Huber
Find all the (ramstage) implementations of enter()/exit() functions for the configuration state, register and call them through the new struct pnp_mode_ops. As our standard PnP functions are aware of the pnp_mode_ops, it's not necessary to call enter()/exit() around them anymore. Patch generated with the cocci below. It's not perfect. The movement of the enter()/exit() calls is somehow fragile. So I checked the remaining calls for sense, and changed some empty lines. Also a duplicate insertion of pnp_conf_mode_ops had to be removed. /* Try to find enter and exit functions by their outb() structure and their usage around calls to our standard pnp functions: */ @ enter_match @ identifier enter; identifier dev; type device_t; @@ void enter(device_t dev) { <... outb(..., dev->path.pnp.port); ...> } @ exit_match @ identifier exit; identifier dev; type device_t; @@ void exit(device_t dev) { <... outb(..., dev->path.pnp.port); ...> } @ pnp_match @ identifier op; identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; identifier enter_match.enter, exit_match.exit; type device_t; identifier dev; @@ void op(device_t dev) { ... enter(dev); ... pnp_op(dev); ... exit(dev); ... } /* Now add enter/exit to a pnp_mode_ops structure: */ @ depends on pnp_match @ identifier enter_match.enter; identifier exit_match.exit; identifier ops; @@ +static const struct pnp_mode_ops pnp_conf_mode_ops = { + .enter_conf_mode = enter, + .exit_conf_mode = exit, +}; + struct device_operations ops = { ..., + .ops_pnp_mode = &pnp_conf_mode_ops, }; /* Match against the new structure as we change the code and the above matches might not work anymore: */ @ mode_match @ identifier enter, exit, ops; @@ struct pnp_mode_ops ops = { .enter_conf_mode = enter, .exit_conf_mode = exit, }; /* Replace enter()/enter() calls with new standard calls (e.g. pnp_enter_conf_mode()): */ @@ identifier mode_match.enter; expression e; @@ -enter(e) +pnp_enter_conf_mode(e) @@ identifier mode_match.exit; expression e; @@ -exit(e) +pnp_exit_conf_mode(e) /* If there are calls to standard PnP functions, (re)move the enter()/exit() calls around them: */ @@ identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; expression e; @@ -pnp_enter_conf_mode(e); pnp_op(e); +pnp_enter_conf_mode(e); ... pnp_exit_conf_mode(e); @@ identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$"; expression e; @@ pnp_enter_conf_mode(e); ... +pnp_exit_conf_mode(e); pnp_op(e); -pnp_exit_conf_mode(e); @@ expression e; @@ -pnp_enter_conf_mode(e); -pnp_exit_conf_mode(e); Change-Id: I5c04b0c6a8f01a30bc25fe195797c02e75b6c276 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3482 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17pnp: Provide alternative pnp_enable() implementationNico Huber
The current default implementation of pnp_enable() only disables devices - if set so in the devicetree - but does not enable them. Enablement takes place in pnp_enable_resources(). Yet, many PnP chips implement their own version of pnp_enable() which also enables devices if set in the devicetree. It's arguable, if enabling those devices makes sense, before they get resources assigned. Maybe we can't write the resource registers if not, who knows? The least we can do is providing a common implementation for this behavior, and get rid of some code duplication. Used the following cocci: @@ expression e; @@ +pnp_alt_enable(e); -pnp_set_logical_device(e); ( -pnp_set_enable(e, !!e->enabled); | -(e->enabled) ? pnp_set_enable(e, 1) : pnp_set_enable(e, 0); | -if (e->enabled) { pnp_set_enable(e, 1); } -else { pnp_set_enable(e, 0); } ) Change-Id: I8d695e8fcd3cf8b847b1aa99326b51a554700bc4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3480 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17pnp: Unify some alignment to ease autogenerating patchesNico Huber
Most PnP drivers align the initialization of their `device_operations` with spaces. Unify this, so next autogenerated patches always match the alignment. Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/3479 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-11winbond/w83627dhg: Add ACPI supportNico Huber
This is loosely based on Christoph Grenz' ACPI code for the W83627HF and makes use of the PnP super i/o ACPI framework. Change-Id: I5e1cd09b83c0041f440562d2a1b73e4560589cb7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3288 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11Start ACPI framework for PnP (super i/o) devicesNico Huber
I'm trying to make writing ACPI code for super i/o devices more comfortable. pnp.asl hosts some general cpp macros. The other four files are to be included in dsdt trees. They are controlled by cpp macros which should be defined/undefined before inclusion. Work was inspired by Christoph Grenz' ACPI code for the W83627HF. Change-Id: Idb55332ba9bc788c98964d30a450e0d734cf28ec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3286 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-10Drop prototype guarding for romccStefan Reinauer
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-12Add new superio deviceSteven Sherk
- Added in new support for Nuvoton NCT5104D LPC device. Change-Id: I0af8c5e3e46fdd0a549475b30917897ae9e144a7 Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/3072 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01Winbond W83627HF: Rename and move ASL snippet to `acpi/superio.asl`Paul Menzel
Put the ASL snippet for inclusion in the DSDT under the `acpi/` folder as it is done for the other Super I/O devices. $ find src/superio/ -name *asl src/superio/ite/it8772f/acpi/superio.asl src/superio/smsc/mec1308/acpi/superio.asl src/superio/smsc/sio1007/acpi/superio.asl src/superio/winbond/w83627hf/devtree.asl As there are no users of this file yet, no other adaptations need to be made. Change-Id: Id10cd8897592b780c9fd3bd6b45ada4cf1fcf33e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2937 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22x86: Unify arch/io.h and arch/romcc_io.hStefan Reinauer
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-15Super I/O W83627DHG: Enable UART B by redirecting pinsWolfgang Kamp
Pins 78-85 are set to GPIO after power on or reset. To enable UART B the pins must be redirected to it. Look at W83627DHG databook version 1.4 page 185 Chip (global) Control Register CR2C. Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845 Signed-off-by: Wolfgang Kamp <wmkamp@datakamp.de> Reviewed-on: http://review.coreboot.org/2626 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-03-06AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperioJens Rottmann
The power up default for the 14M_25M_48M_OSC switchable clock output ball of the SB800 chipset is 14 MHz. sb800/bootblock.c changes this to 48 MHz, which is the correct value for almost all SIOs. However, not for 'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not configurable for other clock speeds. A wrong SIO clock supply results in funny RS232 output (wrong bit speed) and non-working PS/2. We could switch back to 14 MHz in the mainboard's romstage.c, but then the clock frequency would change twice. The resulting short 48 MHz burst causes a handful of rubbish characters on RS232 on every boot until the SIO clock has stabilized again. This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz. This does not affect any boards currently in the repository (yet). Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4 Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2454 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1928 Tested-by: build bot (Jenkins)
2012-11-06smsc/lpc47n227: Make early_serial usablePatrick Georgi
This is the smallest possible change to make early_serial.c compile when included from romstage.c. early_serial could be reworked to be built as separate unit (romstage-y), but that should be done for all SuperIOs, not some individual outlier. Change-Id: I90ee66b43c9677b86b1b5d6fcc8febfbe58d80dd Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1686 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-07Remove chip.h files without config structureKyösti Mälkki
Also deletes files not included in build: src/southbridge/amd/cimx/sb700/chip_name.c src/southbridge/amd/cimx/sb800/chip_name.c src/southbridge/amd/cimx/sb900/chip_name.c Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1473 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 20:17:00 +0000