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2019-01-06superio/*: Link early initialization into bootblockArthur Heymans
This allows to set up the SuperIO in the C_ENVIRONMENT_BOOTBLOCK bootblocks. It is likely unnecessary to do this in verstage. This also renames COMMON_ROMSTAGE to COMMON_PRE_RAM. Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-28superio/smsc/sch5147/acpi/superio.asl: Remove unneeded white spacesElyes HAOUAS
Change-Id: I8a5d937bfc1e0ff61736c19a24b03c1a8defc427 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-19smsc/sch5147: Implement ACPI handling of a few LDNArthur Heymans
Change-Id: Ide30a7396b6248e2037041e177dc8514533718a4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-19superio/smsc: Add SCH5147Arthur Heymans
There are no public datasheets for this SuperIO. The results are from probing the registers manually. Change-Id: Ie5659533c5f224603f918d17942a7057e6701222 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-18{drivers,superio}: Remove unneeded include <pc80/mc146818rtc.h>Elyes HAOUAS
Change-Id: Ia42c1f8559667e7711fac919df8bfbee8455e3cc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-16superio/ite/it8772f: Fix typoElyes HAOUAS
Change-Id: I4fd7bc6a21909a7facd16799c0ef9296ed65a7b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-16superio/ite/it8721f/acpi: Remove unneeded white spaceElyes HAOUAS
Change-Id: Ie605ab8ff13332359aa44fff12acbadd23dcdf74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-11-19src: Add required space after "switch"Elyes HAOUAS
Change-Id: I85cf93e30606bc7838852bd300a369e79370629a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-16src: Remove unneeded include <pc80/keyboard.h>Elyes HAOUAS
Change-Id: I0dcdfb1fa782c7936a19de11adcf17387f49d9db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-08-21superio/ite/it8721f: Add SuperIO ACPI declarationsArthur Heymans
Change-Id: I074d57fa5b140b6946ae81beb210fefac48a66eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21superio/ite/it8721f: Add resourcesArthur Heymans
There is no public datasheet available for this SuperIO so the resources are guessed by looking at other ITE SuperIO's and the register dumps while running vendor firmware. The only board with this SuperIO in the tree is the asus m5a88-v. Most of the devicetree entries would have been invalid here so one should not worry too much about regressions. Tested with Foxconn d41s. Change-Id: I6715c68b3aa9aebf6e292975cbf64ce905b30e8b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-17superio/ite/it8720f: fix power control initFelix Held
The existing code for modifying the power state after power loss of the system only implemented the transitions from power off to either power on or power keep properly. Since I don't have a board with this chip, I couldn't test the patch on real hardware. The two cases described above were tested before the original patch was merged, so I'd expect this to work. Change-Id: I3c26a2837e451dbfd3cee82e9beedc0f4a90af03 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-13superio/winbond/w83627hf: Remove unused valueElyes HAOUAS
Change-Id: I90d1997254f6766f4c61ff55449109adbdd783e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-09src/superio: Fix typo and remove unneeded whitespaceElyes HAOUAS
Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09superio: fix and extend pnp_info of wpcd376iStefan Tauner
The implementation of wpcd376i in coreboot is based on the superiotool output which apparently was incorrect. This patch refines the implementation to match the datasheet. Change-Id: I0108e912dc4f603276074f0999c6d3146c3b13f9 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/27857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-03superio/nuvoton/nct6776/acpi: Add PS/2 mouse supportTristan Corrick
By defining SUPERIO_KBC_PS2M, ACPI code is added to show the PS/2 mouse. This has been tested on an ASUS P8H61-M LX with Linux 4.9.110 and 4.17.8. In each case, the PS/2 mouse works automatically, whereas it was not detected before. Change-Id: I7983f85b3fd23547950f1f75a81bbca63c63d52b Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03superio/acpi: Make _CRS methods Serialized, eliminating IASL remarksTristan Corrick
When compiling for the ASUS P8H61-M LX, IASL 20180531 emits the following remark: "Control Method should be made Serialized (due to creation of named objects within)". Making the appropriate methods Serialized eliminates these remarks. Change-Id: I8e95d9a00a629a2f904c79b78fac20810327ed37 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27796 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03superio/nuvoton/nct6776/acpi: Add parallel port supportTristan Corrick
Exposing the parallel port via ACPI causes Linux to automatically detect the parallel port and load the appropriate modules. Tested on an ASUS P8H61-M LX with Linux 4.9.110 and 4.17.8. However, no parallel port device has been tested. Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-08-03superio/nuvoton/nct6776/acpi: Fix typo in commentsTristan Corrick
The constant used in the ACPI code is NCT6776_SHOW_KBC, so update the comments to reflect that. Change-Id: I9ba69384866088f84a516557d76864104a024968 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/27794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-26sio/smsc/fdc37n972: add missing pnp_conf_mode field to ops structFelix Held
This patch makes it possible to enter the config mode of the super IO chip, so that changes can be made to the configuration registers. Change-Id: I7e31eaf217b3af2226c1e7d2f14f2ef7b0d7ddbe Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2018-07-25superio/winbond: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I4311834f3970bd3471f2f5a73ca7da3c03936d37 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-25superio/via: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I14dbeda9832a25116cf53c36197615e9d02d5134 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-25superio/renesas: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I42469c844074db57071d0191d12d8fd64f462672 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-25superio/intel: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I5bd525532c01b3b9f7ddbc8eab42caa8b7f30795 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-25superio/fintek: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: Ic6387032e043b6ad9e9ceefd2fcc1cdf843e2989 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-24superio/nuvoton/npcd378: Add ACPI code for S3 resumePatrick Rudolph
Configure SuperIO on shutdown to keep devices enabled, set green LED to fading on sleep and normal on wake. Add SSDT to write LDN4 IOBASE addresses stored in devicetree.cb. Tested on HP8200: * Wakes from power button or USB keyboard. * LED is fading Change-Id: I2035249a39616aa2d87bd93f9e49c70d231546cc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-22superio/nuvoton/npcd378: Fix resource sizePatrick Rudolph
Based on vendor ACPI code. Change-Id: I4d6785efb9d18953042775e7164710ef3c041ed5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-18superio/nsc: pass the chip-specific ops struct to pnp_enable_devicesFelix Held
Pass the address of the chip-specific ops struct instead of the one of the generic pnp_ops struct to the PNP device enable function. This allows the removal of the LDN-specific ops overrides which is also done in this patch. Change-Id: I0c820254e97e3f80470d148552af06940e147b74 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/23008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-18superio/smsc: pass the chip-specific ops struct to pnp_enable_devicesFelix Held
Pass the address of the chip-specific ops struct instead of the one of the generic pnp_ops struct to the PNP device enable function. This allows the removal of the LDN-specific ops overrides which is also done in this patch. Change-Id: I16e485494e448ae02e0a7b9e21b90ddbb1a53a4b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/23007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-18superio/ite: pass the chip-specific ops struct to pnp_enable_devicesFelix Held
Pass the address of the chip-specific ops struct instead of the one of the generic pnp_ops struct to the PNP device enable function. This allows the removal of the LDN-specific ops overrides which is also done in this patch. Change-Id: I5f03a4064778c419f4b9c50e70db1296addf6c9e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/23006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-18superio/nuvoton: remove LDN-specific ops overridesFelix Held
The pnp ops struct is already passed to the pnp_enable_devices function and it is used if no override is supplied in the elements of the pnp_info struct array Change-Id: I18345d7cc50a7d46cb15584dfb54df28e8534f81 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-06superio: move files to match the common naming schemeFelix Held
Change-Id: I1a8fc34aaaf42514c8af97ab155ff2712e7a5448 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/23009 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04src/superio/{ite,smsc}: Remove space before tabElyes HAOUAS
Change-Id: I2829e4cb1445f8412f57da10fda6b92c92e56ea0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-01superio/nuvoton/npcd378: Add PSU fan controlPatrick Rudolph
Implement method to access the SuperIO's harware monitor (HWM) IO space. Set the PSU fan using a new CMOS option psu_fan_lvl. Add the CMOS option to all board that use NPCD378. In case no CMOS is set use the default fan level 3. The HWM space can be written to at any time, but the SuperIO has to be notified that a write is ongoing. After clearing the write-lock bit all changes are applied at once. Tested on HP Compaq 8200 SFF. Change-Id: I56ce7ad1df88638589a577b8a09d5d775557887b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26050 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15superio/ite/it8720f: Implement power controlSamuel Holland
Program the Super I/O to turn the machine on or restore its power state when AC power is restored. Based on code from src/superio/nuvoton/nct5572d/superio.c. Change-Id: I1f3432f43b0784c3696bf1d7233b83d3a203af20 Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/25463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-14superio/nuvoton: Add support for NPCD378Patrick Rudolph
The NPCD378 can be found on at least: * HP Compaq 8200 * HP Compaq 8300 The datasheet is not publicly available, as HP implements lots of custom hardware. Add basic support for it, based on HP Compaq 8200. The first eight LDNs seem to be standard nuvoton compatible, except for LDN4, which is used to control front LED and power in ACPI S3. LDN8 provides access to HP's proprietary HWM which is accessiable at the LDN's IOBASE with a size of 0x100 bytes. The HWM consists of 16 pages with each holding 0xff bytes. The pages can be selected by writing the page index to IOBASE + 0xff. TODO: Reverse engineer the HWM to support fan control. WARNING: The remaining LDNs have been guessed and might be wrong! The serial has been tested and is working. Change-Id: Ib497fd41b88e9c159eeeffa69bc2bfdccee9cb38 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25384 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-12superio/ite/it8623e: initialize the PWM fan controllerKevin Cody-Little
Copies the common/env_ctrl support code from the it8728f driver. Tested on an ASUS AM1I-A using Linux 4.16.7-gentoo as payload, and booting userspace without a kexec call. Prior to this change, an error was given during boot: it87 it87.656: Detected broken BIOS defaults, disabling PWM interface After this change, the message is gone, and PWM fan control works through the /sys/class/hwmon interface. Change-Id: Id97c4ec19562e7c78308c5afe6ff7c938922c9e7 Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26224 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04superio/ite/common: Add options to enable beepsVagiz Trakhanov
Add device tree options to enable beeps when exceeding temperature, voltage, and fan limits. As of this commit, setting voltage and fan limits is not implemented. Change-Id: I57ce622ee4498b75f00e678c2e6d72e499925bce Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/22141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-15Intel i3100 boards & chips: Remove - using LATE_CBMEM_INITMartin Roth
All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: northbridge/intel/i3100 southbridge/intel/i3100 superio/intel/i3100 cpu/intel/socket_mPGA479M Mainboards: mainboard/intel/truxton mainboard/intel/mtarvon mainboard/intel/truxton Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/22031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-07superio/ite/it8623e: add support for SIO chip ITE IT8623EGergely Kiss
This change adds basic support for the SuperIO chip ITE IT8623E. Due to the lack of a datasheet, defaults are shown as "not available (NA)" in superiotool's register dump. LDNs defined in it8623e.h are definitely correct and working as expected. Change-Id: I05832c4db7ab59541337f11200640316376e792e Signed-off-by: Gergely Kiss <mail.gery@gmail.com> Reviewed-on: https://review.coreboot.org/23001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07superio/f71869ad: Add temperature sensor typeRenze Nicolai
This patch makes it possible to set the "Temperature Sensor Type Register" at index 6Bh from the devicetree, allowing the use of thermistors instead of BJT type sensors. Register documentation (from page 60 of the F71869 datasheet): 6.6.25 Temperature Sensor Type Register - Index 6Bh Bit 7-4: reserved Bit 3: T3_MODE (0: thermistor, 1: BJT [default]) Bit 2: T2_MODE (0: thermistor, 1: BJT [default]) Bit 1: T1_MODE (0: thermistor, 1: BJT [default]) Bit 0: reserved Change-Id: I6af0d93061ec49aec7a9181cdf7affd60fbdca73 Signed-off-by: Renze Nicolai <renze@rnplus.nl> Reviewed-on: https://review.coreboot.org/22935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-07nuvoton/nct6776: Add ACPI declarationsTobias Diedrich
Add ACPI declarations to be incorporated into ACPI tables for mainboards with this super I/O. Tested on Intel NUC DCP847SKE, Linux 4.13.14. Change-Id: Idb76b2e99e90a213e2695efc1afd4fa9069c134f Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/22808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-01-06superio/ite: add missing pnp_conf_mode fields in ops structFelix Held
This fixes the bug that the LDNs on the affected SIO chips didn't get configured, since the config mode wasn't entered. Change-Id: Ic468847571e164e4e1280428f08fc067b724464e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/23004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-12-02winbond/w83977tf: Add ACPI declarationsKeith Hui
Add ACPI declarations to be incorporated into ACPI tables for mainboards with this super I/O. Change-Id: If113807901619bc0f4250607546be415f9e5e45b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-11-30nuvoton/nct5572d: Disable mouse controller also during resumePaul Menzel
Currently, having a keyboard connected to the PS/2 controller of the ASRock E350M1, after suspending and resuming the system, the keyboard does not work anymore. A similar problem is documented in commit 448e3863 (drivers/pc80: Add PS/2 mouse presence detect) [1]. There is no reason to not disable the controller during resume. Also, that way, the PS2 ASL method does not need to be overriden. [1] https://review.coreboot.org/13165 TEST=Resume system, and notice PS/2 keyboard works. Change-Id: I51dc446861120f80bc9ffc4cc54b86e317d99689 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-11-30superio: Log if mouse controller is disabledPaul Menzel
It’s useful to know, if the mouse controller is disabled or not, so convert the comment to a log message. Change-Id: Ic3f7d5b7b98cf8c258a6a601f4a44ce403f4a576 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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