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Some coreboot project code with my work
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Age
Commit message (
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Author
2019-05-25
AGESA: Move heap_status_name() implementation
Kyösti Mälkki
2019-03-08
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
Julius Werner
2019-01-17
vendorcode/{amd,cavium,intel}: Remove trailing whitespace
Peter Lemenkov
2018-01-23
AGESA_LEGACY: Apply final cleanup and file removals
Kyösti Mälkki
2017-10-05
AGESA vendorcode: Add ENABLE_MRC_CACHE option
Kyösti Mälkki
2017-09-13
AGESA vendorcode: Remove AGESA_ENTRY_INIT_RECOVERY
Kyösti Mälkki
2017-08-30
AGESA vendorcode: Remove AMD_INIT_RECOVERY
Kyösti Mälkki
2017-08-02
AGESA: Move romstage-ramstage splitline
Kyösti Mälkki
2017-08-02
AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpart
Kyösti Mälkki
2017-06-27
vendorcode/amd: Unify Porting.h across all targets
Stefan Reinauer
2017-06-26
vendorcode/amd: Drop multiple copies of gcc-intrin.h
Stefan Reinauer
2016-06-04
AGESA boards: Split dispatcher to romstage and ramstage
Kyösti Mälkki
2016-05-18
AGESA vendorcode: Build a common amdlib
Kyösti Mälkki
2015-10-30
cpu/amd: Fix cbtypes.h to match UINTN convention
Stefan Reinauer
2015-09-22
coreboot: introduce commonlib
Aaron Durbin
2014-12-06
vendorcode/amd/agesa: Make Porting.h common between families
Edward O'Callaghan