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Some coreboot project code with my work
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Author
2020-03-04
vc/amd/agesa: Delete mfParallelTraining.c
Joe Moore
2020-01-13
vc/amd/agesa: Fix out of bounds read
Joe Moore
2019-10-22
vc/amd/agesa/f16kb: Cast to UINT64 to avoid overflow
Joe Moore
2019-10-22
vc/amd/agesa/f16kb: Remove redundant value assignment
Joe Moore
2019-07-19
src: Make implicit fall throughs explicit
Jacob Garber
2019-05-06
Fix code that would trip -Wtype-limits
Julius Werner
2019-03-08
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
Julius Werner
2018-12-18
Fix typos involving "the the"
Jonathan Neuschäfer
2017-08-31
AGESA f16kb vendorcode: Split to Makefile.inc files
Kyösti Mälkki
2017-08-04
AGESA f15 f15tn f16kb: Add extra checks for incorrect SPD data
Konstantin Aladyshev
2017-08-02
AGESA: Correct PCI function number for MEM_GET(SET)REG outputs
Konstantin Aladyshev
2016-07-01
AGESA boards: Fix split to romstage and ramstage
Kyösti Mälkki
2016-06-04
AGESA: Drop unused assembly files
Kyösti Mälkki
2016-04-20
AGESA vendorcode: Suppress maybe-uninitialized warnings
Kyösti Mälkki
2016-04-16
vendorcode/amd/agesa: Fix tautological compare
Edward O'Callaghan
2016-01-07
src/vendorcode/amd: correct spelling of MTRR
Paul Menzel
2015-04-10
vendorcode/amd/agesa/f16kb: Enable support for AM1 socket
Sergej Ivanov
2014-12-07
vendorcode/amd/agesa/f1{5,5tn,6kb}: Silence empty loop warn
Edward O'Callaghan
2014-07-18
vendorcode/amd/agesa: Use macros already defined in stdlib.h
Edward O'Callaghan
2013-10-15
vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7
WANG Siyuan
2013-08-04
AMD Kabini: Add AGESA/PI code for new processor family
Siyuan Wang