coreboot - Some coreboot project code with my work

Age	Commit message (Collapse)	Author
2020-08-19	vc/amd/fsp/picasso: update pci descriptor comments	Matt Papageorge
	Update fsp_dxio_descriptor comments to be more comprehensive of the currently available data fields. Most of these are not currently utilized with Zork but may be in future projects. BUG=b:161218965 TEST=Build test Trembyle Change-Id: I8eb79fa7807dcf5b28b7b0ec60953ef857d51972 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44554 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-02	vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments	Felix Held
	Also document the maximum nuber of lanes for the different platforms. Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44069 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31	vc/amd/fsp/picasso: document DXIO lane number mapping	Felix Held
	Haven't found the official documentation for the DXIO lane mapping on Pollock, so I had to guess that from the working configurations used in google/dalboz and amd/cereme. Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44063 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23	amd/picasso: rename PCIe descriptor to DXIO descriptor	Felix Held
	Most of the DXIO descriptors are used to configure PCIe engines and lanes, but on Picasso system some of the DXIO lanes can also be configured as SATA or XGBE ports. Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23	vc/amd/fsp/picasso: add logical to lane number in port descriptor struct	Felix Held
	The lane numbers in the PCIe/DXIO descriptor are the logical and not the physical ones, so add logical to the corresponding field names of the fsp_pcie_descriptor struct. Change-Id: I7037fed225119218e87593932815aff815e83ff8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-09	vc/amd/fsp/picasso: add comment on logical lane numbers in descriptor	Felix Held
	The expected lane numbers in the fsp_pcie_descriptor struct are the logical and not the physical ones. Change-Id: I14166bbd397a9e5f5c5370717e039b9e71cbdb07 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43311 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19	vc/amd/fsp/picasso: Use fixed width fields for platform descriptors	Matt Papageorge
	PCIe platform descriptors passed to Picasso FSP should use fixed width fields. BUG=b:153681134 TEST=Boot system and suspend/resume. All PCIe devices train succesfully. Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Change-Id: If2a34be895db2c19c8830f5888cb99e43ad21b73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42519 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-11	vc/amd/fsp/platform_descriptors: drop prefix from PCIe/DDI structs	Felix Held
	The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor structs isn't needed, since this code is picasso-specific, so drop it. Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21	vc/amd/fsp/picasso: Rename the fsp_ddi and fsp_pcie descriptors	Raul E Rangel
	This change was missed when I ported over fsp_params.c. BUG=b:157140753 TEST=Boot trembyle to OS Fixes: 89e51e61781 ("soc/amd/picasso: Allow mainboard to provide pci ddi descriptors") Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icdb6aebe5a3be7174170bdf37a1f379f02dcc5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
	Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " \|egrep ":( /\.\/\$\|#\|;#\|-- \| \ )" \| cut -d: -f1 \|grep -v crossgcc \|grep -v gcov \| grep -v /elf.h \|grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. /") -# This file is part of a set of unofficial pre-commit hooks available -/ This file is part of coreboot / -# This file is part of msrtool. -/ This file is part of msrtool. / - This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. / - This file is part of the coreboot project. - /* This file is part of the coreboot project. / -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/ This file is part of the coreboot project / -/ This file is part of the coreboot project. / -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. / -/ This file is part of the ectool project. / - This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. / -## This file is part of the superiotool project. -/ This file is part of the superiotool project / -/ This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-27	vc/amd/fsp/picasso: Add PCIe and DDI helpers	Marshall Dawson
	Add a file for generating PCIe and DDI descriptors that will be understandable to the FSP. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa4d81a0f2909cb66e551e34e1f3fa4725560d60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>