summaryrefslogtreecommitdiff
path: root/src/vendorcode/amd/pi
AgeCommit message (Collapse)Author
2020-01-05vc/amd/pi/00670F00: Fix typo in phony target declarationMarshall Dawson
Correct a copy/paste error for warn_no_agesa. Change-Id: Ife2cca47f1f816f99395b33976d08826c53e3c3e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-24vendorcode/amd/pi/Kconfig: Add prompt to pre/post pi filesRaul E Rangel
This allows the values to be set in a .config BUG=none TEST=Was able to set the value from a .config and built careena firmware Change-Id: I757e4b9a0b80ff42c1f49143a44f15550366fd0b Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37879 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-12vc/amd/pi: Fix typoPatrick Georgi
Change-Id: Ic3d1b9f90c6ed3d85ff209f433de9ab939d760a6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37676 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11soc/amd/stoneyridge|mbs: Deprecate SOC_AMD_NAME_PKG and othersMarshall Dawson
Add package and APU selections to mainboards and remove symbols no longer used in soc//stoneyridge. Change-Id: I60214b6557bef50358f9ec8f9fcdb7265e04663b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11soc/amd/stoneyridge|mbs: Define SOC_AMD_STONEYRIDGE symbolMarshall Dawson
Make a new Kconfig symbol for using soc//stoneyridge. This code also supports Prairie Falcon is backward-compatible with Carrizo and Merlin Falcon. Although Bettong uses Carrizo, it does not currently rely on stoneyridge source, so it is unaffected by this change. Change-Id: I786ca54b0444cbcf36dc428a193006797b01fc09 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11soc/amd/stoneyridge|mb: Add Kconfig symbol for Prairie FalconMarshall Dawson
The stoneyridge code inferred that if Merlin Falcon was built but no Merlin Falcon binaries were present, the intent must be Prairie Falcon. The two falcons are Embedded variants, and Prairie Falcon falls within Family 15h Models 70h-7Fh. Add a Prairie Falcon symbol that can be used explicitely. Drop HAVE_MERLINFALCON_BINARIES. Change-Id: I0d3a1bc302760c18c8fe3d57c955e2bb3bd8153a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11soc/amd/stoneyridge|vc: Change default locations for blobsMarshall Dawson
Set the default location strings to point to the 3rdparty/amd_blobs files. Change-Id: I5426b8de2501ba55843efc1cda4b03bc3768f8cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11vc/amd/pi: Allow 00670F00 to build with no binaryPIMarshall Dawson
Make the default binaryPI image strings for all stoneyridge-based APUs depend on USE_AMD_BLOBS. Ensure the build completes without names, and without images. Change-Id: I74a38efa2a4ad2f9f12a1f8e7fb8694d0ab9dd1e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-04binaryPI: Fix failing AP startupKyösti Mälkki
Fix regression with commit 5639736 binaryPI: Drop CAR teardown without POSTCAR_STAGE Occassionally (maybe 1 boot in 10) SMP lapic_cpu_init() fails with following errors in the logs of pcengines/apu2: CPU 0x03 would not start! CPU 0x03 did not initialize! The CPU number is sometimes 0x02, never seen 0x01. Work-around also suggests something to do with cache coherency and MTRRs that is really at fault. As a work-around return the BSP CAR teardown to use wbinvd instead of invd. These platforms do not support S3 resume so this is the easy work-around for the time being. Change-Id: I3dac8785aaf4af5c7c105ec9dd0b95156b7cca21 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-27soc/amd/stoneyridge: Add selectable packagesMarshall Dawson
The StoneyPI package supports Family 15h Models 60h-6Fh and 70h-7Fh in FT4 and FP4 packages. Add options for the packages. The existing convention of SOC_AMD_PRODUCTNAME_PKG will be phased out. Change-Id: I60232ca099b813640742868db08aa66b32265f3b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-11-27binaryPI: Drop CAR teardown without POSTCAR_STAGEKyösti Mälkki
The remaining (active) binaryPI boards moved away from BINARYPI_LEGACY_WRAPPER and have POSTCAR_STAGE now. As the cache_as_ram.S is also used with AGESA, this slightly reduces the codesize there for romstage and postcar as well. This commit is actually a revert for the vendorcode parts, AMD originally shipped the codes using 'invd' for the CAR teardown, but these were changed for coreboot due the convoluted teardown that used to happen with non-empty stack. Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/18526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-27binaryPI: Drop BINARYPI_LEGACY_WRAPPER supportKyösti Mälkki
Drop all the sources that were guarded with this. Change-Id: I6c6fd19875cb57f0caf42a1a94f59efed83bfe0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/19275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-25binaryPI: Remove FieldAccessors.[ch]Kyösti Mälkki
SAGE brought these in outside AGESA specifications and they had some ill semantics. They were already removed from StoneyRidge. Change-Id: I59d0c450583b2ff58031c127aae881d1f3799338 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-11-23vendorcode/amd/pi/Makefile.inc: remove -fno-zero-initialized-in-bssKrystian Hebel
This fixes issue that became visible after implementing post-CAR stage on top of `340e4b80904f lib/cbmem_top: Add a common cbmem_top implementation`. Compilation error was: Forbidden global variables in romstage: ffffff00 d top.2205 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: I088ac824f9b66387843ae5810fd2c75a8b16d9db Reviewed-on: https://review.coreboot.org/c/coreboot/+/36976 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18vendorcode/amd/pi: Integrate Merlin Falcon as a build optionRichard Spiegel
Add changes needed to build a project using Merlin Falcon SOC using 00670F00 vendor code, which is backward compatible with Merlin Falcon. Only the AGESA binary image is different then the one used by 00670F00. BUG=none. TEST=Tested later with padmelon board. Change-Id: Id3341f6a1ef2561a6391d3db8c54f6bdd09b0c0e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-30src/vendorcode/amd/pi: Fix CONFIG() check issue in rules.hSubrata Banik
This patch fixes problem of adding CONFIG() check inside rules.h. Change-Id: Ifb6842d0efef3521642c5c399fdf2876f71b167a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-25AGESA: Move heap_status_name() implementationKyösti Mälkki
Place it within class libagesa to avoid including AGESA internal header heapManager.h in coreboot proper build CPPFLAGS. Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23AGESA binaryPI: Sync STRUCT_NAME definitionsKyösti Mälkki
While not implemented, copying the definitions from later AGESA/AMD.h to older helps us avoid lots of preprocessor directives. Change-Id: I34edc1ca23e9c063c4286273c53249ff0a953798 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31510 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-21binaryPI/00670F000: Remove AGESA.c fileKyösti Mälkki
Change-Id: Id48de8b2f6feb6c29d745140c872215faa32eb37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31487 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-21soc/amd/common: Refactor AmdCreateStruct() useKyösti Mälkki
AmdCreateStruct() and AmdReleaseStruct() are equally bad when it comes to lack of correct function declarations for definitions found in vendorcode binaryPI/AGESA.c. Replace these with calls that go through the common module_dispatch() functions. Change-Id: I611bcbe2a71fb65c8eb759a9dc74cbd9cb74136e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31486 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06soc/amd/common: Introduce module_dispatch()Kyösti Mälkki
This change removes all the separate entrypoint dispatch functions as they all share the same pattern. Furthermore, none of the function definitions under vendorcode binaryPI/AGESA.c file have proper declarations, the ones compiler picks up from AGESA.h are for the internal implementations and with sanely organized headerfiles would not be exposed outside the build of AGESA at all. Change-Id: I0b72badc007565740c93b58743cfd048e8b42775 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31485 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23soc/amd/common: Remove AmdReadEventLog()Kyösti Mälkki
Parameter passing is incorrect here, it should pass complete StdHeader instead of attempting to fill in HeapStatus that should be treated as a field private to AGESA, based on where it is defined in the header files. Furthermore the while() loop did not evaluate the return value. Feature can be brought back at a later date after someone verifies it actually works correctly across different stages. Change-Id: Ib243b275f8700ecaeb330772c795d305c61899c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31484 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-14binaryPI: Fix cache coherency use for AP CPUsKyösti Mälkki
The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise global variables may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all for some cases. Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/26115 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-28vendorcode/amd/pi/00670F00/Lib: Remove folderRichard Spiegel
Now that the last dependency was resolved, remove AmdLib folder. BUG=b:112525011 TEST=Build and boot grunt. Change-Id: Ibd9a20bc358742520138b9b01f76d7fd2fac92ab Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28742 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26vendorcode/amd/pi/00670F00/Proc/PspBaseLib: Remove folderRichard Spiegel
Now that PspBaseLib is no longer used, fully remove the folder. BUG=b:116579642 TEST=Build grunt Change-Id: I441b3f46e2312c12771766f87b25d1dc15ff3af0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-09-24amd/common/psp: Remove use of PspBaseLibCharles Marslett
Eliminate the references to PspBaseLib.c and PspBaseLib.h in agesa_headers.h. Fix psp.c references to definitions in those files by adding them to include/amdblocks/psp.h. BUG=b:78514564 TEST=Build and boot grunt/ChromeOS and restore an image from the internet. Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a Signed-off-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27619 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28vendorcode/amd/pi/00670F00: Remove IDS headersRichard Spiegel
Only Ids.h had definitions still in use, and they were removed or moved to AGESA.h. Now Ids.h, IdsPerf.h and IdsLib.h can be safely removed. BUG=b:112885948 TEST=Build grunt Change-Id: I031ae8eb5f34fee801365fc89ea11a881211e726 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28299 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28vendorcode/amd/pi/00670F00: Transfer TP_Perf_STRUCT to AGESA.hRichard Spiegel
Google is creating code to measure AGESA performance, which needs structure TP_Perf_STRUCT and associated definitions. In preparation to remove IDS headers, move the necessary definitions to AGESA.h. BUG=b:112885948 TEST=Build grunt Change-Id: I941a67a8889a9dbf35c9fd511c7f670623204134 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27vendorcode/amd/pi/00670F00: Transfer IDS_CALLOUT to AGESA.hRichard Spiegel
Currently, IDS_CALLOUT macros are only used in stoneyridge callout. In preparation to remove IDS headers, move the definitions to AGESA.h. BUG=b:112885948 TEST=Build grunt Change-Id: Ia9717eb68fed2e568eaf169157c2837bb8232b7e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-27vendorcode/amd/pi/00670F00/Include/Ids.h: Remove IDS_ERROR_TRAPRichard Spiegel
The macro IDS_ERROR_TRAP is only defined, and never used. Also, IDSOPT_ERROR_TRAP_ENABLED is defined FALSE, so the macro would translate to nothing. Remove the macro and IDSOPT_ERROR_TRAP_ENABLED. BUG=b:112885948 TEST=Build grunt Change-Id: I2c3ca4b0a4a1f96f245ba2f4902fd0051dda77ef Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-27vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove IdsErrorStopRichard Spiegel
Function IdsErrorStop() is only used within AmdLib.c function LibAmdMsrRead(), which in turn is only used once within PspBaseLib.c and three times inside AmdLib.c, all with well defined MSR addresses. IdsErrorStop() is used as a trap if MSR address is 0 or 0xFFFFFFFF, which clearly it's not. Therefore it can be safely removed from AmdLib.c. BUG=b:112885948 TEST=Build grunt Change-Id: I47ffcbd4fbae28b6d711a340f0ac3f3b007e8e4f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-20vendorcode/amd/pi/00670F00/Lib: Remove unused functionsRichard Spiegel
The only code still used are LibAmdPciRead() and LibAmdPciWrite(). These functions are used by PspBaseLib. Remove all functions that are not used, directly or indirectly, by LibAmdPciRead() and LibAmdPciWrite(). BUG=b:112688270 TEST=Build grunt Change-Id: Iba5cfbeee8e83ca78279a1bc2a333370c04f55ed Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28194 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove unused headersRichard Spiegel
Header files AcpiLib.h, FchDef.h and FchBiosRamUsage.h became obsolete when VENDORCODE_FULL_SUPPORT was removed. Therefor they should be removed. BUG=b:112602580 TEST=Build grunt and gardenia. Change-Id: If4fdb9ae1e106ba15f2a073f592499e638e40c65 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28093 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-15Stoneyridge: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from /soc/amd/stoneyridge/Kconfig and from vendorcode/amd/pi/00670F00/Makefile.inc, thus completing the removal of VENDORCODE_FULL_SUPPORT from coreboot. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Idb5f6dc7add1617f7a97a97ae110901b2dec0996 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in preparation to full removal of VENDORCODE_FULL_SUPPORT functions. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Ic23dcf245b2cee24f7363ca3bb9918eb2f11179c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/binaryPI/AGESA.c: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in preparation to full removal of VENDORCODE_FULL_SUPPORT functions. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Id91e76282509743070e34c02082d3f3f46a14059 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Proc/Psp: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from file: vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: I0d590b175a3cf0426580dc9ee5164b3cedc838e2 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from files FchLib.c and FchPeLib.c. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: If24eb7f005720a62a1280fe78ddb54c9d2690150 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Lib: Remove read modify write functionsRichard Spiegel
Now that the functions that used them were safely removed, remove LibAmdIoRMW(), LibAmdMemRMW() and LibAmdPciRMW(). BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: I570bd91cd9eba7798ea39d9685e214fee10824be Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00: Remove functions that use LibAmdPciRMW()Richard Spiegel
The functions that use LibAmdPciRMW() are not used by coreboot and can be safely removed in preparation to remove LibAmdPciRMW() itself. The functions to be removed are: From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c: ProgramPciByteTable(). From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c: RwXhciIndReg(), RwXhci0IndReg() and RwXhci1IndReg(). From vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c: RwPci(). BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: I0b96d3d6b98140ed8e9298817dbe29d55b9e22cb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00: Remove functions that use LibAmdMemRMW()Richard Spiegel
The functions that use LibAmdMemRMW() are not used by coreboot and can be safely removed in preparation to remove LibAmdMemRMW() itself. The functions to be removed are: ProgramFchAcpiMmioTbl() and GetEfuseStatus(), both from vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c. BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: Ib935b1797c4bf8b504fdda6f676fca369169a7f1 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-31src/vendorcode/amd/pi/00670F00: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove all stoney IMC files and functions from vendor code. BUG=b:111780177 TEST=Build grunt and gardenia Change-Id: I06e993fa498cc0978c1d037bc6001682407f7fac Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27652 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-13vc/amd/00670F00: Sync AGESA.h with PI blobMarshall Dawson
Add a new callout definition for AgesaGetTempHeapBase and displace AgesaHeapRebase (which was merged too soon) in the ordering. Also add its structure. AGESA will be modified to ask coreboot for the location for temporary storage of heap data at the end of InitPost. The old methodology is to use 0xb0000 but the change will allow coreboot to determine the location. BUG=b:74518368 Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26145 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22stonyridge: Add TP_Perf_STRUCT structRaul E Rangel
The TP_Perf_STRUCT was missing from pi/00670F00. So I copied the file from src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h and removed everything that we don't need. I did have to change MAX_PERFORMANCE_UNIT_NUM so it matches the size used by pi/00670F00. This struct is used to extract the timestamps from AGESA. BUG=b:64549506 TEST=built on grunt Change-Id: I06ec82348e3d10f2430c1192a925a49389ae4414 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26235 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09vendorcode/amd/pi/00670F00: Control which procedure buildsRichard Spiegel
Vendor code is compiled as a library, thus the whole library is included into the final image. However, not all procedures are required, they are there because original AGESA code had them. We cannot remove them, in order to facilitate porting of fixed AGESA code. Therefor add #if throughout the code to allow the control if unneeded procedures will be build. BUG=b:78610011 TEST=Build and boot grunt; build kahlee and gardenia. Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26135 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09vendorcode/amd/pi/00670F00: Remove unneeded includesRichard Spiegel
Vendor code has several headers included into source code that are not needed in order to build them. Remove unneeded #include. This is part of controlling the build of unneeded procedures within vendor code. BUG=b:78610011 TEST=Build grunt. Change-Id: Id7d451b6be564632836fc64fd343131edb85183a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-06AGESA: Run ar with DTKyösti Mälkki
Create libagesa as a thin and deterministic archive file, this could reduce build time and used space. Change-Id: Icfd1f3fbf54f7e61ab528fa7686331182959c7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/22068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-25vendorcode/amd/pi/00670F00: Remove include headerGarrett Kirkendall
Remove Fch.h from being included in src/vendorcode/amd/pi/00670F00/agesa_headers.h. It is not needed. BUG=b:69220826 BRANCH=master TEST=build Gardenia and Grunt systems. Change-Id: Ifde58421d20c813ae5708b1d9c6ec76433051d33 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-23 23:52:38 +0000