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2019-02-25AGESA vendorcode: Define libagesa rule just onceKyösti Mälkki
No reason to keep this rule in per-family directory. Change-Id: I6bfc9a277674077774c4cb398f8add5e4fa99c69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31509 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-14binaryPI: Fix cache coherency use for AP CPUsKyösti Mälkki
The memory between _car_region_start .. _car_region_end has to be set up as WB in MTRRs for all the cores executing through bootblock, verstage and romstage. Otherwise global variables may fail on AP CPUs. Fixes combination of CBMEM_CONSOLE=y with SQUELCH_EARLY_SMP=n, which previously did not boot at all for some cases. Change-Id: I4abcec90c03046e32dafcf97d2f7228ca93c5549 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/26115 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17vendorcode/{amd,cavium,intel}: Remove trailing whitespacePeter Lemenkov
find src -type f "!" -regex ".*\.\(vbt\|bin\)" -exec sed -i -e "s,\s\+$,,g" {} \; Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/30959 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14AGESA/PI: replace HUDSON_DISABLE_IMC with HUDSON_IMC_ENABLEMike Banon
Only a few boards are using IMC for the onboard fan control, so regarding the availability of IMC selection it should be opt-in, not opt-out. Also, select HUDSON_IMC_ENABLE for Gizmo 2 because Gizmo 2 could use IMC for the onboard fan control. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I3590b13c3b155405d61e373daf1bd82ca8e3bd16 Reviewed-on: https://review.coreboot.org/c/30756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-12-18Fix typos involving "the the"Jonathan Neuschäfer
Change-Id: I179264ee6681a7ba4488b9f1c6bce1a19b4e1772 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-23src: Typo fix (cosmetic)Peter Lemenkov
Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-28vendorcode/amd/pi/00670F00/Lib: Remove folderRichard Spiegel
Now that the last dependency was resolved, remove AmdLib folder. BUG=b:112525011 TEST=Build and boot grunt. Change-Id: Ibd9a20bc358742520138b9b01f76d7fd2fac92ab Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28742 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26vendorcode/amd/pi/00670F00/Proc/PspBaseLib: Remove folderRichard Spiegel
Now that PspBaseLib is no longer used, fully remove the folder. BUG=b:116579642 TEST=Build grunt Change-Id: I441b3f46e2312c12771766f87b25d1dc15ff3af0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-09-24amd/common/psp: Remove use of PspBaseLibCharles Marslett
Eliminate the references to PspBaseLib.c and PspBaseLib.h in agesa_headers.h. Fix psp.c references to definitions in those files by adding them to include/amdblocks/psp.h. BUG=b:78514564 TEST=Build and boot grunt/ChromeOS and restore an image from the internet. Change-Id: I2740ceb945736c6e413f7d0bd0c41a19e19c7d5a Signed-off-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27619 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20src/vendorcode/amd/agesa: Improve formatting of some f12 and f14 microcodesMike Banon
It is much more convenient to view these files if there are 8 values per line, not 1 value which results in a very long file. The contents remain the same: these microcodes are still the latest publicly available at the time of writing. Change-Id: I3e5296a5b5e895702a60aca1ded7418bb345263d Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/28391 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20src/vendorcode/amd/agesa/f12: Update microcode to version 0x3000027 2011-09-13Mike Banon
This microcode update for CPU ID 0x300F10 should improve the system stability. It is a part of microcode_amd.bin officially released by AMD at linux-firmware: it starts at 0x217C offset, and size is 0x03C0 as specified priorly at 0x2178. Old version: 0x300000F [2010-04-10] replaced by New version: 0x3000027 [2011-09-13] Change-Id: I9650fab377d957904318ebb393323c2509cfea26 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/28378 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28vendorcode/amd/pi/00670F00: Remove IDS headersRichard Spiegel
Only Ids.h had definitions still in use, and they were removed or moved to AGESA.h. Now Ids.h, IdsPerf.h and IdsLib.h can be safely removed. BUG=b:112885948 TEST=Build grunt Change-Id: I031ae8eb5f34fee801365fc89ea11a881211e726 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28299 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28vendorcode/amd/pi/00670F00: Transfer TP_Perf_STRUCT to AGESA.hRichard Spiegel
Google is creating code to measure AGESA performance, which needs structure TP_Perf_STRUCT and associated definitions. In preparation to remove IDS headers, move the necessary definitions to AGESA.h. BUG=b:112885948 TEST=Build grunt Change-Id: I941a67a8889a9dbf35c9fd511c7f670623204134 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27vendorcode/amd/pi/00670F00: Transfer IDS_CALLOUT to AGESA.hRichard Spiegel
Currently, IDS_CALLOUT macros are only used in stoneyridge callout. In preparation to remove IDS headers, move the definitions to AGESA.h. BUG=b:112885948 TEST=Build grunt Change-Id: Ia9717eb68fed2e568eaf169157c2837bb8232b7e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-27vendorcode/amd/pi/00670F00/Include/Ids.h: Remove IDS_ERROR_TRAPRichard Spiegel
The macro IDS_ERROR_TRAP is only defined, and never used. Also, IDSOPT_ERROR_TRAP_ENABLED is defined FALSE, so the macro would translate to nothing. Remove the macro and IDSOPT_ERROR_TRAP_ENABLED. BUG=b:112885948 TEST=Build grunt Change-Id: I2c3ca4b0a4a1f96f245ba2f4902fd0051dda77ef Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-27vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove IdsErrorStopRichard Spiegel
Function IdsErrorStop() is only used within AmdLib.c function LibAmdMsrRead(), which in turn is only used once within PspBaseLib.c and three times inside AmdLib.c, all with well defined MSR addresses. IdsErrorStop() is used as a trap if MSR address is 0 or 0xFFFFFFFF, which clearly it's not. Therefore it can be safely removed from AmdLib.c. BUG=b:112885948 TEST=Build grunt Change-Id: I47ffcbd4fbae28b6d711a340f0ac3f3b007e8e4f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-27vendorcode/amd/cimx/sb*: Rename RSDP headerMarc Jones
Rename RSDP to RSDP_HEADER to match other AMD vendorcode and to not pollute the namespace. We will use RSDP in a future patch. Change-Id: I3b66135ae1732b86b5ebfcdc01a850a0d9d3eb50 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-20vendorcode/amd/pi/00670F00/Lib: Remove unused functionsRichard Spiegel
The only code still used are LibAmdPciRead() and LibAmdPciWrite(). These functions are used by PspBaseLib. Remove all functions that are not used, directly or indirectly, by LibAmdPciRead() and LibAmdPciWrite(). BUG=b:112688270 TEST=Build grunt Change-Id: Iba5cfbeee8e83ca78279a1bc2a333370c04f55ed Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28194 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20vendorcode/amd/agesa/f15tn: add Richland RL-A1 to the equivalence tableMike Banon
This small change is required for the successful loading of microcode from F15TnMicrocodePatch0600110F_Enc.c for the Richland RL-A1 CPUs, such as A10-5750M found at coreboot-supported Lenovo G505S laptop. Richland RL-A1 and Trinity TN-A1 CPUs are using the same microcode, so the Richland RL-A1 IDs should be added to this equivalence table. Function `GetPatchEquivalentId()` in `src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c` goes through the equivalence table like below. for (i = 0; i < (EquivalencyEntries * 2); i += 2) { // check for equivalence if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) { *ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1]; return (TRUE); } } Change-Id: I7a68f2fef74fb4c578c47645f727a9ed45526f69 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/28204 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: <awokd@danwin1210.me> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove unused headersRichard Spiegel
Header files AcpiLib.h, FchDef.h and FchBiosRamUsage.h became obsolete when VENDORCODE_FULL_SUPPORT was removed. Therefor they should be removed. BUG=b:112602580 TEST=Build grunt and gardenia. Change-Id: If4fdb9ae1e106ba15f2a073f592499e638e40c65 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28093 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-15Stoneyridge: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from /soc/amd/stoneyridge/Kconfig and from vendorcode/amd/pi/00670F00/Makefile.inc, thus completing the removal of VENDORCODE_FULL_SUPPORT from coreboot. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Idb5f6dc7add1617f7a97a97ae110901b2dec0996 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in preparation to full removal of VENDORCODE_FULL_SUPPORT functions. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Ic23dcf245b2cee24f7363ca3bb9918eb2f11179c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/binaryPI/AGESA.c: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from file above mentioned file, in preparation to full removal of VENDORCODE_FULL_SUPPORT functions. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: Id91e76282509743070e34c02082d3f3f46a14059 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Proc/Psp: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from file: vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: I0d590b175a3cf0426580dc9ee5164b3cedc838e2 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove VENDORCODE_FULL_SUPPORTRichard Spiegel
Remove VENDORCODE_FULL_SUPPORT from files FchLib.c and FchPeLib.c. BUG=b:112578491 TEST=none, VENDORCODE_FULL_SUPPORT already not used. Change-Id: If24eb7f005720a62a1280fe78ddb54c9d2690150 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00/Lib: Remove read modify write functionsRichard Spiegel
Now that the functions that used them were safely removed, remove LibAmdIoRMW(), LibAmdMemRMW() and LibAmdPciRMW(). BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: I570bd91cd9eba7798ea39d9685e214fee10824be Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00: Remove functions that use LibAmdPciRMW()Richard Spiegel
The functions that use LibAmdPciRMW() are not used by coreboot and can be safely removed in preparation to remove LibAmdPciRMW() itself. The functions to be removed are: From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c: ProgramPciByteTable(). From vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c: RwXhciIndReg(), RwXhci0IndReg() and RwXhci1IndReg(). From vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c: RwPci(). BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: I0b96d3d6b98140ed8e9298817dbe29d55b9e22cb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15vendorcode/amd/pi/00670F00: Remove functions that use LibAmdMemRMW()Richard Spiegel
The functions that use LibAmdMemRMW() are not used by coreboot and can be safely removed in preparation to remove LibAmdMemRMW() itself. The functions to be removed are: ProgramFchAcpiMmioTbl() and GetEfuseStatus(), both from vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c. BUG=b:112541697 TEST=Build grunt and gardenia Change-Id: Ib935b1797c4bf8b504fdda6f676fca369169a7f1 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-31src/vendorcode/amd/pi/00670F00: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove all stoney IMC files and functions from vendor code. BUG=b:111780177 TEST=Build grunt and gardenia Change-Id: I06e993fa498cc0978c1d037bc6001682407f7fac Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27652 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-13vc/amd/00670F00: Sync AGESA.h with PI blobMarshall Dawson
Add a new callout definition for AgesaGetTempHeapBase and displace AgesaHeapRebase (which was merged too soon) in the ordering. Also add its structure. AGESA will be modified to ask coreboot for the location for temporary storage of heap data at the end of InitPost. The old methodology is to use 0xb0000 but the change will allow coreboot to determine the location. BUG=b:74518368 Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26145 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24Remove leftover AMD CIMX RD890 vendorcodeKyösti Mälkki
Change-Id: Ic7d80b25c0815f3816ae40646d024e0d9fe61f08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-22stonyridge: Add TP_Perf_STRUCT structRaul E Rangel
The TP_Perf_STRUCT was missing from pi/00670F00. So I copied the file from src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h and removed everything that we don't need. I did have to change MAX_PERFORMANCE_UNIT_NUM so it matches the size used by pi/00670F00. This struct is used to extract the timestamps from AGESA. BUG=b:64549506 TEST=built on grunt Change-Id: I06ec82348e3d10f2430c1192a925a49389ae4414 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26235 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-10AGESA f14: Remove OPTION_DDR2Kyösti Mälkki
Was never used for the boards in our tree. Change-Id: Ib9e9ab25ccb8d1d556fdeb8bb4c6558f25bb81b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-10AGESA f14 vendorcode: Only have f14 Ontario configKyösti Mälkki
Change-Id: I8cf2f23d785e934371dfa687483491cd22b9863d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-09vendorcode/amd/pi/00670F00: Control which procedure buildsRichard Spiegel
Vendor code is compiled as a library, thus the whole library is included into the final image. However, not all procedures are required, they are there because original AGESA code had them. We cannot remove them, in order to facilitate porting of fixed AGESA code. Therefor add #if throughout the code to allow the control if unneeded procedures will be build. BUG=b:78610011 TEST=Build and boot grunt; build kahlee and gardenia. Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26135 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09vendorcode/amd/pi/00670F00: Remove unneeded includesRichard Spiegel
Vendor code has several headers included into source code that are not needed in order to build them. Remove unneeded #include. This is part of controlling the build of unneeded procedures within vendor code. BUG=b:78610011 TEST=Build grunt. Change-Id: Id7d451b6be564632836fc64fd343131edb85183a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-06AGESA: Remove remains of HT recoveryKyösti Mälkki
While built, this code was never called. Change-Id: Ie8216d8f4636330d38ea02aab83bc9e440864f17 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-06AGESA f14: Remove early HT initKyösti Mälkki
Syncronise HT init code with f12 vendorcode. Constructor for HT init is not required since init itself is not called. Change-Id: I0552c4d019c700f84d98473978afb18fe4eea1e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-06AGESA: Run ar with DTKyösti Mälkki
Create libagesa as a thin and deterministic archive file, this could reduce build time and used space. Change-Id: Icfd1f3fbf54f7e61ab528fa7686331182959c7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/22068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-03vendorcode/amd/agesa: Fix variable length array declarationKyösti Mälkki
Fix (assumed) regression with commit ac63b41 vendorcode/amd/agesa: Fix variable length array declaration The code used sizeof() on the struct where array length was previously adjusted, but only f14 case was fixed accordingly. Change-Id: Ib83660d5e102e13b4ffad19fb78f695ac4a871dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26036 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03vendorcode/amd/agesa: Fix variable length array declarationPaul Menzel
Definition of S_PSTATE only allowed PStateStruct[0], while it is effectively used as a flexible array. Since sizeof(S_PSTATE) is reduced here by sizeof(S_PSTATE_VALUES), we have to account for that when calculating PStateLevelingSizeOfBytes. In S_PSTATE context, PStateStruct[PStateMaxValue] is valid reference. GCC 7.2.0 warns about an out of bounds array subscript. ``` CC libagesa/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.o src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c: In function 'PStateLevelingMain': src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c:524:65: error: array subscript is above array bounds [-Werror=array-bounds] PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html Change-Id: If9598a951c6b882432689b677a956c44650c7083 Found-by: gcc (Debian 7.2.0-2) 7.2.0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21297 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-25vendorcode/amd/pi/00670F00: Remove include headerGarrett Kirkendall
Remove Fch.h from being included in src/vendorcode/amd/pi/00670F00/agesa_headers.h. It is not needed. BUG=b:69220826 BRANCH=master TEST=build Gardenia and Grunt systems. Change-Id: Ifde58421d20c813ae5708b1d9c6ec76433051d33 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16vendorcode/amd/pi/00670F00: Remove unused headersGarrett Kirkendall
Remove unused header files in src/vendorcode/amd/pi/00670F00/agesa_headers.h. This is a first clean up. Hopefully more headers will be removed in other commits. Header files cannot be removed at this time. They are used by files in vendorcode/amd/pi/00670F00/. BUG=b:77944801 BRANCH=none TEST=build Gardenia and Grunt Change-Id: I99b77f6ba41ded30122a01bbe709681312561436 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25644 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16vendorcode/amd/pi/00670F00: Remove unused headersGarrett Kirkendall
Remove unused AGESA header files from vendorcode/amd/pi/00670F00/binaryPI/AGESA.c BUG=b:77905293 BRANCH=none TEST=build Gardenia. Change-Id: Ic38424d489dcc37a4074159e33fca0d49c71f701 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-11Correct "MTTR" to "MTRR"Jonathan Neuschäfer
The term MTRR has been misspelled in a few places. Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-06vc/amd/stoneyridge: Add definition for AGESA heap rebaseMarshall Dawson
AgesaHeapRebase is an optional callout that allows AGESA to use a coreboot-managed heap base address. Its internal default location is determined by AMD_HEAP_START_ADDRESS which is defined as 4 MB. Add a #define that AGESA may use once the feature is available. BUG=b:74518368 Change-Id: Id23455779b1c8c4931ad1a3122587e09ad237ecc Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-16stoneyridge: Update AGESA binary and AGESA.hRichard Spiegel
AGESA.bin was updated in the binary repo, so update the submodule pointer. Among other changes, this added a callback "AGESA_HALT_THIS_AP", which requires updated header files. BUG=b:70338633 TEST=build kahlee. Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25183 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-12vc/amd/00670F00: Introduce S3FinalRestore helperMarshall Dawson
The Arch2008 spec describes an AmdS3FinalRestore Entry Point that coreboot has been missing. Add the helper function that can call into the blob to execute this. BUG=b:69614064 Change-Id: Ic72feb0406cd1d0d5c23e391c2464e12c9e10007 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-01vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9Marc Jones
Update the shared AGESA headers to 1.3.0.9. This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated to the same version. BUG=b:72679320 TEST=build and boot Grunt Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 19:38:51 +0000