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2020-07-23soc/intel/xeon_sp/cpx: display SystemMemoryMapHob fieldsJonathan Zhang
SystemMemoryMapHob is necessary for SMBIOS type 17 among other things. It is a fairly large structure, so the pointer to the data instead of the structure itself, is included in the HOB. Use pointer to SystemMemoryMapHob structure to interpret SystemMemoryHob HOB body. Adjust the structure definition to match with CPX-SP ww28 release. Display more fields to ensure the structure definition is correct. TEST=Boot DeltaLake server, and check field values of SystemMemoryMapHob to make sure they are correct: 0x7590a090, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION f8870015-6994-4b98-95a2bd56da91c07f: FSP_SYSTEM_MEMORYMAP_HOB_GUID ================== MEMORY MAP HOB DATA ================== hob: 0x777f7000, structure size: 0x6c88 lowMemBase: 0x0, lowMemSize: 0x20, highMemBase: 0x40, highMemSize: 0x5d0 memSize: 0x600, memFreq: 0xb76 NumChPerMC: 3 SystemMemoryMapElement Entries: 2, entry size: 16 memory_map 0 BaseAddress: 0x0, ElementSize: 0x20, Type: 0x1 memory_map 1 BaseAddress: 0x40, ElementSize: 0x5d0, Type: 0x1 BiosFisVersion: 0x0 MmiohBase: 0x80000 0x777f7000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I271bcbd6030276b8fcd99d5b4f2c93f034dd9b52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43336 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3274Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3274. Compared to the current version 3197, v3274 adds most of the legacy UPDs in both FSPM and FSPS. BUG=b:159151231 BRANCH=none TEST=build and boot volteer proto2 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Id3f957aa9d9ad9710a3c930717c22f485699315e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43473 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12soc/intel/xeon_sp/cpx: use HOB_TYPE_GUID_EXTENSION to interpret platform HOBsJonathan Zhang
Platform HOBs (in particular IIO_UDS and MemoryMap HOBs) are of HOB type HOB_TYPE_GUID_EXTENSION, therefore they do not have resource structure. Remove the erroneous code related to resource structure. Remove unnecessary function prototypes from header files, and define them as static in hob_display.c. Since we have the HOB pointer, there is not need to search HOB by GUID. Remove unnecessary calling of fsp_find_extension_hob_by_guid(). Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: Ib99bce39e6eb2aeb95242dfba36774653bbe91fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/43335 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12vendocode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww28 release and adapt socJonathan Zhang
CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX. Also update IIO UDS HOB definition file accordingly. Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG. Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel is that they will converge to use FSPM_CONFIG over time. So both will co-exist for some time. Today coreboot common code expects FSP_M_CONFIG. Accomodate this situation in FspmUpd.h. The CPX-SP soc code is updated accordingly. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-07vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt socJonathan Zhang
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also update memory map HOB definition file accordingly. The CPX-SP soc code is updated to direct FSP log to SOL. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194Ronak Kanabar
The FSP-M/S headers added are generated as per FSP v2194. BUG=b:159193895 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: TBD Change-Id: I0cd84fdb0089bf8ea3f4440e89fdee7f11119751 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42471 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt socJonathan Zhang
The previous Intel CPX-SP FSP release was ww20 release. The ww22 release fixs issues related to FSP_NV_STORAGE HOB. The end of end flow of using memory training data to generate FSP_NV_STORAGE HOB and using memory training data passed from bootloader to skip memory training, works now. This saves 8 minutes of boot time (with FSP verbose logging enabled on DeltaLake server). This release also adds UPD parameters to support IIO bifuration. The ww24 release has following updates: a. Removed a number of unnecessary UPD parameters, such as mmiolSize, mmiolBase, OemHookPostTopologyDiscovery, OemGetResourceMapUpdate. b. Added UPD parameters to support PCIe ports configuration. c. Updated IIO_UNIVERSAL_DATA HOB, each stack now has mmio base/limit fields, in addition to PCIe resource memory base/limit fields. With ww24 release, the issue with PCIe link training persists. On YV3 config A, the onboard NIC card has x4 connection to port 2D. This NIC device is not recognized by FSP. Corresponding soc/intel/xeon_sp/cpx change is made: * There are changes in PLATFORM_DATA structure, so hob_display.c is updated. * There are changes in UPD parameters, so romstage.c is updated. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41903 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25vendorcode/intel: Add edk2-stable202005 supportJonathan Zhang
This patch includes (edk2/edk2-stable202005) all required headers for edk2-stable202005 quarterly EDK2 tag from EDK2 github project using below command: >> git clone https://github.com/tianocore/edk2.git vedk2-stable202005 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I3172505d9b829647ee1208c87623172f10b39310 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42239 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18vendorcode/intel/fsp: Update MemInfoHob header for Jasper LakeAamir Bohra
Jasper Lake has been using the incorrect MemInfoHob header. Updating the header to align it with Jasper Lake MRC code. BUG=b:158722318 TEST=Verify memory info is populated for channnel 0 and 1 on wadddledoo. Change-Id: Icca3e3b4cda9ca257f3b725823facf52ceec37b7 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-06-12vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3197 to include below additional UPD: FSP-M: SkipCpuReplacementCheck PCH HSIO Tuning UPDs FSP-S: PcieRpHotPlug TccActivationOffset TccOffsetClamp TccOffsetLock TccOffsetTimeWindowForRatl USB3 HSIO Tuning UPDs BUG=none BRANCH=none TEST=build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ib40d226dd2ecc4fb34965e1f2c416c53edef01d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42243 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3197 to include below additional UPD: FSPS: ITbtConnectTopologyTimeoutInMs Signed-off-by: John Zhao <john.zhao@intel.com> Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I06d605b156c1e6f90921c20e0b8fbbe4d64916ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/42046 Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3197Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3197, which includes below additional UPDs: FSPM: CmdMirror RMTBIT FSPS: SataPortsEnableDitoConfig BUG=b:157725468 BRANCH=none TEST=build and boot volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I23d6baacc3d963b473280c7fdb1e5df950cd7ca8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41974 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02vendorcode/intel/fsp/fsp2_0/cpx_sp: update to FSP WW20 releaseJonathan Zhang
Update Cooperlake-SP (CPX-SP) FSP header files to WW20 release. As CPX-SP FSP engineering is on-going (the processor Mass Production is some time in this year). These header files will be adjusted when changes are necessary with newer FSP release. This commit corresponds to FSP release WW20 (tag WHITLEY.0.PRB.0016.D.65). Also update soc/xeon_sp code file and Skylake-SP header file accordingly to use FsptPort80RouteDisable instead of PcdPort80RouteDisable. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/40034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-01src: Fix up ##-commented SPDX headersAngel Pons
Delete leading empty comment lines. Change-Id: If1c5f568af3290c329d22dfc054d10d01c079065 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-26vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2114Ronak Kanabar
The FSP-M/S headers added are generated as per FSP v2114. Following UPDs are deprecated - IedSize - EnableC6Dram Following UPDs are added - TurboMode - PavpEnable - CnviMode - CnviBtCore - PchFivrExtV1p05RailEnabledStates - PchFivrExtVnnRailSxEnabledStates - PchFivrVccinAuxRetToLowCurModeVolTranTime - PchFivrVccinAuxRetToHighCurModeVolTranTime - PchFivrVccinAuxLowToHighCurModeVolTranTime - PchLockDownGlobalSmi - PchLockDownBiosInterface - PchLockDownBiosLock BUG=b:155054804 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: TBD Change-Id: Id9355a1eccfbdc1e9a07b37cb3d8e3de125054d9 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-18vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3163, which includes below additional UPDs: FSPM: TcssDma0En TcssDma1En FSPS: PchFivrExtV1p05RailEnabledStates PchFivrExtV1p05RailSupportedVoltageStates PchFivrExtVnnRailEnabledStates PchFivrExtVnnRailSupportedVoltageStates PchFivrExtVnnRailSxVoltage PchFivrExtV1p05RailIccMaximum CstateLatencyControl5TimeUnit VmdEnable BUG=none BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Icc893073629df59aef60162bed126d1f4b936e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41377 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3163. Which includes below additional UPDs: FSPM: -BootFrequency -SerialIoUartDebugMode FSPS: -PcieRpPmSci -PchPmWoWlanEnable -PchPmWoWlanDeepSxEnable -PchPmLanWakeFromDeepSx BUG=b:155315876 BRANCH=none TEST=build and boot ripto/volteer Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ida87ac7dd7f5fd7ee0459ae1037a8df816976083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40898 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v2527Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 2527. Which includes below additional UPDs: FSPM: - PchTraceHubMode - CpuTraceHubMode - CpuPcieRpEnableMask FSPS: - D3HotEnable - D3ColdEnable - RtcMemoryLock - PchLockDownGlobalSmi - PchLockDownBiosInterface - PchUnlockGpioPads - CpuMpPpi - ThcPort0Assignment - ThcPort1Assignment BUG=b:150357377 BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I0cdce28b01f291dbb02a01ded7629e94c77b7e47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40026 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31vendorcode/intel/fsp: Update FSP header for Tiger LakeRonak Kanabar
Update FSPM header to include DisableDimmCh Upds for Tiger Lake platform version 2457. BUG=b:152000235 BRANCH=none TEST="Build and Boot on Ripto/Volteer" Change-Id: Ic743cb2134e6273a63c1212506c81ccbbdec442a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-26vendorcode: Add fake Cooperlake-SP FSP header filesAndrey Petrov
These header files are just placeholders. Currently FSP does not look into any real platform-specific UPD fields anyway, so having padding instead of real thing makes no difference. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: Id123f4386124b2ceb7776ab719a9970c9c23a0e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-25soc/intel/cometlake: Use IntelFSP repoFelix Singer
Make use of the publicly-available FSP binaries and headers for Comet Lake. Also, remove the Comet Lake header files from src/vendorcode, since they are no longer necessary. Change-Id: I392cc7ee3bf5aa21753efd6eab4abd643b65ff94 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39372 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger LakeSrinidhi N Kaushik
Update FSPS header to include HybridStorageMode Upd for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ib6ac89163c0f7a11910e56b9804e386f8bcf355d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-06vendorcode/intel/fsp/fsp2_0/skylake_sp: update header filesJonathan Zhang
Added definitions in FspmUpd.h. Added gpio_fsp.h file which has definitions needed by mainboard gpio header file, to set gpio configuration through FSP-M UPD. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: I72727952685b5e453f4cde6c2e7e7fc7114c6884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <anpetrov@fb.com>
2020-03-03vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header for Tiger LakeSrinidhi N Kaushik
Update FSPM header to add Vtd related Upds for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I063f921832a4e4a45eb6978b6dbb37b1ac7dde7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-02vendorcode/intel/fsp/fsp2_0: Add FSP header files for Skylake-SPJonathan Zhang
Add header files for FSP of Skylake Scalable Processor. These header files are from an Intel SKX-SP FSP engineering build. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Tested-by: johnny_lin@wiwynn.com Change-Id: If47f102c2c7979da1196f8c6b315d5be558e786c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <anpetrov@fb.com>
2020-02-28vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2052Ronak Kanabar
The FSP-M/S headers added are generated as per FSP v2052. Change-Id: Icb911418a6f8fe573b8d097b519c433e8ea6bd73 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-02-26vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header file for Tiger LakeRonak Kanabar
Update FSP header file for Tiger Lake platform version 2457. Add SerialIoUartAutoFlow, Enable8254ClockGating, Enable8254ClockGatingOnS3 UPD Change-Id: Ib2a08ce73526fb0eb4e7c2a674af78c2913f0a08 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-11vendorcode/intel: Remove Ice Lake FSP BindingsJohanna Schander
By updating the FSP submodule we now got all FSP headers from within that repo. This commit changes the default paths to use these and fixes some include paths to allow the usage of vendorcode/intel/edk2/UDK2017 together with the official Intel distribution. We are also adding back the CHANNEL_PRESENT enum, that is missing in the official headers. This was tested on the Razer Blade Stealth (late 2019). Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37579 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header files for Tiger LakeSrinidhi N Kaushik
Update FSP header files for Tiger Lake platform version 2457. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I47574844a8b5fd888e8e75ed2f60f6df465b33ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/38555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-12-26vendorcode/intel/fsp/fsp2_0/tgl: Add FSP header files for Tiger LakeSubrata Banik
Add header files for FSP for Tiger Lake platform version 2457. Change-Id: I52bb2e164cc89d3535fe67493686d1e8e064e31e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-12-16vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v1433Aamir Bohra
The FSP-M/S/T headers added are generated as per FSP v1433. Change-Id: Iacb44204c3f7220a20ab3edc2163c97188014bbf Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37559 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-21soc/intel/fsp_baytrail: Drop supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-21nb/sb/cpu: Drop Intel Rangeley supportArthur Heymans
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-11-12vendorcode/intel/Kconfig: Hide UDK_VERSION when unneededElyes HAOUAS
This cleans .config from unused UDK_VERSION's symbol. Change-Id: I2a17db711f615d388dbd964f67ff2cc7875c54fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34536 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25src/vendorcode/intel: Update Comet Lake FSP headers as per FSP v1394Ronak Kanabar
"EnforceEDebugMode" UPD added in FSP_S_TEST_CONFIG Change-Id: I1583d8583db20b29505e5a7ae4084013334c87c2 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35852 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344Ronak Kanabar
Cq-Depend: chrome-internal:1759167 Change-Id: Ib5784eb8c0f7c6e56950dad5c8254e00aa73cef4 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35245 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessorKyösti Mälkki
Remove cases of __PRE_RAM__ and other preprocessor guards. Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1263Aamir Bohra
Change-Id: Ia29769f1fc9947d9e37de2534c9486d21a4c9eae Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-12vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155Aamir Bohra
This CL implements below changes: 1) Update FSP-M and FSP-S header files as per FSP release version 1155. 2) Update the PcdSerialIoUartNumber reference in fsp_params.c with SerialIoUartDebugControllerNumber. Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32844 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-09vendorcode/intel/../icelake: Update ICL FSP header BIOS version 3092Subrata Banik
After building from here : https://chrome-internal.googlesource.com/chromeos/third_party/intel-fsp/icl/+/refs/tags/upstream/BIOS_Version_3092 Change-Id: I8924dbf4a8d6a303540ced1c9c48586d26d6beaa Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-04-04Make common macros double-evaluation safeJulius Werner
I just got hit by a double-evaluation bug again, it's time to attempt to fix this once more. Unfortunately there are several issues that don't make this easy: - bitfield variables don't support typeof() - local macro variables that shadow others trigger -Werror=shadow - sign warnings with integer literal and unsigned var in typeof-MIN() - ({ statement expressions }) can not be used outside functions - romcc doesn't support any of the fancy GCC/clang extensions This patch tries to address all of them as far as possible with macro magic. We don't have the technology to solve the bitfield and non-function context issues yet (__builtin_choose_expr() still throws a "no statement expression outside a function" error if it's only in the branch that's not chosen, unfortunately), so we'll have to provide alternative macros for use in those cases (and we'll avoid making __ALIGN_MASK() double-evaluation safe for now, since it would be annoying to do that there and having an alignment mask with side effects seems very unlikely). romcc can continue using unsafe versions since we're hopefully not writing a lot of new code for it. Sign warnings can be avoided in literal/variable comparisons by always using the type of the variable there. Shadowing is avoided by picking very explicit local variable names and using a special __COUNTER__ solution for MIN() and MAX() (the only ones of these you're likely to nest). Also add DIV_ROUND_UP() to libpayload since it's a generally quite useful thing to have. Change-Id: Iea35156c9aa9f6f2c7b8f00991418b746f44315d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-15vendorcode/intel/fsp/fsp2_0/cnl: Update FSP header files for CannonlakeJohn Zhao
Update FSP header files for Cannonlake platform. Change-Id: I7f1a1f61c32510062a440c14a897e95bed7a9718 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-03-12vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for CometlakeRonak Kanabar
Update header files for FSP for cometlake platform version 1065 BUG=b:125439832 Change-Id: I1eb679f842915f256137a33c09e20f5881d5143d Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-03-06vendorcode/intel/fsp/fsp2_0/cml: Update FSP header files for CometlakeSubrata Banik
Update header files for FSP for cometlake platform version 1065 Change-Id: I7be7535975b442490cc77c9c1dca4ef7a2d43a58 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-02-28vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for CometlakeMaulik V Vaghela
Adding header files for FSP for cometlake platform version 1034 Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-02-11mb/intel/galileo: Drop the FSP1.1 optionArthur Heymans
This board is EOL and has FSP2.0 support, so drop the older version. Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-30soc/intel/apollolake: Sync fsp upd structure updateJohn Zhao
FSP 2.0.9 provides UPD interface to adjust integrated filter value, usb3 LDO and pmic vdd2 voltage. Change coreboot upd structure to sync with fsp 2.0.9 release. BUG=b:123398358 CQ-DEPEND=CL:*817128 TEST=Verified yorp boots to kernel. Change-Id: I3d17dfbe58bdc5222378459723da8e9ac0573510 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/31131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-06 06:04:38 +0000