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2018-01-31vendorcode/intel/fsp/fsp2_0: Add CannonLake FirmwareVersionInfoHob headerSubrata Banik
Base patch to create Firmware Version Info (FVI) for CannonLake coreboot platform using CannonLake FSP new feature. Expectation is that, FSP will provide version information of all Firmware ingredient its equip with (i.e. CPU Ref Code, uCode version, MCH Ref Code, CSE Sku type, CSE version, System Agent Ref Code, OpRom Version, GOP version, PCH Ref Code version etc.) Change-Id: Ic388e036709190e8d5c5010f4ea87223291f21d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31intel/fsp: Update cannonlake fsp headerLijian Zhao
Update Cannonlake FSP header to revision 7.x.20.52. Following changes had been made: 1. Hide internal EV related options. 2. Add GT voltage override options. 3. Add PEG IMR selection. 4. Add PCH DMI ASPM options. TEST=NONE Change-Id: If186a1eb440266f1eaeb03505fe0ff4c6a521be6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-31vendorcode/intel/fsp: Remove TODOs and make use of EDK2 headerSubrata Banik
This patch ensures MemInfoHob.h file can make use of existing UEFI headers as is rather than redefining the same structure locally. TEST=Download BIOS_Version_122.3 from external github and build MemInfoHob.h without any compilation error. Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31vendorcode/intel: Add Kconfig option to get UDK_VERSIONSubrata Banik
This patch ensures if required SoC/FSP driver code can retrieve UDK version for a platform. Change-Id: I3120ce512255ed6f2a40413e8e6d8000c7285b39 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31vendorcode/intel: Add UDK2017 supportSubrata Banik
This patch includes (edk2/UDK2017) all required headers for UDK2017 from EDK2 github project using below command >> git clone https://github.com/tianocore/edk2.git vUDK2017 commit hash: 66833b2a87d98be8d81d1337c193bcbf0de47d47 Change-Id: If0d5a3fef016c67e9eed6aed9b698b3b13b930c4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-24AGESA f15 cimx/sb700: Remove vendorcode sourceKyösti Mälkki
Change-Id: If5a72786d1119908073488c1d6d8787ac0f4f95c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-24AGESA f15 cimx/sb700: Remove unused chips codeKyösti Mälkki
Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/23275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23binaryPI vendorcode: Remove HeapXXBuffer functionsKyösti Mälkki
The HeapAllocateBuffer and HeapDeallocateBuffer functions are not used. Change-Id: I491a796d87afd0e37051f9caabfff3f70d4d803c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/22069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-23AGESA_LEGACY: Apply final cleanup and file removalsKyösti Mälkki
With no boards left using AGESA_LEGACY, wipe out remains of that everywhere in the tree. Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Change TPM naming for different layers.Philipp Deppenwiese
* Rename tlcl* to tss* as tpm software stack layer. * Fix inconsistent naming. Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-18security/tpm: Move tpm TSS and TSPI layer to security sectionPhilipp Deppenwiese
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17AGESA f15: Drop CAR teardown without POSTCAR_STAGEKyösti Mälkki
Change-Id: Ie5ff62ee1c7ca193ba841c5b2fb20940ec657625 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v77_12Srinidhi N Kaushik
Update FSP header files to match FSP v77_12 Following fields have been added in FSP-S UPD: - SkipPunitInit (Skip P-unit Initialization) - HgSubSystemId (Sub system Vendor ID VGA) Change-Id: I6c4c2580b2d0d76038b495be31744c04cc0dc959 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/22820 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-05soc/amd/common: load post-memory AGESA as rmoduleAaron Durbin
Now that the AGESA binary is split into two sections load the post-memory AGESA binary into ram. It needs to be an rmdoule so that it can be relocated into ram. agesawrapper_amdinitenv() entry CBFS: 'VBOOT' located CBFS at [10000:cfd40) CBFS: Locating 'AGESA_POST_MEM' CBFS: Found @ offset 875c0 size 11c5e Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes) Loading module at c7580000 with entry c7580000. filesize: 0x2bafc memsize: 0x2bb0d Processing 1112 relocs. Offset value of 0xc7780000 AGESA call 00020001 using c75818fe AGESA call 00020003 using c75818fe Fch OEM config in INIT ENV Done agesawrapper_amdinitenv() returned AGESA_SUCCESS BUG=b:68141063,b:70714803 TEST=Booted kahlee. Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05soc/amd/common: Allow AGESA file split for pre- and post-memoryJustin TerAvest
By splitting the binary files for platform initialization, the post-memory code can be modified to stop executing in place (--xip). This change creates two separate sections in CBFS for AGESA and loads the appropriate file at the correct stage. BUG=b:68141063 TEST=Booted kahlee with split agesa enabled. Change-Id: I2fa423df164037bc3738476fd2a34522df279e34 Signed-off-by: Justin TerAvest <teravest@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-22vendor/intel/skykabylake: Update FSP header files to version 2.9.2Balaji Manigandan B
There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source(s) of PCIe Root Ports. This UPD is used to disable clock source(s) of disabled PCIe Root Port which has active device connected. CQ-DEPEND=CL:*520658,CL:*520659 BUG=b: BRANCH=None TEST= Build and boot soraka Change-Id: Ia4e4d22be8b00a72de68ddde927a090d3441a76e Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Reviewed-on: https://review.coreboot.org/22692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-12-13vc/amd/pi/0067F00: add option to add AGESA binary PI as stageAaron Durbin
Stage addition to CBFS allows relocation to happen on the fly. Take advantage of that by adding AGESA binary PI as a stage file so that each instance will be relocated properly within CBFS. Without this patch Chrome OS having multiple CBFS instances just redirects the AGESA calls back into RO which is inappropriate. BUG=b:65442265,b:68141063 TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and noted each instance in Chrome OS build was relocated. Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-12vc/amd/pi/00670F00: fix #include paths to only use <amdblocks/header.h>Aaron Durbin
Ensure that soc/amd/common/blocks/include is the only #include path for the AMD common code. This removes the duplicate soc/amd/common include as well using the correct #include header in AGESA.c. BUG=b:69262110 Change-Id: I50d85b28514fd905df415f0cc052b9924ee4e741 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-12soc/amd/common: Move Agesa related headersRichard Spiegel
Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11vc/amd/pi/00670F00/binaryPI: cache the AGESA dispatcherAaron Durbin
Instead of repeatedly walking cbfs for the AGESA blob and parsing it cache the resulting dispatcher value. There's only one dispatcher table so use it. The resulting change is that this work is done one time per stage. BUG=b:70401101 TEST=Booted and noted only one lookup per stage. Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22789 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2017-12-09soc/intel/skylake: add acoustic noise mitigation params for FSP 1.1Matt DeVillier
Adapted from Chromium commit d6655eb [Skylake: create UPD Interface for acoustic noise tuning] Add FSP 1.1 params needed for acoustic mitigation on google/caroline (to be upstreamed in a subsequent commit). TEST: build/boot google/caroline Change-Id: Ifb36ecef8c1735c63a5322d952929e9c34cddfb9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-08vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v69_51Ravi Sarawadi
Update FSP header files to match FSP v69_51. UPD updates in FSP v69_51 are: - SGX Epoch - Sub/System Vendor ID - Remove deprecated UPD Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/22391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-08cr50: Make EC clear AP_OFF before hibnernateDaisuke Nojiri
This patch makes AP send EC_REBOOT_HIBERNATE_CLEAR_AP_OFF, which makes EC clear AP_OFF flag then hibernate. This is needed to make Chromebox boot when cr50 toggles the EC's reset line after TURN_UPDATE_ON command. BUG=b:69721737 BRANCH=none CQ-DEPEND=CL:802632 TEST=Verify Fizz reboot after cr50 update. Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-04security/vboot: Guard google_chromeec_reboot by if clauseDaisuke Nojiri
794d222886 "cr50_enable_update: Add printk before EC hibernate" inserted printk and kicked out google_chromeec_reboot from the if-clause. This patch fixes it. BUG=none BRANCH=none TEST=none Change-Id: I058e929e2acd883d2265b2ab019743e3849cb3af Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/22668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22vendorcode/amd/pi/00670F00: Halt build if headers aren't wrappedMartin Roth
Make sure that AGESA headers don't get pulled directly into coreboot files again. BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee; Include AGESA.h into files verify that the build fails. Change-Id: I8d6d94872ebf76a9df2850ed0452cf6b1a446ffd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22vendorcode/amd/pi/00670F00: Remove direct AGESA header includesMartin Roth
Update amdlib to pull in the AGESA headers through agesa_headers.h BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: I3a2a2fde9738a9fe7a0b55cb91c29416cdc227a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21vendorcode/amd/pi/00670F00: Clean up makefileMartin Roth
- Remove unnecessary cflags, exports, and variables - Don't include AGESA cflags in the entire build - Reformat build target BUG=b:69220826 TEST=Build Change-Id: I60cb20a3849439cb808f5d3919588853e9c8c734 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19vendorcode/amd/pi/00670F00: Remove dependency on amd/include dirMartin Roth
Copy the two headers used by the Stoney BinaryPI implementation into the 00670F00 directory so that any changes that are made to them don't affect other platforms. BUG=b:67299330 TEST=Build Change-Id: I5d37fac72871f2617c4be45c151741436cbfce96 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19vendorcode/amd/pi/00670F00: Remove cpuFamilyTranslation.cMartin Roth
The file Proc/CPU/cpuFamilyTranslation.c isn't being included into the build, so it's obviously not needed. BUG=b:69220826 TEST=Build Change-Id: Id244d110b4f15e1d6af6c701f62e2f05d7eb289a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-16vendorcode/amd/pi/00670F00: Get rid of filecodes, replace filecode.hMartin Roth
coreboot doesn't need AGESA's version of Filecode.h. Some of the files that have been copied from AGESA include the header, so we can't get rid of it completely yet. - Remove includes from files that weren't copied from the AGESA source. - Remove FILECODE definitions from coreboot source. BUG=B:69220826 TEST=Build Gardenia; Build & boot Kahlee. Change-Id: If16feafc12dedeb90363826b62ea7513e54277f4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-16vendorcode/amd/pi: Create stoney version of amdlibMartin Roth
Copy the vendorcode/amd/pi/Lib directory into 00670F00 directory and update the 00670F00 Makefile to use it instead of using the common version. This allows changes to stoney without affecting the rest of the AMD binary PI platforms. BUG=b:67299330 TEST=Build Gardenia; Build & boot kahlee Change-Id: I2fe4303f882938e9d917a3001476213f49426455 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-16vendorcode/amd/pi: Split stoney PI into its own MakefileMartin Roth
- Copy vendorcode/amd/pi makefile to 00670F00 directory - Remove all stoney references from the vendorcode/amd/pi makefile - Remove all non-stoney references from 00670F00 Makefile - Remove directories that don't exist from 00670F00 Makefile -- Proc/CPU/Feature -- Proc/Fch/Kern -- Proc/Fch/Kern/KernImc BUG=b:67299330 TEST=Build Gardenia; Build & boot kahlee Change-Id: I34690cfc3b1c4508d25d7cf062fcb9aea5945634 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14AMD Stoney Ridge: Add agesa_headers.hMartin Roth
- Create header files for the stoneyridge PI that pulls in AGESA pi headers and encloses them in #pragma pack push/pop to keep the '#pragma pack(1)' in Porting.h from leaking. - Add that header to agesawrapper.h, replacing AGESA.h and Porting.h Following patches will update the coreboot code to use only agesawrapper.h to pull in the AGESA headers. BUG=b:66818758 TEST=Build tested Change-Id: Ib7d76811c1270ec7ef71266d84f3960919b792d4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11intel/fsp: Update cannonlake FSP headerLijian Zhao
Update cannonlake FSP header to revision 7.x.11.43. Following changes had been made: 1.Remove Minimum control ration from FSPM UPD. 2.Add Intersil VR command option in FSPS UPD. 3.Add minimum and maxiam ring ratio override. TEST=None Change-Id: I63c990e5766370a82dc1c044bcf744612229a605 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11vendorcode/amd/pi/00670f00: Set ModuleIdentifier to be 8 bytesMartin Roth
ModuleIdentifier must be 8 bytes. Every other location else that uses this value explicityly defines it as 8 bytes. If it's initialized here to less than 8 bytes, it gets passed to those other locations with garbage at the end and fails to load the AGESA binary. TEST=Build & boot Kahlee BUG=B:69165234 Change-Id: I11fc90748f49782e2b16ee5326aee17cfe92d0bc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07src: Fix all Siemens copyrightsMario Scheithauer
Some Siemens copyright entries incorrectly contain a dot at the end of the line. This is fixed with this patch. Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-03vendorcode/amd/pi/00670F00: remove unused headersMartin Roth
These header files are not used, so remove them. BUG=b:68812513 TEST=Build Change-Id: Ib43fc544186f7b46ecf9b318b9edcf008f2d08dc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-20cr50_enable_update: Add printk before EC hibernateShelley Chen
Add printout before EC hibernates during a cr50 update to clarify that failure is due to EC rather than cr50. Ran into a situation where DUT shut down during cr50 update and the EC was the culprit. BUG=None BRANCH=None TEST=None Change-Id: I54813fec123de69604d1da4dfc65eaeb77d1662e Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22120 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-20vendorcode/amd/pi/00670F00: Remove S3 restore functionsMartin Roth
These functions are not currently used, and were not in the original AGESA source code drop. The structs involved here were marked "private" in AGESA headerfiles and should not be exposed. They could be handled as anonymous structs and required allocation size is communicated by other means. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: Iec346205470150257fd9d09131d54231b321740b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-19intel/fsp: Update cannonlake FSP headerLijian Zhao
Update cannonlake FSP header file to revision 7.x.15.46. The following item had been updated: 1. Remove/Hide restricted structure. 2. Add EBR as extention of RMT features. 3. Add cpu wakeup timer UPD. 4. Remove XHCI access lock UPD. TEST=NONE Change-Id: I065edbeffdaf555ea7d54ec3fdce56d026789c52 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19src/vendorcode/amd: Use AR variable in MakefilesMartin Roth
Change-Id: I5158f1bcc18eb5b15f310d0cf50fb787c12317c8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-05vendor/intel/skykabylake: Update FSP header files to version 2.7.2Balaji Manigandan B
Update FSP header files to version 2.7.2. New UPDs added FspmUpd.h: *CleanMemory FspsUpd.h: *IslVrCmd *ThreeStrikeCounterDisable Structure member names used to specify memory configuration to MRC have been updated, SoC side romstage code is updated to handle this change. CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592 BUG=b:65499724 BRANCH=None TEST= Build and boot soraka, basic sanity check and suspend resume checks. Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-05AGESA vendorcode: Add ENABLE_MRC_CACHE optionKyösti Mälkki
When selected, try to store and restore memory training results from/to SPI flash. This change only pulls in the required parts from vendorcode for the build. Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-04intel/fsp: Update cannonlake FSP headerLijian Zhao
Update FSP header file to latest version, cannonlake reference code 7.0.14.11. Details of FSP changes can be find in FSP release notes. Change-Id: Iac8db8403b0f909f32049329f867c28c68e3b830 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03vc/amd/pi/00670F00: Remove HeapXXBuffer functionsMartin Roth
The HeapAllocateBuffer and HEAPDeallocateBuffer functions are not used in Stoney Ridge, so get rid of them. Change-Id: I716d5c8957ced52c25fd501697111b1b0b263467 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-03vendorcode/amd/pi: Put libagesa build all in libagesa directoryMartin Roth
Half the files were being placed in build/agesa and half in build/libagesa. Change-Id: Ied69dafffe2eb3354bd430789e098a1cb1d40551 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-28amd/stoneyridge: Drop FieldAcccessorsKyösti Mälkki
It was either SAGE or AMD AES who implemented these for binaryPI, and it is not part of the documented AGESA API. My conclusions of these are: AmdGetValue() returns values from build-time configuration, these may not reflect the actual run-time configuration as there are OEM customization hooks to implement overrides. AmdSetValue() in __PRE_RAM__ will fail, as configuration data is const. Also AmdSetValue() in ramstage may fail, if said configuration data has already been evaluated. Semamtics of these calls are unusable unless one also has access to PI source to make exact decision on when they can be called. Remove these now that stoneyridge does not actually require them. Change-Id: I3379a75ce3b9448c17ef00eb16d3193c296626cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-27soc/amd/stoneyridge: Revert CAR teardown wbinvdMarshall Dawson
Change the cache-as-ram teardown to use invd instead of wbinvd. Save the return and recover the call's return address in chipset_teardown_car. CAR teardown had been modified to use wbinvd to send CAR contents to DRAM backing prior to teardown. This allowed CAR variables, stack, and local variables to be preserved while running the AMD_DISABLE_STACK macro. Using the wbinvd instruction has the side effect of sending all dirty cache contents to DRAM and not only our CAR data. This would likely cause corruption, e.g. during S3 resume. Stoney Ridge now uses a postcar stage and this is no longer a requirement. BUG=b:64768556 Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20967 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-26AGESA: Drop CAR teardown without POSTCAR_STAGEKyösti Mälkki
Except for family15, all AGESA boards have moved away from AGESA_LEGACY_WRAPPER, thus they all have POSTCAR_STAGE now. AGESA family15 boards remain at AGESA_LEGACY=y, but those boards have per-board romstage.c files and are not touched here. Change-Id: If750766cc7a9ecca4641a8f14e1ab15e9abb7ff5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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