Age | Commit message (Collapse) | Author |
|
Remove unused header files in
src/vendorcode/amd/pi/00670F00/agesa_headers.h. This is a first
clean up. Hopefully more headers will be removed in other commits.
Header files cannot be removed at this time. They are used by files in
vendorcode/amd/pi/00670F00/.
BUG=b:77944801
BRANCH=none
TEST=build Gardenia and Grunt
Change-Id: I99b77f6ba41ded30122a01bbe709681312561436
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25644
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove unused AGESA header files from
vendorcode/amd/pi/00670F00/binaryPI/AGESA.c
BUG=b:77905293
BRANCH=none
TEST=build Gardenia.
Change-Id: Ic38424d489dcc37a4074159e33fca0d49c71f701
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The term MTRR has been misspelled in a few places.
Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Header files based on FSP 7.0.25.34
BUG=none
BRANCH=none
TEST=built coreboot without build error.
Change-Id: Id92d99915bda89dd475f393a48adee60bbaee80f
Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com>
Reviewed-on: https://review.coreboot.org/25335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
|
|
This imports common BDK sources that will be used in subsequent
patches.
The BDK is licensed under BSD and will be reduced in size and optimized to
compile under coreboot.
Change-Id: Icb32ee670d9fa9e5c10f9abb298cebf616fa67ad
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
AgesaHeapRebase is an optional callout that allows AGESA to use a
coreboot-managed heap base address. Its internal default location
is determined by AMD_HEAP_START_ADDRESS which is defined as 4 MB.
Add a #define that AGESA may use once the feature is available.
BUG=b:74518368
Change-Id: Id23455779b1c8c4931ad1a3122587e09ad237ecc
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17
Offset 15h Speed report incorrectly issue.
BUG=None
TEST=Boot up with meowth platform and run dmidecode to see two dimm
entries under Type 17.
Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25378
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update FSP header files to match GLK FSP Reference Code Release v2.0.0
Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/25247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Update Cannonlake FSP header to version 7.x.2A.20, the following changes
were made:
1. Add MemtestonWarmBoot option.
2. Add enable8254clockgatingonS3 option.
3. Default disable Tccoffsetlock
BUG=None
TEST=None
Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
AGESA.bin was updated in the binary repo, so update the submodule pointer.
Among other changes, this added a callback "AGESA_HALT_THIS_AP", which
requires updated header files.
BUG=b:70338633
TEST=build kahlee.
Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25183
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update Cannonlake FSP header to revision 7.x.25.31. Following changes
had been made:
1. Add PeciSxRest option.
2. Add Thermal Velocity Boost option.
3. Add VR power deliver design option.
4. Match MrcChannelSts.
TEST=NONE
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6
Reviewed-on: https://review.coreboot.org/23677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The Arch2008 spec describes an AmdS3FinalRestore Entry Point that
coreboot has been missing. Add the helper function that can call
into the blob to execute this.
BUG=b:69614064
Change-Id: Ic72feb0406cd1d0d5c23e391c2464e12c9e10007
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Update the shared AGESA headers to 1.3.0.9.
This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated
to the same version.
BUG=b:72679320
TEST=build and boot Grunt
Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Base patch to create Firmware Version Info (FVI) for CannonLake coreboot
platform using CannonLake FSP new feature.
Expectation is that, FSP will provide version information of all Firmware
ingredient its equip with (i.e. CPU Ref Code, uCode version, MCH Ref Code,
CSE Sku type, CSE version, System Agent Ref Code, OpRom Version, GOP version,
PCH Ref Code version etc.)
Change-Id: Ic388e036709190e8d5c5010f4ea87223291f21d0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Update Cannonlake FSP header to revision 7.x.20.52. Following changes
had been made:
1. Hide internal EV related options.
2. Add GT voltage override options.
3. Add PEG IMR selection.
4. Add PCH DMI ASPM options.
TEST=NONE
Change-Id: If186a1eb440266f1eaeb03505fe0ff4c6a521be6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
This patch ensures MemInfoHob.h file can make use of existing UEFI
headers as is rather than redefining the same structure locally.
TEST=Download BIOS_Version_122.3 from external github and
build MemInfoHob.h without any compilation error.
Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch ensures if required SoC/FSP driver code can retrieve
UDK version for a platform.
Change-Id: I3120ce512255ed6f2a40413e8e6d8000c7285b39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch includes (edk2/UDK2017) all required headers for UDK2017
from EDK2 github project using below command
>> git clone https://github.com/tianocore/edk2.git vUDK2017
commit hash: 66833b2a87d98be8d81d1337c193bcbf0de47d47
Change-Id: If0d5a3fef016c67e9eed6aed9b698b3b13b930c4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: If5a72786d1119908073488c1d6d8787ac0f4f95c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: Id4e05941122c8756f15d5d24482e4cdc04215c55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The HeapAllocateBuffer and HeapDeallocateBuffer functions are not used.
Change-Id: I491a796d87afd0e37051f9caabfff3f70d4d803c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/22069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
With no boards left using AGESA_LEGACY, wipe out remains
of that everywhere in the tree.
Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
* Rename tlcl* to tss* as tpm software stack layer.
* Fix inconsistent naming.
Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: Ie5ff62ee1c7ca193ba841c5b2fb20940ec657625
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Update FSP header files to match FSP v77_12
Following fields have been added in FSP-S UPD:
- SkipPunitInit (Skip P-unit Initialization)
- HgSubSystemId (Sub system Vendor ID VGA)
Change-Id: I6c4c2580b2d0d76038b495be31744c04cc0dc959
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/22820
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Now that the AGESA binary is split into two sections load the
post-memory AGESA binary into ram. It needs to be an rmdoule
so that it can be relocated into ram.
agesawrapper_amdinitenv() entry
CBFS: 'VBOOT' located CBFS at [10000:cfd40)
CBFS: Locating 'AGESA_POST_MEM'
CBFS: Found @ offset 875c0 size 11c5e
Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes)
Loading module at c7580000 with entry c7580000. filesize: 0x2bafc
memsize: 0x2bb0d
Processing 1112 relocs. Offset value of 0xc7780000
AGESA call 00020001 using c75818fe
AGESA call 00020003 using c75818fe
Fch OEM config in INIT ENV Done
agesawrapper_amdinitenv() returned AGESA_SUCCESS
BUG=b:68141063,b:70714803
TEST=Booted kahlee.
Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
By splitting the binary files for platform initialization, the
post-memory code can be modified to stop executing in place (--xip).
This change creates two separate sections in CBFS for AGESA and loads
the appropriate file at the correct stage.
BUG=b:68141063
TEST=Booted kahlee with split agesa enabled.
Change-Id: I2fa423df164037bc3738476fd2a34522df279e34
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to
configure clock source(s) of PCIe Root Ports. This UPD is used
to disable clock source(s) of disabled PCIe Root Port which
has active device connected.
CQ-DEPEND=CL:*520658,CL:*520659
BUG=b:
BRANCH=None
TEST= Build and boot soraka
Change-Id: Ia4e4d22be8b00a72de68ddde927a090d3441a76e
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Reviewed-on: https://review.coreboot.org/22692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Stage addition to CBFS allows relocation to happen on the fly. Take
advantage of that by adding AGESA binary PI as a stage file so that
each instance will be relocated properly within CBFS. Without this
patch Chrome OS having multiple CBFS instances just redirects the
AGESA calls back into RO which is inappropriate.
BUG=b:65442265,b:68141063
TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and
noted each instance in Chrome OS build was relocated.
Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Ensure that soc/amd/common/blocks/include is the only #include
path for the AMD common code. This removes the duplicate soc/amd/common
include as well using the correct #include header in AGESA.c.
BUG=b:69262110
Change-Id: I50d85b28514fd905df415f0cc052b9924ee4e741
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Move AGESA related headers in soc/amd/common to
soc/amd/common/block/include/amdblocks.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, headers moved).
Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Instead of repeatedly walking cbfs for the AGESA blob and parsing it
cache the resulting dispatcher value. There's only one dispatcher table
so use it. The resulting change is that this work is done one time per
stage.
BUG=b:70401101
TEST=Booted and noted only one lookup per stage.
Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22789
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
Adapted from Chromium commit d6655eb
[Skylake: create UPD Interface for acoustic noise tuning]
Add FSP 1.1 params needed for acoustic mitigation on google/caroline
(to be upstreamed in a subsequent commit).
TEST: build/boot google/caroline
Change-Id: Ifb36ecef8c1735c63a5322d952929e9c34cddfb9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Update FSP header files to match FSP v69_51.
UPD updates in FSP v69_51 are:
- SGX Epoch
- Sub/System Vendor ID
- Remove deprecated UPD
Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/22391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This patch makes AP send EC_REBOOT_HIBERNATE_CLEAR_AP_OFF, which makes
EC clear AP_OFF flag then hibernate.
This is needed to make Chromebox boot when cr50 toggles the EC's reset
line after TURN_UPDATE_ON command.
BUG=b:69721737
BRANCH=none
CQ-DEPEND=CL:802632
TEST=Verify Fizz reboot after cr50 update.
Change-Id: I5f590286393ac21382cab64afdccae92d3fc14ba
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
794d222886 "cr50_enable_update: Add printk before EC hibernate"
inserted printk and kicked out google_chromeec_reboot from the
if-clause. This patch fixes it.
BUG=none
BRANCH=none
TEST=none
Change-Id: I058e929e2acd883d2265b2ab019743e3849cb3af
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Make sure that AGESA headers don't get pulled directly into coreboot
files again.
BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee; Include AGESA.h into files
verify that the build fails.
Change-Id: I8d6d94872ebf76a9df2850ed0452cf6b1a446ffd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Update amdlib to pull in the AGESA headers through agesa_headers.h
BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee
Change-Id: I3a2a2fde9738a9fe7a0b55cb91c29416cdc227a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
- Remove unnecessary cflags, exports, and variables
- Don't include AGESA cflags in the entire build
- Reformat build target
BUG=b:69220826
TEST=Build
Change-Id: I60cb20a3849439cb808f5d3919588853e9c8c734
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Copy the two headers used by the Stoney BinaryPI implementation into
the 00670F00 directory so that any changes that are made to them don't
affect other platforms.
BUG=b:67299330
TEST=Build
Change-Id: I5d37fac72871f2617c4be45c151741436cbfce96
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The file Proc/CPU/cpuFamilyTranslation.c isn't being included into
the build, so it's obviously not needed.
BUG=b:69220826
TEST=Build
Change-Id: Id244d110b4f15e1d6af6c701f62e2f05d7eb289a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
coreboot doesn't need AGESA's version of Filecode.h. Some of the files
that have been copied from AGESA include the header, so we can't get rid
of it completely yet.
- Remove includes from files that weren't copied from the AGESA source.
- Remove FILECODE definitions from coreboot source.
BUG=B:69220826
TEST=Build Gardenia; Build & boot Kahlee.
Change-Id: If16feafc12dedeb90363826b62ea7513e54277f4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Copy the vendorcode/amd/pi/Lib directory into 00670F00 directory and
update the 00670F00 Makefile to use it instead of using the common
version.
This allows changes to stoney without affecting the rest of the AMD
binary PI platforms.
BUG=b:67299330
TEST=Build Gardenia; Build & boot kahlee
Change-Id: I2fe4303f882938e9d917a3001476213f49426455
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
- Copy vendorcode/amd/pi makefile to 00670F00 directory
- Remove all stoney references from the vendorcode/amd/pi makefile
- Remove all non-stoney references from 00670F00 Makefile
- Remove directories that don't exist from 00670F00 Makefile
-- Proc/CPU/Feature
-- Proc/Fch/Kern
-- Proc/Fch/Kern/KernImc
BUG=b:67299330
TEST=Build Gardenia; Build & boot kahlee
Change-Id: I34690cfc3b1c4508d25d7cf062fcb9aea5945634
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
- Create header files for the stoneyridge PI that pulls in AGESA pi
headers and encloses them in #pragma pack push/pop to keep the
'#pragma pack(1)' in Porting.h from leaking.
- Add that header to agesawrapper.h, replacing AGESA.h and Porting.h
Following patches will update the coreboot code to use only
agesawrapper.h to pull in the AGESA headers.
BUG=b:66818758
TEST=Build tested
Change-Id: Ib7d76811c1270ec7ef71266d84f3960919b792d4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Update cannonlake FSP header to revision 7.x.11.43. Following changes
had been made:
1.Remove Minimum control ration from FSPM UPD.
2.Add Intersil VR command option in FSPS UPD.
3.Add minimum and maxiam ring ratio override.
TEST=None
Change-Id: I63c990e5766370a82dc1c044bcf744612229a605
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
ModuleIdentifier must be 8 bytes. Every other location else that uses
this value explicityly defines it as 8 bytes. If it's initialized here
to less than 8 bytes, it gets passed to those other locations with
garbage at the end and fails to load the AGESA binary.
TEST=Build & boot Kahlee
BUG=B:69165234
Change-Id: I11fc90748f49782e2b16ee5326aee17cfe92d0bc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Some Siemens copyright entries incorrectly contain a dot at the end of
the line. This is fixed with this patch.
Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
These header files are not used, so remove them.
BUG=b:68812513
TEST=Build
Change-Id: Ib43fc544186f7b46ecf9b318b9edcf008f2d08dc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|