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2015-01-16fmap: Fix pointer related castsFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles Original-Change-Id: I3a747cb562e7390bb81eca874d6c5aaa54b81e6e Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209337 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 5d3aef321a9313719308909ec40fdad0ec631a9f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia8edf54f65947be12a7ae69f6825545fb2aed0f1 Reviewed-on: http://review.coreboot.org/8222 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2015-01-14Revert "vboot2: add verstage"Paul Menzel
This reverts commit 320647abdad1ea6cdceb834933507677020ea388, because it introduced the following regression. $ LANG=C make V=1 Warning: no suitable GCC for arm. Warning: no suitable GCC for aarch64. Warning: no suitable GCC for riscv. /bin/sh: --: invalid option Usage: /bin/sh [GNU long option] [option] ... /bin/sh [GNU long option] [option] script-file ... GNU long options: --debug --debugger --dump-po-strings --dump-strings --help --init-file --login --noediting --noprofile --norc --posix --rcfile --restricted --verbose --version Shell options: -ilrsD or -c command or -O shopt_option (invocation only) -abefhkmnptuvxBCHP or -o option make: -print-libgcc-file-name: Command not found It also introduced trailing whitespace. Change-Id: I50ec00a38e24c854fa926357cd24f9286bf4f66f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8223 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-14vendorcode/amd/agesa: Remove UCODE_VS_FLAG() macro unused variableEdward O'Callaghan
Remove useless AGESA microcode macro that leads to unused variable warnings. Change-Id: Ia21bfc758f81e349bdd0bfd185df75e8b1898336 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/8200 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-01-13vboot2: add verstageDaisuke Nojiri
Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I42b2b3854a24ef6cda2316eb741ca379f41516e0 Reviewed-on: http://review.coreboot.org/8159 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-13vendorcode/intel: remove DebugDeadLoop() from fsptypes.hMartin Roth
When included for the CAR transition, this was causing the error: error: invalid storage class for function 'DebugDeadLoop' Change-Id: Idf37a8104b4468b40c29c8cbe9a40f7a357a4f17 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8193 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03elog: Add function to log boot reason in ChromeOS caseDavid Hendricks
This adds a generic helper function for adding boot reason in the ChromeOS case. If vboot is enabled, it will use information passed in via the vboot handoff table in cbmem to determine mode and reason in the case of recovery. BUG=chromium:373467 BRANCH=nyan TEST=built along with follow-up CL and booted on Big under various modes, verified entry was added to eventlog with "mosys eventlog list" Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I50a7aa6d55eb46413fe9929e732d6eb18c758d4b Original-Reviewed-on: https://chromium-review.googlesource.com/199690 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 961c0bd1dd5512b1c2feb2ed4391bf507900eb7a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6ae4e2a891966d2d1de7d37dcc551383e94e4d75 Reviewed-on: http://review.coreboot.org/7991 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-31vendorcode/amd/cimx/sbX00: Make SBPort.c filename consistentEdward O'Callaghan
Change-Id: I41ba4cffa545a31c1e0845ec44c8a433bda9f99d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7886 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-30chromeos: Unconditionally clear the EC recovery requestSheng-Liang Song
Add the empty weak function clear_recovery_mode_switch(). Problem: If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is set, the following will happen: 1. Boot device in recovery mode with Esc + F3 + Pwr. 2. Turn device off with Pwr button. 3. Turn device on with Pwr button. Device still boots to recovery screen with recovery_reason:0x02 recovery button pressed. If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC isn't set, turning the device off and on again with the Pwr button does a normal boot. Solution: Unconditionally clear the recovery flag. BUG=chromium:279607 BRANCH=TOT TEST=Compile OK. Original-Change-Id: Ie1e3251a6db12e75e385220e9d3791078393b1bf Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197780 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Commit-Queue: Sheng-liang Song <ssl@google.com> Original-Tested-by: Sheng-liang Song <ssl@google.com> (cherry picked from commit 18908bb64cef34ca41812814817ef887961bed34) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I71ca9f3ea8d816c865375ec66a0603ca211f23ae Reviewed-on: http://review.coreboot.org/7895 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-12-30vboot: Convert response_length from uint32_t to size_t in VbExTpmSendReceiveDaisuke Nojiri
Length arguments for VbExTpmSendReceive have type uint32_t but it calls function which expects size_t. This change converts uint32_t to size_t on call and size_t to uint32_t on return. BUG=None BRANCH=None TEST=Booted Nyan Big to Linux Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I1971488baae2d060c0cddec7749461c91602a4f9 Original-Reviewed-on: https://chromium-review.googlesource.com/198016 (cherry picked from commit 6830747eb47568f2a2b494624522d37d8945c030) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I20741759e7bbd60dd7044c532287d6b55047e19a Reviewed-on: http://review.coreboot.org/7894 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30vboot: Add a new post code for TPM failureDuncan Laurie
If the kernel does not properly handle the TPM and send it a TPM_SaveState command before suspend then it will not be in the correct state on resume. In order to easily detect this case add a new post code for TPM failure and use it in the vboot resume path. BUG=chromium:371105 TEST=Build and boot on wtm2. Original-Change-Id: I412520b521387a8e18ad1c6f5a64b39cdd5c88ec Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199371 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit ff2f0dc56c1a783295710f81567af02729fe1da2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I5baf894fd72922acd79d191e5485ae8ef7e0d559 Reviewed-on: http://review.coreboot.org/7936 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-22amd/agesa/f15/Proc/Common/S3SaveState.c: Sync with f15tnEdward O'Callaghan
Change-Id: If46079c1affc7d74767c4215467fd6754b24f20c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7576 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-18AMD Trinity: Update SMU firmware from 10.9 to 10.14Zheng Bao
The first dword in FirmwareTN has been changed from 0xa0009 to 0xa000e. The FirmwareTNHeader is not called by any one in latest PI. It seems to be useless for now. Change-Id: Ic7a20e0bcca8de0b56c7bc5d01e0ce86347bde21 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-12-17chromeos: Add empty functions when CONFIG_CHROMEOS is disabledDuncan Laurie
This allows the chromeos header and functions to be included without needing to guard with #if CONFIG_CHROMEOS. BUG=chrome-os-partner:28234 BRANCH=None TEST=emerge-rambi coreboot Original-Change-Id: I523813dc9521d533242ae2d2bc822eb8b0ffa5e2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196265 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b78ccada9a01f54a60993dfc2c618201d31df9ad) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic2f7127966da716e114336c30829a6403d82e180 Reviewed-on: http://review.coreboot.org/7843 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17chromeos: vboot_loader: Add support for SW_WP_ENABLED flagShawn Nematbakhsh
Set VB_INIT_FLAG_SW_WP_ENABLED according to the status returned by an optional platform / mainboard function vboot_get_sw_write_protect(). BUG=chrome-os-partner:26777 TEST=Manual on Rambi with all patches in sequence: `crossystem sw_wpsw_boot` prints 0 `flashrom --wp-enable` and reboot `crossystem sw_wpsw_boot` prints 1 BRANCH=Rambi Original-Change-Id: Ifb852d75cc106d10120cfee0a396b0662282051a Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190096 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c4668fc8a9ab31d9cf876b3d9ad3405756d4d683) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idace325439958f6b490d2e6705d55e95305c4b2a Reviewed-on: http://review.coreboot.org/7750 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-12-16amd/agesa/f*/Lib/amdlib.c: Integer overflow in loop constructEdward O'Callaghan
As is the case in commit: 3312ed7 amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop construct The semantics of this loop relies on an integer overflow in Index >=0 that implies a return value of (UINT8)-1 which around wraps to 0xFF, or VOLT_UNSUPPORTED. Also fix an infinite loop. Change-Id: Iced3eff3ae7b8935db3bdd6147372cf3b540883c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7676 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-15tegra124: Skip display init when vboot says we don't need it.Gabe Black
If EFS is enabled and vboot didn't tell us it's going to use the display, we can skip initializing it and save some boot time. BUG=chrome-os-partner:27094 TEST=Built and booted on nyan without EFS in recovery mode and normal mode. Built and booted on nyan with EFS in recovery mode and normal mode. Verified that in normal mode with EFS the display initialization was skipped and boot time was essentially the same as when display initialization was simply commented out. BRANCH=None Original-Change-Id: I1e2842b57a38061f40514407c8fab1e38b75be80 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/192544 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a672d18c3570e6991a1c1c0089697112a4cd71d0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I95e8bd7a447876174305f755cc632365ed6f5a30 Reviewed-on: http://review.coreboot.org/7734 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-12vendorcode/amd/pi/00730F01/Lib/amdlib.c: Remove optimize attributeBruce Griffith
Remove '__attribute__((optimize("Os")))' as it is unlikely to be necessary as it is not used in other families that have the same code and only hides deeper issues. Change-Id: Ica890812ebc2fb659b9c3e46b40cf3f6534b3cf2 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/7689 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-10vendorcode/amd/agesa/f16kb/*/PcieComplexDataKB.c: Implicit truncationEdward O'Callaghan
Clang complains: "implicit truncation from 'int' to bitfield changes value from -1 to 15" -1 is define in 'c11std 6.3.1.3p2' as: [Signed and unsigned integers] Otherwise, if the new type is unsigned, the value is converted by repeatedly adding or subtracting one more than the maximum value that can be represented in the new type until the value is in the range of the new type.60) FOOTNOTE.60 The rules describe arithmetic on the mathem... This is "0xFF" on Mullins and "0xF" in this case. Clang seems to complain about this two's complement in a bitfield as being truncated. As the bitfield is 4 bits wide, (a maximum of 15 decimal), we set the field as '0x0F'. Ideally this field /should/ be set to 'UINT8_MAX' however we still have silly truncation warnings. Change-Id: Ib7476d453ffd932bb911e638117cf9f56f71f269 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7719 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-09vboot: allow for non-memory-mapped VBOOT regionsAaron Durbin
Depending on the platform the underlying regions vboot requires may not be accessible through a memory-mapped interface. Allow for non-memory-mapped regions by providing a region request abstraction. There is then only a few touch points in the code to provide compile-time decision making no how to obtain a region. For the vblocks a temporary area is allocated from cbmem. They are then read from the SPI into the temporarily buffer. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built and booted a rambi with vboot verification. Original-Change-Id: I828a7c36387a8eb573c5a0dd020fe9abad03d902 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190924 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit aee0280bbfe110eae88aa297b433c1038c6fe8a3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia020d1eebad753da950342656cd11b84e9a85376 Reviewed-on: http://review.coreboot.org/7709 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-08vendorcode/amd/agesa/fam10: Build as a static libraryEdward O'Callaghan
Following the same reasoning as commit ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I8fbb318daacf64a14a71022705eb040a01c34fa8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7699 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-08vendorcode/amd/agesa/fam15: Build as a static libraryEdward O'Callaghan
Following the same reasoning as commit ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I7798b689db3e582649eb4af4ccd1877bb1d49063 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7698 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-07vendorcode/amd/agesa/f1{5,5tn,6kb}: Silence empty loop warnEdward O'Callaghan
Add decorations to specify that empty loop is intended so. Change-Id: Ia3e40d341eca5e26da3832edc733cf1ccc96c136 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Found-by: Clang Reviewed-on: http://review.coreboot.org/7688 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-07vendorcode/amd/agesa/f15tn/*/F15TnMsrTables.c: Topology Extensions SupportEdward O'Callaghan
Topology Extensions Support (bit 54 of 0xC0011005) applies to PACKAGE_TYPE_FS1r2 also. Rids us of: "Re-enabling disabled Topology Extensions Support" showing up in dmesg. Change-Id: Id123fa9632936c150cf1aebc4d34b404a4398ead Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7671 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-12-06vendorcode/amd/agesa: Remove unused helper.c fileAlexandru Gagniuc
The contents of these files were guarded by a check for the _MSC_VER macro, which we don't use. Change-Id: Ic595c8e6284c54e1449cf21e0cebee8c9ce7c682 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7670 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-06vendorcode/amd/agesa: Make Porting.h common between familiesEdward O'Callaghan
Change-Id: Ica17b2452498f30b710533caf610c9f0c1a0452c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7594 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-12-06vendorcode/amd/agesa/f15tn: Fix GnbIommuScratch in AGESA compilationEdward O'Callaghan
Missing IOMMU support is missing from the libagesa Makefile, it also lacks a header with type-signature and a few bad typecast issues. Change-Id: I7f2ad2104de9baaa66dbb6ffeb0f2b4d35fa5c16 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Co-Author: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/7642 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06vendorcode/amd/agesa/fam15tn: Clean #includes in public headersAlexandru Gagniuc
Right now, coreboot code using AGESA headers can only build if all the AGESA path are given to the compiler via the "-I" option. This is sub- optimal, as it requires us to have every AGESA source directory specified as a compiler include path. This pollutes our global include paths. We restrict the compiler include paths to only allow "AGESA_ROOT/" and "AGESA_ROOT/Include". We then modify the AGESA headers to specify non-local include files relative to "AGESA_ROOT/Include". We use the convention that includes relative to the directory of the header are included as "path/to/header.h", while includes relative to AGESA_ROOT are included as <path/to/header.h>. This change allows building coreboot code based on AGESA with the limited subset of include paths, but does not allow AGESA itself to build with this restricted subset. Change-Id: I31102273c8caa8d6b1d80774bfd35711825bec03 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5424 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-12-05vendorcode/amd/agesa/f15tn: Trim out ASCII art in GnbIommuScratch.cEdward O'Callaghan
TL;DR ASCII art that sucks, remove it. Change-Id: I424736b040fe019bba6155de76903225a266760d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7641 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-04vendorcode/amd/agesa/f*/cpcar.in: Remove non-GCC CAR implementationEdward O'Callaghan
We don't actually use nor support these as our implementation makes use of gcccar.inc. They maybe useful as a reference for history so lets keep them in version history. Change-Id: I388251dead449dde14283e57db39c37982d947b2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7596 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-01Mark non-executable files non-executablePatrick Georgi
No need to mark Makefiles, C files or devicetrees executable. Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-29vendorcode/intel/fsp: Update FSP_VENDORCODE_HEADER_PATHFEI WANG
Minor change in Kconfig to remove "/" defined in FSP_VENDORCODE_HEADER_PATH and update the path in Makefile.inc. Change-Id: Ic19ab9560aabe307d45b560f167874383cc920aa Signed-off-by: Fei Wang <wangfei.jimei@gmail.com> Signed-off-by: FEI WANG <wangfei.jimei@gmail.com> Reviewed-on: http://review.coreboot.org/5894 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-28Use AMD_F15_TN_A0 define in FTnLogicalIdTables.cEdward O'Callaghan
Change-Id: I6b20ded866fa0418bd24ce9eef3775557c2feec7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7562 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-27vendorcode/amd/agesa: Use F15TN AGESA for F15RLEdward O'Callaghan
For the moment we make use of Trinity f15tn AGESA for Richland f15rl support until we have properly worked out the discrepancies. Adds RL-A1 Richland stepping cpuid to F15TnLogicalIdTables lookup. We later wish to merge f15tn and f15rl support into the AGESA in any case. Change-Id: Ia9070d4e392ce7eb912771d1c7b3ef1440f8e8a8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7559 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2014-11-21intel/fsp_baytrail: add Gold3 FSP supportYork Yang
Baytrail Gold3 FSP adds a couple of parameters in UPD_DATA_REGION making platform more configurable via devicetree.cb Update the UPD_DATA_REGION structure and pass settings to FSP Add Baytrail Gold2 and earlier FSP backward compatible, as Gold3 FSP changes UPD_DATA_REGION struct Change-Id: Ia2d2d0595328ac771762a84da40697a3b7e900c6 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/7334 Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
2014-11-20AMD: Isolate AGESA and PI build environments for southbridgeKyösti Mälkki
To backport features introduced with recent Chromebooks and/or Intel boards in general, heavy work on the AMD AGESA platform infrastructure is required. With the AGESA PI available in binary form only, community members have little means to verify, debug and develop for the said platforms. Thus it makes sense to fork the existing agesawrapper interfaces, to give AMD PI platforms a clean and independent sandbox. New directory layout reflects the separation already taken place under 3rdparty/ and vendorcode/. Change-Id: Ia730f0e45e7c1bdfc0c91e95eb6729a77773e2b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7388 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins)
2014-11-20AMD: Isolate AGESA and PI build environmentsKyösti Mälkki
To backport features introduced with recent Chromebooks and/or Intel boards in general, heavy work on the AMD AGESA platform infrastructure is required. With the AGESA PI available in binary form only, community members have little means to verify, debug and develop for the said platforms. Thus it makes sense to fork the existing agesawrapper interfaces, to give AMD PI platforms a clean and independent sandbox. New directory layout reflects the separation already taken place under 3rdparty/ and vendorcode/. Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7149 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Tested-by: build bot (Jenkins)
2014-11-20vendorcode/amd/agesa/f15?tn: Reduce useless differencesSara Lelliott
Reduce inconsequential differences between fam15 and fam15tn to better prepare for possible merger. Change-Id: I016aa1a4cc45553d51190988d48c8a54cfd85f5a Signed-off-by: Sara Lelliott <sara@jupitercrash.org> Reviewed-on: http://review.coreboot.org/7503 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-11-20vendorcode/amd/agesa/f*/Porting.h: Sync files across fam'sEdward O'Callaghan
Sync up these 'Porting.h' headers to include fixes from each family on botched-up typedef's for primitive data types. Fix corresponding breakage introduced by typecasts in mainboards. Change-Id: I003b155cc6c860f6b0cd75667083634a04814473 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7512 Tested-by: build bot (Jenkins)
2014-11-19vendorcode/amd/agesa/f15tn: Fix assembly bugsDamien Zammit
Found missing '$' symbol on variable. Change-Id: I748c315adc44598e16283f8e629be0ecfe9cb6a9 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7514 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19vendorcode/amd/agesa/f15tn: Remove extraneous bracketDamien Zammit
Found an extra bracket that appears it should not be there. Change-Id: I66b7967833afd25f12bd4eaaf6419a6ed3ad544b Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7515 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-15vboot: allow non-relocatable ramstage loadingAaron Durbin
The vboot implementation previously assumed that ramstage would be a relocatable module. Allow for ramstage not being a relocatable module. BUG=chrome-os-partner:27094 BRANCH=None TEST=Built nyan with vboot. Original-Change-Id: Id3544533740d77e2db6be3960bef0c129173bacc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190923 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 756ee3a6987097c65588c8784ee9653fd6e735e4) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I813b07e1bec75640ad4066aca749ba8dccec31d4 Reviewed-on: http://review.coreboot.org/7220 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-15chromeos: provide stub functions for !CONFIG_VBOOT_VERIFY_FIRMWAREAaron Durbin
Instead of checking #if CONFIG_VBOOT_VERIFY_FIRMWARE #else #endif provide empty stub functions for !CONFIG_VBOOT_VERIFY_FIRMWARE. BUG=none BRANCH=baytrail TEST=Built and booted. Original-Change-Id: Id9d1843a0ec47c5a186c9a22ea3e4c13c89ec379 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/184841 (cherry picked from commit f6d95cf4ba6ce1bc0e1df4a0e9f655ad9fea9feb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If35ace863243e36399fc40c2802a2f7f2711e83b Reviewed-on: http://review.coreboot.org/7395 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-13AMD Trinity: Update the Trinity SMU FirmwareZheng Bao
Change-Id: I059047390e80e084f5d7763259d918446d96931e Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7294 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-13vboot: provide empty vboot_verify_firmware()Aaron Durbin
In the case of CONFIG_VBOOT_VERIFY_FIRMWARE not being selected allow for calling vboot_verify_firmware() with an empty implementation. This allows for one not to clutter the source with ifdefs. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built with a !CONFIG_VBOOT_VERIFY_FIRMWARE and non-guarded call to vboot_verify_firmware(). Original-Change-Id: I72af717ede3c5d1db2a1f8e586fefcca82b191d5 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/172711 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit c1e0e5c7b39c947b2a0c237b4678944ab86dd780) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: src/vendorcode/google/chromeos/chromeos.h Change-Id: Iaaa3bedbe8de701726c28412e7eb75de0c58c9c9 Reviewed-on: http://review.coreboot.org/7394 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-11-13vendorcode/amd/agesa/f1{0,2,4,5}: Typo in header guardEdward O'Callaghan
Change-Id: I05d568f27f610c395e2638e79a7fd6646a407955 Found-by: Clang preprocessor wizard powers Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7441 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-11AMD Kabini: Update SMU firmware from 0.4 to 0.9Zheng Bao
Version 0.9 contains a fix for a security issue. A more detailed changelog is not available. Change-Id: I1a66c9da900f89ba9b4c13f3457582278d3793e2 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7293 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2014-11-10AGESA f14: Add "const" modifiersEdward O'Callaghan
Apply commit 283ba78415 to f14 (literally, plus one adaptation). Change-Id: Ieea47470e5852ec8a46596ce23a2d18444618624 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7361 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-04amd/agesa/f16kb: Invalid inline asm in gcc-intrin.hEdward O'Callaghan
Forward port commit: db0e0e2 amd/agesa/*/gcc-intrin.h: Invaild inline asm Change-Id: Ia857f76d3782aea07e09df1352eeb286e40b2689 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7302 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-03AGESA f12: Add "const" modifiersPatrick Georgi
Apply commit 283ba78415 to f12 (literally, plus one adaptation). Change-Id: Ied7891806e269320caf968cae3de3dc792c5f8fd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7312 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 18:21:36 +0000