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2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profileMike Banon
The ability to set up a custom memory profile is useful if you don't like the XMP memory profiles (if they exist) of your RAM sticks, or want to try some overclocking. Read SPD data will be overriden by your custom values. Tested on Crucial BLT8G3D1869DT1TX0 (1866MHz 9-9-9-27). Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-02vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profilesMike Banon
Add XMP memory profiles support that has been tested on f15tn (A88XM-E) and f16kb (AM1I-A) with two Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40488 Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341Tan, Lean Sheng
The FSP-M/S/T related headers added are generated as per FSP v2341. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I98f738402490b47efa1a346f81db47857e384e13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-02vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04Ronak Kanabar
The headers added are generated as per FSP v2385_04. Previous FSP version was 2385_02. Changes Include: - add FastPkgCRampDisable, SlowSlewRate, PreWake, RampUp and RampDown UPDs in Fsps.h BUG=b:174330941 BRANCH=dedede TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3438485 Change-Id: I477af05c34f767a43990670a711992641eaf6000 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47862 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-26vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1483_11Subrata Banik
List of changes: 1. FSP-M Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace32 -> UnusedUpdSpace29 2. FSP-S Header: - Rename UPD Offset UnusedUpdSpace46 -> UnusedUpdSpace44 Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47901 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22vendorcode/eltan/security: Add dependency for menu itemsFrans Hendriks
Subitem for VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT are always displayed. Add dependency and display these items when feature is enabled only. Tested on Facebook FBG1701. Change-Id: I51e47efddbcf51d87439bec33b85432da56fa4c6 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22cpu/amd/pi: Remove unused cpu code 00660F01Martin Roth
Remove the processor directory and references to the Kconfig symbol. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I403a453362fd76d6ef2a5b75728a362efa4f2491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFSFurquan Shaikh
If AGESA is added as a raw binary (and not a stage), then cbfstool does not perform relocation. In this case, it should be added only to COREBOOT (i.e. default) CBFS since the binary needs to be present only in one specific location that is present in the default CBFS. Change-Id: I7a7edc217663f9d1d36b05308bbd35f56a28b9b1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-21vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1474_11Subrata Banik
List of changes: 1. FSP-M Header: - Rename UPD Offset UnusedUpdSpace33 -> UnusedUpdSpace32 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-20vc/intel/fsp2/denverton_ns: Remove unused filesFelix Singer
The Denverton-NS SoC uses the header files from the FSP git repository. Therefore, remove these from coreboot source. Change-Id: Ib22d3f5e5ce83eb83bf589ea8bba7b55ebe44ea8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47754 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20vc/google/chromeos/sar: Make "SAR not found" log a debug messageMaulik V Vaghela
coreboot might not store wifi SAR values in VPD and may store it in CBFS. Logging the message with 'error' severity may interfere with automated test tool. Lowering severity to BIOS_DEBUG avoids this issue. BUG=b:171931401 BRANCH=None TEST=Severity of message is reduced and we don't see it as an error Change-Id: I5c122a57cfe92b27e0291933618ca13d8e1889ba Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-20vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field inTim Chu
SystemMemoryMapHob This field from SystemMemoryMapHob can be used to define error correction type in SMBIOS type 16. Tested=On OCP Delta Lake, the value is expected. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/47505 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_02Ronak Kanabar
The headers added are generated as per FSP v2385_02. Previous FSP version was 2376. Changes Include: - add VtdIopEnable, VtdIgdEnable, and VtdIpuEnable UPDs in Fspm.h TEST=Build and boot JSLRVP Change-Id: I268eca1bcbbf26d4dc4ecf54d432cdb6ad49b4eb Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47500 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19ACPI S3: Replace acpi_is_wakeup()Kyösti Mälkki
It was supposed to return true for both S2 and S3, but level S2 was never stored in acpi_slp_type or otherwise implemented. Change-Id: Ida0165e647545069c0d42d38b9f45a95e78dacbe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW45 FSP Memory map HOB mismatchJohnny Lin
Tested=On OCP Delta Lake, verify the memory map hob data are correct. Change-Id: I86bd809e21270395c4115788e5521606e9dcc2fb Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-15vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 3444. Previous version was 3425. BUG=b:173160613 BRANCH=none TEST=build and boot delbin Cq-Depend:chrome-internal:3403586, chrome-internal:3403392 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47555 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454Subrata Banik
List of changes: 1. FSP-M Header: - Add new UPD Lp5CccConfig - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx, PsOnEnable, RpPtmBytes, PmSupport, GtFreqMax, Hwp, TccActivationOffset, Cx, PchLockDownGlobalSmi, PcieRpLtrMaxSnoopLatency, PcieRpLtrMaxNoSnoopLatency, UnusedUpdSpace45 Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47244 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07vc/intel/FSP2_0/CPX-SP: update to ww45 release and add watermark optionJonathan Zhang
Intel CPX-SP FSP ww45 release annotates default values for FSP-M UPD variables. FSPM MemRefreshWatermark option support is present in FB's CPX-SP FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP FSP binary, this option takes the space of UnusedUpdSpace0[0]. For DeltaLake mainboard, if corresponding VPD variable is set, use it to control the behavior. Such control is effective when FB's CPX-SP FSP binary is used. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-06soc/amd/picasso: Update coreboot UPD variable names to include unitsZheng Bao
Use command below to change the variable globally. sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \ --exclude-dir=build --exclude-dir=crossgcc` BUG=b:171334623 TEST=Build Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-02vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 3425. Previous version was 3373. BUG=b:172045149 BRANCH=none TEST=build and boot delbin Cq-Depend:chrome-internal:3373431 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47041 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30vc/amd/fsp: Update bl_errorcodes_public.hMartin Roth
Replace the initial bl_errorcodes_public.h (a temporary, minimal version) with the full version released by AMD. BUG=None TEST=Build BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-25vc/intel/fsp/fsp2_0/adl: Update FSP header file version to 1432Subrata Banik
List of changes: 1. FSP-M Header: - Add new UPD GpioOverride - Change help text for PlatformDebugConsent UPD - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust Reservedxx UPD Offset - PcieRpLtrMaxSnoopLatency and PcieRpLtrMaxNoSnoopLatency array grew by 4 elements Change-Id: I54aabd759b99df792b224f91ce94927275dd9b80 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46695 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23vc/amd/fsp/picasso: Remove typedefs in bl_syscall_public.hJason Glenesk
Remove all typedefs and cleanup references to all structs and enums. BUG=b:159061802 TEST=Boot morphius to shell. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-19volteer+vendorcode: Retrieve Cr50 version only via SPIJes Klinke
No recent Chromebooks have used I2C for TPM communication, and as a result, a bug has crept in. The ability to extract Cr50 firmware string is only supported via SPI, yet code in mainboard and vendorcode attempt to do so unconditionally. This CL makes it such that the code also compiles for future designs using I2C. (Whether we want to enhance the I2C protocol to be able to provide the version string, and then implement the support is a separate question.) This effort is prompted by the desire to use reworked Volteer EVT devices for validating the new Ti50/Dauntless TPM. Dauntless will primarily be using I2C in upcoming designs. BRANCH=volteer TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-10-19vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376Ronak Kanabar
The headers added are generated as per FSP v2376. Previous FSP version was 2295. Changes Include: - add GpioOverride UPD in Fspm.h - add new header FirmwareVersionInfo.h Cq-Depend: TBD Change-Id: I65c03d8eda11664541479983c7be11854410e1c6 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45899 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-17vendorcode/amd: Fix typo in *is defined* in commentsPaul Menzel
The passive clause is constructed with the past participle, which is *defined* in this case. Fix all occurrences in AMD vendor code with the command below. $ git grep -l "is define at" src/vendorcode/amd/ | xargs sed -i 's/is define at/is defined at/' Change-Id: Ia26c87aecb484dcb55737e417367757d38ce3b56 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-17vc/amd/Kconfig: Add missing dot in AMD domain www.amd.comPaul Menzel
Fixes: b266c6b5 ("AMD Steppe Eagle: Add binary PI vendorcode files") Change-Id: Id317b53cfafaae629c2a94144c419e2112eaf7a9 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-14vc/intel/fsp/fsp2_0/adl: Update FSP header to version 1332.01Subrata Banik
List of changes: - Add FSP-M UPD 'TmeEnable' TEST=Build and boot ADLRVP platform. Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46295 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-13vendorcode/google/dram_part_num: Lower the severity of debug statementKarthikeyan Ramasubramanian
DRAM part number may not be provisioned in CBI during early stages of development. Logging the debug statement with error severity interferes with some of the test tools. Lower the severity of debug statement to BIOS_DEBUG. BUG=b:170529094 TEST=Build and boot to ChromeOS in Drawlat. Change-Id: Ib0c707ec6478060d6e18ea01cc467dfda00a6d42 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46299 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 3373. Previous version was 3333. Changes include below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable BUG=b:169759177 BRANCH=none TEST=build and boot delbin/tglrvp Cq-Depend:chrome-internal:3308203, chrome-internal:3308204 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45630 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fieldsJohnny Lin
The fields from SystemMemoryMapHob can be used to generate SMBIOS type 17. Tested=On OCP Delta Lake, verify the values are expected. Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45797 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 releaseJonathan Zhang
Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter, and adds some fields to HOBs. Update FspmUpd.h and HOB header files. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45940 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-07vc/amd/fsp: Update the svc call header for the Mod Exp SVCMartin Roth
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp svc call. BUG=b:169157796 TEST=Build BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I1ce69c80cec77e1692cf9713a739cc4da4677da6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45942 Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05vendorcode/google: add CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig optionNick Vaccaro
Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option to declare whether the SPD Module Part Number (memory part name) is stored in the CBI. Move mainboard_get_dram_part_num() into src/vendor/google/chromeos to allow mainboards to use it without having to duplicate that code by enabling the CHROMEOS_DRAM_PART_NUMBER_IN_CBI config option. BUG=b:169789558, b:168724473 TEST="emerge-volteer coreboot && emerge-hatch coreboot && emerge-dedede coreboot && emerge-nocturne coreboot" and verify it builds. Change-Id: I0d393efd0fc731daa70d3990e5b69865be99b78b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-01vc/amd/fsp/picasso: Add bit definitions for PSP info in transfer blockMartin Roth
BUG=b:168895748 TEST=None BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I299fdd0f007f7e4a8f597931a52f68dc98acc9ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45804 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28vc/intel/fsp/fsp2_0/CPX-SP: upgrade to ww38 FSP releaseJonathan Zhang
Intel CPX-SP FSP ww38 release made some changes to FSP-M header file. Those changes do not need corresponding soc code change. TESTED=built image with ww38 FSP RELEASE binary, booted DeltaLake DVT to target OS. Change-Id: I320c4a674f9f4d37c30ce6df510f18ad1ae057eb Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-25vc/amd/fsp/picasso: Update to UPD 1.0.1.3Raul E Rangel
This adds eMMC preset settings. It also fixes some formatting and a comment. BUG=b:159823235 TEST=Build test Cq-Depend: chrome-internal:3251807 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic5caff594157e03d792b999ca60274cf53c708e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45096 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15chromeos: Provide common watchdog reboot support in romstageRavi Kumar Bokka
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I2a1f1411e9d58a0738e0e8057f5b1ad049bf03e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45213 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14src/vendorcode/intel/fsp/fsp2_0/cpx-sp: add prev boot error info HOB header fileJonathan Zhang
PREV_BOOT_ERR_SRC_HOB is generated by CPX-SP FSP by interrogating error status registered (such as MCA MSRs) to list fatal errors happened during the previous boot session. The header file supports 3 different error source types. CPX-SP FSP supports only McBankType. Change-Id: I9b88af17075b98e88c7e94e55fea37627ec03cd0 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44973 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11vc/amd/fsp/picasso: Fix FSP-S UPD header file formattingFelix Held
Use one tab instead of 8 spaces at the beginning of the lines added in commit 39a8040ddc551306d823d52a459fdb5dd717b2fe. Change-Id: I8d7553e1b41dbbbdabd7392028a51e3a0f79c97a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-10vc/amd/fsp/picasso: Sync FSP-S UPD header fileMarshall Dawson
Sync the UPD definitions with the latest auto-generated files. Definitions and usage will be updated in a subsequent FSP Integration Guide. Cq-Depend: chrome-internal:3247431 BUG=b:167421913, b:166519072, b:159664044 TEST=Boot morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic85e1f457c8932d933d8645738de68319dbf375a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-09-10vendorcode/intel/fsp/alderlake: Fix FSPS_ARCH_UPD redefinition issueSubrata Banik
FSPS_ARCH_UPD struct is part of edk2-stable202005 branch (FspApi.h) hence local definition of FSPS_ARCH_UPD inside FspsUpd.h is causing compilation issue. Change-Id: Id5b3637d9ab6d87aab6da810f9c83d3258900a29 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-09vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332Subrata Banik
List of changes: 1. Select FSP_HEADER_PATH 2. Select FSP_FD_PATH 3. Select PLATFORM_USES_FSP2_2 4. Select UDK_202005_BINDING Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-08vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM definition in SystemMemoryMapHobJohnny Lin
Most of them are needed for SMBIOS type 17 creation. Tested=With FSP WW36 verified the printed hob values match with FSP hob data. Change-Id: I02f4600f1be39e2576d7c84a5a6b6672ebb7034b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08vendorcode/intel/FSP2_0/CPX-SP: update to ww36Jonathan Zhang
Intel CPX-SP FSP ww36 release has following changes: * Update FSP header version to change among FSP releases. * Add SPDRegVen field in memory map HOB, to facilitate SMBIOS type 11 (OEM strings) generation. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45100 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08vendorcode/intel/fsp/fsp2_0/cpx_sp: Set correct stack number for IOU3Johnny Lin
PSTACK2 (IOU3) should be stack number 4, mainboard uses stack number as the index to access the bus number array read by get_stack_busnos(). Without the fix it would get the wrong bus number (0xb1). Tested=On OCP Delta Lake, dmidecode -t 9 to verify slots bus number on IOU3 are correct (0xb2). Change-Id: I1c9e49bbc9a00de82d1fc67b3b4ed47e03eacdda Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3333Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3333. Previous version was 3313. Changes Include: 1. Update comments 2. Add new UPD for Gpio Override support BUG=b:166790597 BRANCH=none TEST=build and boot volteer proto2 Cq-Depend:chromium-internal:3240396,chromium-internal:2870145 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie3f0688143eef532946c7a2141909c1ac173fc2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44912 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-01{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 23:01:22 +0000