summaryrefslogtreecommitdiff
path: root/src/vendorcode
AgeCommit message (Collapse)Author
2013-12-21chromeos: Check for recovery reason code in shared dataDuncan Laurie
When using RW firmware path the proper recovery reason can be retrieved from the shared data region. This will result in the actual reason being logged instead of the default "recovery button pressed" reason. 1) build and boot on falco 2) crossystem recovery_request=193 3) reboot into recovery mode, check reason with <TAB> 4) reboot back into chromeos 5) check event log entry for previous recovery mode: 25 | 2013-07-15 10:34:23 | Chrome OS Recovery Mode | Test from User Mode Change-Id: I6f9dfed501f06881e9cf4392724ad28b97521305 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61906 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4368 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-07Correct file permissions.Idwer Vollering
Some files have incorrect/odd permissions, correct them: remove unnecessary +x flags. Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4490 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07src/vendorcode/amd: remove Visual Studio remnants.Idwer Vollering
Delete files that (were overlooked and) are probably needed to build with Visual Studio. Remove doxygen helper files as well. Change-Id: I6b6cece178917ad9da1081eb6b1bb9be33066a77 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4489 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-05AMD IMC AGESA: Access the data in stack by correct lengthZheng Bao
The bug is hard to find. We were adding the feature of fan control. We met some strange things which could not be explained. Like, sometimes adding printk let the error disappear. Then we traced the code by hardware debug tool (HDT). It turned out the data in stack was overwritten. The values of AccessWidthxx are { AccessWidth8 = 1, AccessWidth16, AccessWidth32,} For the case of AccessWidth8, we only need to access the index/data once. But ReadECmsg and WriteECmsg did the loop twice, 1 more time than they are supposed to do. The data in stack next to "Value" would be overwritten. For all the cases, the code should be OpFlag = OpFlag & 0x7f; switch (OpFlag) { case 1: /* AccessWidth8 */ OpFlag = 0;break; case 2: /* AccessWidth16 */ OpFlag = 1;break; case 3: /* AccessWidth32 */ OpFlag = 3;break; case 4: /* AccessWidth64 */ OpFlag = 7;break; default: error; } Actually, the caller only takes AccessWidth8 as the parameter. We can ignore other cases for now. That is an AGESA bug. AMD's AGESA team own this code. They have given the response that they are going to update this in next release. I presume let them decide the proper way to fix that. Before that, I change the code as little as possible to make it run without crash. Change-Id: I566f74c242ce93f4569eedf69ca07d2fb7fb368d Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/4297 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2013-12-04Add Intel FSP northbridge support Sandybridge and IvybridgeMarc Jones
Add support for Sandybridge and Ivybridge using the Intel FSP. The FSP is different enough to warrant its own source files. This source handle the majority of FSP interaction. "Intel® Firmware Support Package (Intel® FSP) provides key programming information for initializing Intel® silicon and can be easily integrated into a boot loader of the developer’s choice. It is easy to adopt, scalable to design, reduces time-to-market, and is economical to build." http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html Change-Id: Ib879c6b0fbf2eb1cbf929a87f592df29ac48bcc5 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4015 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-03vboot: use out_flags to indicate recovery modeDuncan Laurie
In order to make the proper decision on loading the option rom or not the recovery mode setting needs to be known. Normally this is detected by asking the EC, but if recovery is requested with crossystem then the EC does not know about it. Instead we need to check the output flags from VbInit(). Change-Id: I09358e6fd979b4af6b37a13115ac34db3d98b09d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57474 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4223 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-12-03vboot: Do not pass OPROM_MATTERS flag to VbInitDuncan Laurie
Since we are using VBNV to determine if developer mode is active we do not need the messy OPROM hook magic any longer. Change-Id: I1b9effef3ef2aa84e916060d8e61ee42515a2b7c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57473 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4222 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02Add option to disable ChromeOSKyösti Mälkki
Those building Chromebook firmware from coreboot git might be more interested in building without ChromeOS extras. Change-Id: I2f176d059fd45bf4eb02cc0f3f1dcc353095d0ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3977 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-02vboot: use out_flags to indicate dev modeAaron Durbin
In order to make the proper decision on loading the option rom or not the developer mode setting needs to be known. Under early firmware selection it is possible to know the state of developer mode by a flag in out flags. Use this flag when early firmware selection is being employed to determine if developer mode is enabled or not. Change-Id: I9c226d368e92ddf8f14ce4dcde00da144de2a5f3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57380 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4218 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25slippy: Minor vboot related fixesDuncan Laurie
- Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4169 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Honor vboot's request to load the VGA option ROMBill Richardson
This removes an earlier patch that caused the VGA option ROM to be loaded by coreboot even in normal mode when it isn't needed. Change-Id: Ie0a331a10fff212a2394e7234a0dbb37570607b7 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48173 Commit-Queue: Stefan Reinauer <reinauer@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4125 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24Fix compile error in chromeos by adding stddef.hDuncan Laurie
Compile was failing with the following error: In file included from src/vendorcode/google/chromeos/vboot_handoff.h:22:0, from src/vendorcode/google/chromeos/chromeos.c:22: vboot_reference/firmware/include/vboot_api.h:388:18: error: unknown type name 'size_t' src/vendorcode/google/chromeos/chromeos.c: In function 'vboot_get_payload': src/vendorcode/google/chromeos/chromeos.c:50:23: error: 'NULL' undeclared (first use in this function) Change-Id: I13f9e41ef6a4151dc65a49eacfa0574083f72978 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48289 Reviewed-on: http://review.coreboot.org/4131 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-15vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7WANG Siyuan
The platform initialization (PI) code v1.0.0.7 for Kabini has some enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH bug fix (RTC) and so on. Use the name Kabini instead of Kerala everywhere. Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0 as used in `AGESA_VERSION_STRING`. Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3935 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-10-13Rename cpu/x86/car.h to arch/early_variables.hStefan Reinauer
and add an ARMv7 version. Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156 Signed-off-by: Stefan Reinauer <reinauer@google.com> [km: rebased fa004acf8 from chromium git] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3939 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2013-09-24southbridge/cimx/sb900: Rename headers to match sb700 & sb800Corey Osgood
Northbridge code includes these headers, so they all need to have the same name to allow different combinations of northbridge and southbridge. This changes the sb900 names to match sb700 & sb800, and points agesa/family12 and amd/torpedo to the new file names. Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Reviewed-on: http://review.coreboot.org/3825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-27AMD f16kb: use AZ_PIN in Kconfig to customize AZALIA_PIN in YangtzeWANG Siyuan
src/southbridge/amd/agesa/hudson/Kconfig config default value, mainboard Kconfig config value for specific mainboard. bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3 Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3879 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-16Correct spelling of shadow, setting and memoryPaul Menzel
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3768 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15CBFS: Change the signature of cbfs_decompress.Gabe Black
Instead of returning 0 on success and -1 on error, return the decompressed size of the data on success and 0 on error. The decompressed size is useful information to have that was being thrown away in that function. Change-Id: If787201aa61456b1e47feaf3a0071c753fa299a3 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3578 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-06AMD AGESA: Fix comment for `PCIE_DDI_DATA_INITIALIZER`Paul Menzel
Copied from a similar commit for Family 10h AGESA [1] Remove the fourth argument in the comments. Luckily the compiler, at least gcc, warns about a wrong number of arguments, and therefore no incorrect code resulted from the wrong documentation. [1] 07e0f1b AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments [2] fc47bfa Revert "AMD f14 vendorcode: Fix warning" Change-Id: I3806e368a823e4a40d22e99b91bf3598d9ed2f15 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3840 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD AGESA: Add missing breaks to switch statement in one fileBruce Griffith
This is the same patch as an earlier one applied to family 15 [1]. Static analysis often flags case statements that do not include a terminating "break;" statement. Eclipse's CODAN is an example of this. This changelist modifies amdlib.c to terminate case statements with "break;". [1] e44a89f amd/agesa/f15/Lib/amdlib.c: Add missing breaks ... Change-Id: Ibd1ae6f2b52fde07de3d978d174975f4d93647ab Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3839 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06AMD Kabini: Add "const" modifier to AGESA function parametersBruce Griffith
Add CONST modifiers to read-only pass-by-reference function parameters in AGESA. This allows the use of "const" modifiers on the declaration of lookup tables that are pass-by-reference. These will be used to identify tables that are copied onto the HEAP but don't need to be. This same change was made for AMD Trinity APUs (Family15tn) [1]. [1] 283ba78 AGESA: Add "const" modifier to function parameters Change-Id: I2bdd9fc5e027e938de9df0f923b95da934bb48dc Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3837 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-08-05AMD SATA: Correct "them implement" to "then implement" in commentsPaul Menzel
This changelist was cherry-picked from merged community code for Parmer [1] and the paths modified so that the Parmer modification is applied against Olive Hill. [1] 0086162 AMD SATA: Correct _them implement_ ... in comments Change-Id: I9849e9a75dacfde15331c4200d72343a59036f14 Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3841 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-04AMD Kabini: Add AGESA/PI code for new processor familySiyuan Wang
Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Nick Dill <nick.dill@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3836 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-06-28amd/agesa/f15/Lib/amdlib.c: Add missing breaks to switch statementBruce Griffith
Static analysis often flags case statements that do not include a terminating "break;" statement. Eclipse's CODAN is an example of this. This changelist modifies amdlib.c to terminate case statements with "break;". Change-Id: I3d43acaf64e2e2d9717421cb547fec35e582cf8b Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3539 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28amd/agesa/f15/Proc/CPU: Add length modifier to eliminate compiler warningsBruce Griffith
This change adds length modifiers to constant values to eliminate compiler warning messages. Change-Id: I032cb37cec788e2b5f79f5bbf9efc19a7892dc14 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3538 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28vendorcode/amd/agesa/f15: Eliminate compiler warningsBruce Griffith
This change is mostly type casts to eliminate compile time warnings. These specific changes are mostly cherry-picked from AMD Family 14 code and, as such, contain artifacts copied over from F14. For example, there are a number of UINT64 casts that are commented out rather than removed. This is to maintain consistency between AGESA versions. Ultimately, this is in preparation for turning on warnings as errors for AMD Family 15 server parts. Change-Id: Ic73d0b6ebab18d97015a9dd1130aff4e5e432fb7 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3525 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-09fam15 vendorcode: Change license to BSD from AMD software licenseSiyuan Wang
fam15 vendorcode (src/vendorcode/amd/agesa/f15tn) was licensed under the AMD software license agreement. Change this license to 3-clause BSD. Change-Id: I7cab09bb58ef7cd24602628e2278672d577214a2 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3414 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-06AGESA: Add "const" modifier to function parametersBruce Griffith
Add CONST modifiers to read-only pass-by-reference function parameters in AGESA. This allows the use of "const" modifiers on the declaration of lookup tables that are pass-by-reference. These will be used to identify tables that are copied onto the HEAP but don't need to be. Change-Id: Ie1187a427804fddf47b935a110ad23931a3447a9 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16chromeos: use cache-as-ram migration API for vbnvAaron Durbin
It's possible that the vbnv global variables may be accessed in romstage after cache-as-ram is torn down. Therefore use the cache-as-ram migration API. Wrappers were written to wrap the API to keep the existing code as close as possible. Change-Id: Ia1d8932f98e00def0a44444a1ead0018a59d3d98 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3234 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-14EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1.Ronald G. Minnich
build-snow got broken when the snow makefile improved. So fix it. While we're at it, create a script like the update-microcode scripts that gets the bl1. I thought about making this a common script but the various names and paths always evolve, leaving me thinking it's not worth it. This script is just a piece of the snow build script. Change-Id: I65c0f8697a978c62fe12533c4f0152d14dbaefda Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3238 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-05-04AMD F15: Fix warning in Proc/CPU/FeatureMartin Roth
Fix Warning: cpuFeatureLeveling.c:265, GNU Compiler 4 (gcc), Priority: Normal cast to pointer from integer of different size [-Wint-to-pointer-cast] with an intermediate cast to (intptr_t) Change-Id: I3bfd2ea1e797632316675338789dabef8f73ba64 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3126 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-04AMD F15: Fix warnings in Proc/CommonMartin Roth
This fixes 3 warnings in the Proc/Common directory: AmdS3Save.c:250, GNU Compiler 4 (gcc), Priority: Normal AmdS3LateRestore.c:123, GNU Compiler 4 (gcc), Priority: Normal cast from pointer to integer of different size [-Wpointer-to-int-cast] Fixed with a second cast to (intptr_t) AmdInitReset.c:153, GNU Compiler 4 (gcc), Priority: Normal statement with no effect [-Wunused-value] Fixed by commenting the line out as it is in the other families code. Change-Id: Ib35ec466671712af01568b7c2a18ee138fe883c0 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3125 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-03AMD SATA: Correct »them implement« to »then implement« in commentsPaul Menzel
The following command was used to correct all occurences of this typo. $ git grep -l "them implem" | xargs sed -i 's/them implem/then implem/' Change-Id: Iebd4635867d67861aaf4d4d64ca8a67e87833f38 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3145 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-20Eliminate use of pointers in coreboot tableStefan Reinauer
Because pointers can be 32bit or 64bit big, using them in the coreboot table requires the OS and the firmware to operate in the same mode which is not always the case. Hence, use 64bit for all pointers stored in the coreboot table. Guess we'll have to fix this up once we port to the first 128bit machines. Change-Id: I46fc1dad530e5230986f7aa5740595428ede4f93 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3115 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-04-16AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in commentsPaul Menzel
When looking into possible reasons for a proposed revert [1], I noticed that the comments use four arguments for `PCIE_DDI_DATA_INITIALIZER`, but the actual definition only uses three. $ git grep -A1 PCIE_DDI_DATA_INITIALIZER # manually squeeze whitespace in output […] -- src/vendorcode/amd/agesa/f10/AGESA.h:#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ src/vendorcode/amd/agesa/f10/AGESA.h-{mConnectorType, mAuxIndex, mHpdIndex} -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * }, -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * } -- […] So remove the fourth argument in the comments. Luckily the compiler, at least gcc, warns about a wrong number of arguments, and therefore no incorrect code resulted from the wrong documentation. [1] http://review.coreboot.org/#/c/3077/ Change-Id: I3e5a02c66a23af1eb2d86be8dbc7aaa3e5cea05e Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-14AMD CIMx sb800/SATA.c, sb900/Sata.c: Fix R*AI*D typo in commentsPaul Menzel
Spell RAID correctly in comments. Found with the following command. $ git grep -i riad Change-Id: I68e8476d885a88df589d25f88cc158d71eb04e07 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-01chromeos: honor MOCK_TPM=1Aaron Durbin
The TPM code wasn't previously honoring MOCK_TPM=1. Because of this, boards with TPMs that didn't handle S3 resume properly would cause a hard reset. Allow one to build with MOCK_TPM=1 on the command line so that S3 can still work. Change-Id: I9adf06647de285c0b0a3203d8897be90d7783a1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2976 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-29chromeos: remove CACHE_ROM automatic selectionAaron Durbin
It's not appropriate for the chromeos Kconfig to automatically select CACHE_ROM. The reason is that enabling CACHE_ROM is dependent on the board and chipset atrributes. Change-Id: I47429f1cceefd40226c4b943215d627a3c869c7b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-23vboot module: fix compilation issuesAaron Durbin
There were 3 things stopping the vboot module from being compiled: 1. The vboot_reference code removed in the firmware/arch/$(ARCH)/include directory. This caused romcc to fail because romcc fails if -I<dir> points to non-existent directory. 2. The rmodule API does not have the no-clearing-of-bss variant of the load function. 3. cbfs API changes. Change-Id: I1e1296c71c5831d56fc9acfaa578c84a948b4ced Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-22Unify coreboot table generationStefan Reinauer
coreboot tables are, unlike general system tables, a platform independent concept. Hence, use the same code for coreboot table generation on all platforms. lib/coreboot_tables.c is based on the x86 version of the file, because some important fixes were missed on the ARMv7 version lately. Change-Id: Icc38baf609f10536a320d21ac64408bef44bb77d Signed-off-by: Stefan Reinauer <reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/2863 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2013-03-22vboot: pass correct coreboot include pathsAaron Durbin
The coreboot include were not being passed correctly when building vboot_reference. The paths being included were of the src/<dir> form. However, vboot_reference lives in src/../vboot_reference. That coupled with the recursive make call made vboot_reference not see coreboot's header files. Fix this by appending ../ to coreboot's default include paths. Change-Id: I73949c6f854ecfce77ac36bb995918d51f91445e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2860 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22coreboot: add vboot_handoff to coreboot tablesAaron Durbin
The vboot_handoff structure contians the VbInitParams as well as the shared vboot data. In order for the boot loader to find it, the structure address and size needs to be obtained from the coreboot tables. Change-Id: I6573d479009ccbf373a7325f861bebe8dc9f5cf8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2857 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22romstage: add support for vboot firmware selectionAaron Durbin
This patch implements support for vboot firmware selection. The vboot support is comprised of the following pieces: 1. vboot_loader.c - this file contains the entry point, vboot_verify_firmware(), for romstage to call in order to perform vboot selection. The loader sets up all the data for the wrapper to use. 2. vboot_wrapper.c - this file contains the implementation calling the vboot API. It calls VbInit() and VbSelectFirmware() with the data supplied by the loader. The vboot wrapper is compiled and linked as an rmodule and placed in cbfs as 'fallback/vboot'. It's loaded into memory and relocated just like the way ramstage would be. After being loaded the loader calls into wrapper. When the wrapper sees that a given piece of firmware has been selected it parses firmware component information for a predetermined number of components. Vboot result information is passed to downstream users by way of the vboot_handoff structure. This structure lives in cbmem and contains the shared data, selected firmware, VbInitParams, and parsed firwmare components. During ramstage there are only 2 changes: 1. Copy the shared vboot data from vboot_handoff to the chromeos acpi table. 2. If a firmware selection was made in romstage the boot loader component is used for the payload. Noteable Information: - no vboot path for S3. - assumes that all RW firmware contains a book keeping header for the components that comprise the signed firmware area. - As sanity check there is a limit to the number of firmware components contained in a signed firmware area. That's so that an errant value doesn't cause the size calculation to erroneously read memory it shouldn't. - RO normal path isn't supported. It's assumed that firmware will always load the verified RW on all boots but recovery. - If vboot requests memory to be cleared it is assumed that the boot loader will take care of that by looking at the out flags in VbInitParams. Built and booted. Noted firmware select worked on an image with RW firmware support. Also checked that recovery mode worked as well by choosing the RO path. Change-Id: I45de725c44ee5b766f866692a20881c42ee11fa8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-20f15tn/Include/OptionIdsInstall.h: Remove idle `… || )`Siyuan Wang
Change-Id: I4aba6cc490ab24c6db345c0c5a64a6a9985ed0ab Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/2864 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-16google/snow: rename a file so that it is clear what board it is forRonald G. Minnich
One might wonder what a board named 'build' does. Rename the file to build-snow. The fact that it is in a directory with google in the name should be enough to identify the vendor. Change-Id: I0b473cdce67d56fc6b92032b55180523eb337d66 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2766 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-08AGESA: Fix CR0_PE bit defineKonstantin Aladyshev
AGESA code has wrong definition of CR0_PE bit (1 instead of 0). PE [Protected Mode Enable] is 0 bit in CR0 register (If PE=1, system is in protected mode, else system is in real mode) Bit 1 is MP [Monitor co-processor] (Controls interaction of WAIT/FWAIT instructions with TS flag in CR0) System uses CR0_PE define, but I didn't expect any consequences because of this bug. Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2591 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08AGESA: Fix bug in AMD_DISABLE_STACK_FAMILY_HOOK_F15Konstantin Aladyshev
_RDMSR instruction loads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. EDX:EAX = MSR[ECX] So bit 49 will be contained in EDX register. Buggy code instead of bit 49 (CombineCr0Cd) sets bit [49-32=17] (PfcStrideDis). PfcStrideDis bit disables stride prefetch generation. This leads to memory bandwidth loss. _________ Supermicro H8QGI board After applying this change i observed huge memory bandwidth increase in tests that runs on small amount of cores. But unfortunately it doesn't affect overall bandwidth results on 4P system with 48 cores. So i think that in this system leading limiting factor is AMD HT-ASSIST feature (Probe filter). But right now it is not working. System stucks in Linux boot. I have done some experiments and figured out that stuck happens when system have cores in compute unit (CU) other than CU with BSC (boot strap core). CU is two cores (primary and seconary) that shares some things (L2 cache, FPU ...) So with probe filter i can boot Linux with one (BSC) or two (BSC + secondary core in its CU) cores. And with this configuration i can see memory bandwidth on 1 core (or two cores) close to original bios. Change-Id: I5a95f5b753d600c70d3c93d36fecc687610c61cd Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2588 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-25google/snow: enable GPIO entries and CHROMEOS in buildingRonald G. Minnich
These were not separable or it would have been two CLs. Enable CHROMEOS configure option on snow. Write gpio support code for the mainboard. Right now the GPIO just returns hard-wired values for "virtual" GPIOs. Add a chromeos.c file for snow, needed to build. This is tested and creates gpio table entries that our hardware can use. Lots still missing but we can now start to fill in the blanks, since we have enabled CHROMEOS for this board. We are getting further into the process of actually booting a real kernel. Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2467 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-24AMD f14 vendorcode: Fix warningMartin Roth
Add brackets around initializer in #define for PCIE_DDI_DATA_INITIALIZER to fix the warning: PlatformGnbPcie.c:89, GNU Compiler 4 (gcc), Priority: Normal missing braces around initializer [-Wmissing-braces] This warning happens for Inagua and South Station Change-Id: I7d8f742dd8335b704b0493aa6e9eaebc3cc50b1e Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/2495 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 11:52:47 +0000