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2021-02-04vendorcode/intel/Makefile: Add x86_64 supportPatrick Rudolph
This allows to compile FSP related tools (like the FSP loader) in x86_64 mode, but it doesn't add support for properly running x86_32 FSP on x86_64. This is handled in a separate patch. Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-04drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph
Add new Kconfig symbols to mark FSP binary as x86_32. Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. This issue has been reported here: https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. Tested on Intel Skylake. FSP-M no longer returns the error "Invalid Parameter". Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.hSubrata Banik
The recent merge of Intel ADL FSP 2017.00 appears to have introduced a new dependency within the file MemInfoHob.h. Adding required macros to resolve the dependency. BUG=b:178846328 Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50254 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04vc/google/chromeos: Drop <acpi/vpd.asl>Kyösti Mälkki
This was used as a means to read the MAC address and dynamically return it to the ethernet driver via ACPI. The kernel team ended up going another direction so this became obsolete. Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04vc/../chromeos.asl: Drop CHROMEOS guardKyösti Mälkki
coreboot proper now has a single include for this file with the guard around it already. Change-Id: Ice48a6af391170232a0319cc894bdb6c465c5143 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-04vendorcode/amd/fsp/cezanne: add UPD structs from FSP buildFelix Held
There will be incompatible changes during the further development of the coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct size to match the one in the FSP header. See CB:50241 for details. Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242 Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03soc/intel/tgl: Add configurable value for ConfigTdpLevelDerek Huang
According to Tigerlake TDP specifications (doc #575683, table 4-2), TGL supports different TDP levels depends on CPU segement/package, IA Cores and graphics configuration. For example, UP3 4-Core GT2 suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable TDP-Down_2=12W. This configurable value can be used to select suitable TDP level Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-02-03soc/amd/picasso: clean up and re-sort UPD tableChris Wang
Clean up the unused UPD and re-sort the table, and also update the new phy parameter in the soc code and overridetree. remove: EDpPhySel EDpVersion rename: DpPhyOverride -> edp_phy_override EDpPhySel -> edp_physel DpVsPemphLevel -> edp_dp_vs_pemph_level MarginDeemPh -> edp_margin_deemph Deemph6db4 -> edp_deemph_6db_4 BoostAdj -> edp_boost_adj eDP phy setting: DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0) COMMON_MAR_DEEMPH_NOM = 0x004b COMMON_SELDEEMPH60 = 0x0 CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80 BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-03vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037Subrata Banik
List of changes: 1. FSP-M Header: - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-29vc/google/chromeos/Kconfig: Remove unused NO_TPM_RESUMEFrans Hendriks
lint-008-kconfig reports unused symbol NO_TPM_RESUME. Remove NO_TPM_RESUME. BUG = N/A TEST = Build Intel Elkhart Lake with Chrome EC enabled Change-Id: I257ebcb4c42036d1476b9dc8e6d46fcc8c05f452 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28ACPI: Separate ChromeOS NVS in ASLKyösti Mälkki
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there is reduced dsdt.aml size and reduced GNVS allocation from cbmem. More importantly, it's less error-prone when the OperationRegion size is not hard-coded inside the .asl files. Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd/picasso: Add UPDs for support eDP power sequence adjustChris Wang
Add UPDs for eDP power sequence adjust. BUG=b:171954512 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-24soc,vendorcode/amd/cezanne: add basic FSP integrationFelix Held
This is a trimmed-down version of the Cezanne FSP integration code, so for example the UPD definitions are empty, which will be addressed later. Since coreboot just leaves the UPD values at their default, this is not a problem during the initial platform bring-up. Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-22vendorcode/google/chromeos: Build CSE Board Reset in RomstageKarthikeyan Ramasubramanian
CSE Firmware Sync is being performed in romstage currently. But the CSE board reset is not included as part of romstage. This causes the CSE firmware sync to use global reset instead of EC assisted AP reset with the old Cr50 Firmware version. Include the board specific CSE reset in romstage. BUG=b:171731175,b:177795247 BRANCH=dedede,volteer,puff TEST=Ensured that the Drawlat boots to OS with both old(0.0.22) and new(0.6.7) Cr50 FW versions. Change-Id: I5e362271ffb68ffd5884279acd1ab0a462195a8a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49850 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18ACPI: Refactor ChromeOS specific ACPI GNVSKyösti Mälkki
The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of <chromeos/gnvs.h>. If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-15vc/eltan/security/verified_boot/vboot_check.c: Add check PROG_POSTCARFrans Hendriks
On Coffee Lake systems prog_locate_hook() is called with PROG_POSTCAR. For this reason the early check is not executed. Add check for prog->type == PROG_POSTCAR, but execute verified_boot_early_check() once. BUG = N/A TEST = Build and boot on Facebook FBG1701 and Intel CoffeeLake system Change-Id: Ia3bd36064bcc8176302834c1e46a225937d61c20 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48852 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11{soc,vc,mb}/intel: Drop support for Cannon Lake SoCFelix Singer
Drop the support for the Intel Cannon Lake SoC for various reasons: * Most people can't use coreboot on Cannon Lake, since the required FSP binaries aren't publicly available. Given that FSP binaries for several newer platforms have been released, it's very unlikely that Cannon Lake FSP will ever be released. * It seems there is no interest in this, since the reference mainboard is the only available mainboard in tree. Also, remove the related reference mainboard intel/cannonlake_rvp and its FSP headers in intel/fsp2_0/cannonlake. Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11vc/intel/FSP2_0/CPX-SP: update to FSP ww01 releaseJonathan Zhang
With Intel CPX-SP FSP ww01 release, CidBitMap field is added to DimmDevice struct in hob_memmap.h. The copyright statements were updated to accomodate year 2021. gpio_fsp.h is not needed any more as coreboot takes over GPIO configuration. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I3242c8b50401757a28de8a9e9c71fb95bc0515dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-11vendorcode/intel/fsp: Update Tiger Lake v3444 FSP HeadersSrinidhi N Kaushik
Update v 3444 FSP headers for Tiger Lake platform to include the below 2 UPDs to control TC cold support usb connect or not. FSPS: Usb3ComplModeEnable DisableTccoldOnUsbConnected BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I68b32730293fc83b5088074f71fa215220574748 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-09vc/intel/fsp1_1/skylake: Remove unused header fileFelix Singer
Change-Id: I329a1484cbd16296a2aa047876c2506c74d4452d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-03vc/google/chromeos: Move chromeos_set_me_hash() prototypeKyösti Mälkki
Change allows to remove some <chromeos/gnvs.h> exposure from coreboot proper. Change-Id: I7817914cc7b248331bb8fa79baa642ed548bbc11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48782 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28sb/amd/pi/hudson: Enable use of common GPIO APIKyösti Mälkki
The code in soc/amd/common has an implementation of GPIO register space that is compatible with the hardware sb/amd/pi/hudson supports. Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-23vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1514_11Subrata Banik
List of changes: FSP-S Header: - Add UPD MicrocodeRegionBase and MicrocodeRegionSize - Adjust UPD Offset for Reservedxx Change-Id: I376abf6cd64dcf8c848901074e2c2f30d4f302da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2020-12-21soc/amd/picasso: Add UPDs for support eDP phy tunning adjustChris Wang
Add UPDs for eDP phy tunning adjust BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I6df063f828447841ac9a6dba00a4aad2001f04df Reviewed-on: https://review.coreboot.org/c/coreboot/+/48731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-18vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1512_11Subrata Banik
List of changes: FSP-S Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace44 -> UnusedUpdSpace45 Change-Id: If0c18cbb556fc41786391464b76d7c9cc19eab0d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-07vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOBJohnny Lin
Tested=On OCP Delta Lake, verify the memory map hob data are correct. Change-Id: I7bb2e9f41daa4cbce49169535eadf7f0d4972716 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-05amd_blobs: Always set default pathsNico Huber
Don't make the default paths to AMD blobs depend on USE_AMD_BLOBS. This way we get error messages about the missing files when the blobs repos aren't checked out. Change-Id: I754fdc5e1414c8a3dc88b364bcfbea9a26b59eb0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profileMike Banon
The ability to set up a custom memory profile is useful if you don't like the XMP memory profiles (if they exist) of your RAM sticks, or want to try some overclocking. Read SPD data will be overriden by your custom values. Tested on Crucial BLT8G3D1869DT1TX0 (1866MHz 9-9-9-27). Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-02vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profilesMike Banon
Add XMP memory profiles support that has been tested on f15tn (A88XM-E) and f16kb (AM1I-A) with two Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40488 Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v2341Tan, Lean Sheng
The FSP-M/S/T related headers added are generated as per FSP v2341. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I98f738402490b47efa1a346f81db47857e384e13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-02vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_04Ronak Kanabar
The headers added are generated as per FSP v2385_04. Previous FSP version was 2385_02. Changes Include: - add FastPkgCRampDisable, SlowSlewRate, PreWake, RampUp and RampDown UPDs in Fsps.h BUG=b:174330941 BRANCH=dedede TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3438485 Change-Id: I477af05c34f767a43990670a711992641eaf6000 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47862 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-26vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1483_11Subrata Banik
List of changes: 1. FSP-M Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace32 -> UnusedUpdSpace29 2. FSP-S Header: - Rename UPD Offset UnusedUpdSpace46 -> UnusedUpdSpace44 Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47901 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22vendorcode/eltan/security: Add dependency for menu itemsFrans Hendriks
Subitem for VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT are always displayed. Add dependency and display these items when feature is enabled only. Tested on Facebook FBG1701. Change-Id: I51e47efddbcf51d87439bec33b85432da56fa4c6 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22cpu/amd/pi: Remove unused cpu code 00660F01Martin Roth
Remove the processor directory and references to the Kconfig symbol. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I403a453362fd76d6ef2a5b75728a362efa4f2491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFSFurquan Shaikh
If AGESA is added as a raw binary (and not a stage), then cbfstool does not perform relocation. In this case, it should be added only to COREBOOT (i.e. default) CBFS since the binary needs to be present only in one specific location that is present in the default CBFS. Change-Id: I7a7edc217663f9d1d36b05308bbd35f56a28b9b1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-21vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1474_11Subrata Banik
List of changes: 1. FSP-M Header: - Rename UPD Offset UnusedUpdSpace33 -> UnusedUpdSpace32 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-20vc/intel/fsp2/denverton_ns: Remove unused filesFelix Singer
The Denverton-NS SoC uses the header files from the FSP git repository. Therefore, remove these from coreboot source. Change-Id: Ib22d3f5e5ce83eb83bf589ea8bba7b55ebe44ea8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47754 Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20vc/google/chromeos/sar: Make "SAR not found" log a debug messageMaulik V Vaghela
coreboot might not store wifi SAR values in VPD and may store it in CBFS. Logging the message with 'error' severity may interfere with automated test tool. Lowering severity to BIOS_DEBUG avoids this issue. BUG=b:171931401 BRANCH=None TEST=Severity of message is reduced and we don't see it as an error Change-Id: I5c122a57cfe92b27e0291933618ca13d8e1889ba Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-20vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field inTim Chu
SystemMemoryMapHob This field from SystemMemoryMapHob can be used to define error correction type in SMBIOS type 16. Tested=On OCP Delta Lake, the value is expected. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/47505 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2385_02Ronak Kanabar
The headers added are generated as per FSP v2385_02. Previous FSP version was 2376. Changes Include: - add VtdIopEnable, VtdIgdEnable, and VtdIpuEnable UPDs in Fspm.h TEST=Build and boot JSLRVP Change-Id: I268eca1bcbbf26d4dc4ecf54d432cdb6ad49b4eb Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47500 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19ACPI S3: Replace acpi_is_wakeup()Kyösti Mälkki
It was supposed to return true for both S2 and S3, but level S2 was never stored in acpi_slp_type or otherwise implemented. Change-Id: Ida0165e647545069c0d42d38b9f45a95e78dacbe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-16vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW45 FSP Memory map HOB mismatchJohnny Lin
Tested=On OCP Delta Lake, verify the memory map hob data are correct. Change-Id: I86bd809e21270395c4115788e5521606e9dcc2fb Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-15vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 3444. Previous version was 3425. BUG=b:173160613 BRANCH=none TEST=build and boot delbin Cq-Depend:chrome-internal:3403586, chrome-internal:3403392 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47555 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1454Subrata Banik
List of changes: 1. FSP-M Header: - Add new UPD Lp5CccConfig - Adjust Reservedxx UPD Offset 2. FSP-S Header: - Adjust UPD Offset for Reservedxx, PsOnEnable, RpPtmBytes, PmSupport, GtFreqMax, Hwp, TccActivationOffset, Cx, PchLockDownGlobalSmi, PcieRpLtrMaxSnoopLatency, PcieRpLtrMaxNoSnoopLatency, UnusedUpdSpace45 Change-Id: I973f48b2af0336f04ee16cd1c4c91940a49af0e3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47244 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-07vc/intel/FSP2_0/CPX-SP: update to ww45 release and add watermark optionJonathan Zhang
Intel CPX-SP FSP ww45 release annotates default values for FSP-M UPD variables. FSPM MemRefreshWatermark option support is present in FB's CPX-SP FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP FSP binary, this option takes the space of UnusedUpdSpace0[0]. For DeltaLake mainboard, if corresponding VPD variable is set, use it to control the behavior. Such control is effective when FB's CPX-SP FSP binary is used. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-11-06soc/amd/picasso: Update coreboot UPD variable names to include unitsZheng Bao
Use command below to change the variable globally. sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \ --exclude-dir=build --exclude-dir=crossgcc` BUG=b:171334623 TEST=Build Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-02vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 3425. Previous version was 3373. BUG=b:172045149 BRANCH=none TEST=build and boot delbin Cq-Depend:chrome-internal:3373431 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47041 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30vc/amd/fsp: Update bl_errorcodes_public.hMartin Roth
Replace the initial bl_errorcodes_public.h (a temporary, minimal version) with the full version released by AMD. BUG=None TEST=Build BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 11:11:19 +0000