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2021-05-02vendorcode: add code for cezanne psp_verstageKangheui Won
These are mostly copied from picasso code with exception for bl_syscall_public.h. For some SVCs svc number and/or prototype has been changed. Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6b431fdbf34fca2747833980ae53c06244905f93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-30amd/cezanne: Add telemetry setting to UPDChris Wang
Add telemetry setting to UPD, the value comes from the SDLE testing. BUG=b:182754399 TEST=Build & Boot guybrush Cq-Depend: chrome-internal:3787638 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I9dd3643e9c582a41192130901935eef321b2c67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52733 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30mb/google: Move ECFW_RW setting for non-ChromeEC boardsKyösti Mälkki
The boolean is stored in ChromeOS NVS, not GNVS. Change-Id: I5c424a052d484228a456f8f0ad4fb0bed3165e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-30vc/google/chromeos: Refactor GNVS initKyösti Mälkki
Move the support code for filling ChromeOS GNVS from acpi/chromeos-gnvs.c to vc/google/chromeos/gnvs.c. Change-Id: I7e92206561812eb3dc69739df49b6c3a93853858 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50612 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29migrate out of flashrom deprecated optionsDaniel Campello
This change replaces --diff and --fast-verify for the supported equivalent flashrom options Signed-off-by: Daniel Campello <campello@chromium.org> Change-Id: I8c48c7f819f968c3ddd94278415e5e9e0ef93924 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-04-27vc/amd/agesa/f15tn/Config/PlatformInstall.h: enable the AMD CPB featureMike Banon
Enable the AMD Turbo Core a.k.a. AMD Core Performance Boost (CPB) feature [1] for f15tn boards - like it's already done for f14 and f16kb. According to CB:51394 [2] it improves the performance of Lenovo G505S by up to 50%, and is unlikely to cause regressions for the other boards. [1] https://en.wikipedia.org/wiki/AMD_Turbo_Core [2] https://review.coreboot.org/c/coreboot/+/51394 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I1eaa8ff3953c492e8f9431d7b4a09b86e0ef77a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-26amd/cezanne: Add slow_ppt_time & thermctl_limit to UPDMartin Roth
These values will be added in the upcoming STAPM configuration update. BUG=b:185209734 TEST=Build & Boot guybrush Cq-Depend: chrome-internal:3780259 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26src/vendorcode/amd/fsp/picasso: Add HDMI 2.0 Disable setting section of ↵Patrick Huang
FspmUpd.h This change adds HDMI 2.0 Disable setting BUG=b:179170193 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Ie00389074f3718a23440c41ae0b116455aa8b603 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-04-26vc/amd/fsp/cezanne:Add s0i_enable upd controlJason Glenesk
Add upd to enable S0i3 in fsp. BUG=b:178728116 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Cq-Depend: chrome-internal:3777391 Change-Id: I01759caa4d72e284b2b960634f89c6a2ab1dad57 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-21ChromeOS: Use CHROMEOS_NVS guardKyösti Mälkki
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20vc/amd/fsp/cezanne: update SMU setting section of FspmUpd.hFelix Held
There was a bug in the UPDs for STAPM settings that required one UPD field to be extended from 8 to 32 bits, so this patch is a breaking change to the binary layout, but since the UPD struct fields for the SMU SoC power and performance tuning parameters aren't populated by the coreboot code yet and we added some padding after each logical section in the UPD, this isn't expected to cause too much trouble; the only thing that is required is that a very recent build of the FSP binaries need to be used in combination with the new coreboot code that will populate the struct fields in follow-up patches. BUG=b:182297189 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If39aaf64e8e1b4c0426f22ce8ed07707c2a31e61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-04-16vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2117_00Ronak Kanabar
The headers added are generated as per FSP v2117_00. Previous FSP version was v2081_02. Changes Include: - Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h - Remove FivrFaults and FivrEfficiency Upds from FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:184129128 BRANCH=None TEST=Build and boot ADLRVP Change-Id: I068552084b1ef3e5c4fba7a46240d116c92c7b5b Cq-Depend: TBD Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-15vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v4133Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 4133. Previous version was 4043. BUG=b:185463045 BRANCH=none TEST=build and boot voxel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I27d8f7783a944bdd21e3615799b1342ffb0edd22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-10vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v4043Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 4043. Previous version was 3444. BUG=b:178846052 BRANCH=none TEST=none Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ibada380fe757d9a8b50b2ddfeb2c86b4a98cb5e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-07vc/amd/fsp/cezanne/FspmUpd: use arrays for DXIO/DDI descriptorsFelix Held
This allows coreboot to easily iterate over the descriptors. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2ecb3b543f90b8c6a957794f0c55b0ba5c72d59d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07vc/amd/fsp/cezanne: update UPD headersMatt Papageorge
The UPD header files get generated as part of the FSP build process. For the initial Cezanne development we took the Picasso UPD data structures as a starting point. This patch replaces it with the first version of the Cezanne-specific UPD data structures that is present in version 12 of the internal work-in-progress FSP binary drops. The serial_port_stride UPD-M field is removed, since the information is already given by serial_port_use_mmio. The stride is 4 bytes for the MMIO UART case and 1 byte for the legacy I/O case. BUG=b:182524631 TEST=NVMe works on google/guybrush when the rest of the patch train is applied as well. Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-07vc/amd/fsp/cezanne: add platform_descriptors.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib16f133b270c99c6e060e5bd0c156cbb03293474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-06vendorcode/intel/FSP2_0/CPX-SP: Declare struct RC_VERSION non-packedDeomid "rojer" Ryabkov
It is a bug acknowledged by Intel (IPS case 00600003) that has been fixed for SRP but won't be fixed for CPX. This fixes field offsets for fields that follow SYSTEM_STATUS.RcVersion Change-Id: I5248734e2f086d39bb75b7b1359e60dfd8704200 Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-06vc/eltan/security/mboot/Kconfig: Add dependency of VBOOTFrans Hendriks
VENDORCODE_ELTAN_MBOOT should not be used when VBOOT is enabled. Hide VENDOCODE_ELTAN_MBOOT when VBOOT is enabled. BUG = N/A TEST = run `make menuconfig` and boot Facebook FBG1701 Change-Id: Iac57103431cc7efac5b6019f180572d255e683ab Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2021-04-05vc/amd/fsp/picasso/platform_descriptors: fix typos in enum element namesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5cad6a6a585320b33bfab7b3950888241f7c179c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-23vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02Ronak Kanabar
The headers added are generated as per FSP v2081_02. Previous FSP version was v2081_02. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Add UPDs in Fsps.h and Fspm.h BUG=b:180918805 BRANCH=None TEST=Build and boot ADLRVP Change-Id: I69611de8286a570c59a6b4a44b9164384e9be81f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51632 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18vc/google/chromeos/acpi: Add type to OIPG declarationRaul E Rangel
OIPG is a Package. Define the type so it doesn't default to UnknwonObj. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I068ed4ae95967aa884506c4971ee2e2dba7b5e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51537 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17sar: Fix semantics of `get_wifi_sar_cbfs_filename()`Furquan Shaikh
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then `get_wifi_sar_limits()` assumes that the default filename is used for CBFS SAR file. This prevents a board from supporting different models using the same firmware -- some which require SAR support and some which don't. This change updates the logic in `get_wifi_sar_limits()` to return early if filename is not provided by the mainboard. In order to maintain the same logic as before, current mainboards are updated to return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default case. Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17vc/google/chromeos: Deprecate support for SAR tables in VPDFurquan Shaikh
SAR table in VPD has been deprecated for Chrome OS platforms for > 1 year now. All new Chrome OS platforms have switched to using SAR tables from CBFS. This change drops the support for SAR table in VPD from coreboot to align with the factory changes. `get_wifi_sar_limits()` is thus updated to look for SAR file in CBFS only. Anyone building ToT coreboot for an already released Chrome OS platform with SAR table in VPD will have to extract the "wifi_sar" key from VPD and add it as a file to CBFS using following steps: - On DUT, read SAR value using `vpd -i RO_VPD -g wifi_sar` - In coreboot repo, generate CBFS SAR file using: `echo ${SAR_STRING} > site-local/${BOARD}-sar.hex` - Add to site-local/Kconfig: ``` config WIFI_SAR_CBFS_FILEPATH string default "site-local/${BOARD}-sar.hex" ``` BUG=b:173465272 Change-Id: I21d190dcc9f3554fab6e21b4498e7588a32bb1f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-16vendorcode/mt8192: change to short log macro namesXi Chen
Originally, log macro names are too long, and they use double parentheses style: ((...)), which causes compile or runtime error easily. Now, change them to single parenthesis mode (...), and use shorter name. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2959dc1ba0dd40a8fb954406072f31cf14c26667 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16vendorcode/mt8192: fix fast-k gating PI P1 initializationXi Chen
In RX Gating flow, PI P1 delay is missing, so re-add the initialization. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ic72ccecd205062ee79f6928993fac772fc10f880 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16vendorcode/mt8192: limit fast-k frequency count from 7 to 3Xi Chen
For bootup faster, fast-k elapsed time is improved by ~400ms. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ifa945012aa66df4433fe63aab75a1e785d343d9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51406 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15vc/intel/fsp/fsp2_0/cooperlake_sp: Update memory map hob for WW06 FSPJohnny Lin
Change-Id: Id534e1b73e73bbb9d944c988d1ef66bc1f463eff Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50867 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12soc/amd: GOP: add UPD for VBIOS bufferNikolai Vyssotski
This UPD will be used to pass VBIOS buffer pointer to FSP PEI GOP driver. BUG=b:171234996 BRANCH=Zork Change-Id: I0c5d4a9d96e5c3d47e262072b689ed62e59129b3 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49866 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02Ronak Kanabar
The headers added are generated as per FSP v2081_02. Previous FSP version was v2037. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Add DevIntConfigPtr and NumOfDevIntConfig UPDs in Fsps.h BUG=b:180758116 BRANCH=None TEST=Build and boot ADLRVP Cq-Depend: chrome-internal:3669105 Change-Id: Ib99748a428709ffad27d47f600e00bd91b70d8f3 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51248 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08soc/mediatek/mt8192: initialize DRAM using vendor reference codeHuayang Duan
Mediatek has released the reference implementation for DRAM initialization in vendorcode/mediatek/mt8192/dramc (CB:50294) so we want to use it to replace the derived calibration code in soc folder. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-08vendor: mediatek: Add mediatek mt8192 dram initialization codeXi Chen
This is the DRAM initialization code from the reference implementation released by Mediatek for MT8192. The DRAM calibration code can be taken as a standalone library, used by different boot loaders for initializing DRAM and following a different coding style (coreboot was using Linux Kernel coding style), so we have to put it in vendor code folder. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I3853204578069c6abf52689ea6f5d88841414bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-04vc/amd/fsp/picasso: fix DDI enum name prefixFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12ec6a3c2704effc1a626181898a9ed7a17f0640 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51239 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03vc/amd/fsp/picasso: increase FSPS UPD block size from 0x152 to 0x202Nikolai Vyssotski
We will need more FSPS UPD space for PEI GOP changes coming. BUG=b:171234996 BRANCH=Zork Cq-Depend: chrome-internal:3609213, chromium:50576 Change-Id: I35d0bb0ee30e04f66882b6103acd9d673d040c07 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-25vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2037Ronak Kanabar
The headers added are generated as per FSP v2037. Previous FSP version was v2037. Changes Include: - add BootFrequency, RMTBIT, RmtPerTask, RMTLoopCount and MrcFastBoot UPDs in Fspm.h - add EnableFastMsrHwpReq, VbtSize, CpuPcieComplianceTestMode, LidStatus and PcieComplianceTestMode UPDs in Fsps.h BUG=b:178461282,b:180627057 BRANCH=None TEST=Build and boot ADLRVP Change-Id: I5496dfebc7b65a94abb31244ef2b400d89d6d444 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50914 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/intel/tigerlake: Add CrashLog implementation for intel TGLFrancois Toguo
CrashLog is a diagnostic feature for Intel TGL based platforms. It is meant to capture the state of the platform before a crash. The state of relevant registers is preserved across a warm reset. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-17vc/google/chromeos: Account for GNVS allocated earlyKyösti Mälkki
We have adjusted allocation order such that GNVS is available before ME hash needs to be stored. Change-Id: I8428dd85f44935938a118a682767f2f8d6d539ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-17vc/google/chromeos: Allocate RAMOOPS lateKyösti Mälkki
The allocation is for the OS. Just need to take care in the firmware that ChromeOS GNVS is allocated first. Change-Id: I16db41b31751d7b4a8a70e638602f3f537fe392e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50609 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17vc/intel/fsp: Change line endings to unixMartin Roth
These files have windows line endings. Change to unix to match the rest of the tree. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5bb3338745a6a47b6714aa268d16866aada27790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17treewide: Remove trailing whitespaceMartin Roth
Remove trailing whitespace in files that aren't typically checked. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I8dfffbdeaadfa694fef0404719643803df601065 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
Always allocate RAMOOPS from CBMEM and drop the related static variable CHROMEOS_RAMOOPS_RAM_START. Change-Id: Icfcf2991cb78cc6e9becba14cac77a04d8ada56a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50608 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16soc/intel: Switch guard to CHROMEOS_RAMOOPSKyösti Mälkki
Change-Id: I484220342b5c1055471403f562a8c9db6a403a05 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-15src: use ARRAY_SIZE where possiblePatrick Georgi
Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09vc/amd/fsp/cezanne: add FspGuids.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I54579a7998d1a4a232cb5286d3f481e2e63a4476 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50402 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06drivers/intel/fsp2_0: Add support for MP services2 PPIAamir Bohra
Add support for MP services2 PPIs, which is slight modification over MP services 1 PPIs. A new API StartupAllCPUs have been added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES parameter has been removed from all MP PPI APIs. This implementation also selects the respective MP services PPI version supported for SoCs BUG=b:169196864 Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-05soc/amd/picasso: add UPD for RV2 USB3 phy setting adjustChris Wang
add UPD for RV2 USB3 phy setting adjust. Note: it only for RV2 silicon and not available for RV/PCO. Usb 3.1 PHY Parameters: 1. RX_EQ_DELTA_IQ_OVRD_VAL -Override value for rx_eq_delta_iq. Range 0-0xF 2. RX_EQ_DELTA_IQ_OVRD_EN -Enable override value for rx_eq_delta_iq. Range 0-0x1 3. Override value for rx_vref_ctrl. Range 0 - 0x1F 4. Enable override value for rx_vref_ctrl. Range 0 - 0x1 5. Override value for tx_vboost_lvl: 0 - 0x7. 6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 7. Override value for rx_vref_ctrl. Range 0 - 0x1F 8. Enable override value for rx_vref_ctrl. Range 0 - 0x1 9. Override value for tx_vboost_lvl: 0 - 0x7. 10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 BUG=b:175192931 TEST=Build/verify the valule will been apply on dirinboz Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04vendorcode/intel/Makefile: Add x86_64 supportPatrick Rudolph
This allows to compile FSP related tools (like the FSP loader) in x86_64 mode, but it doesn't add support for properly running x86_32 FSP on x86_64. This is handled in a separate patch. Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-04drivers/intel/fsp2_0: Fix running on x86_64Patrick Rudolph
Add new Kconfig symbols to mark FSP binary as x86_32. Fix the FSP headers and replace void pointers by fixed sized integers depending on the used mode to compile the FSP. This issue has been reported here: https://github.com/intel/FSP/issues/59 This is necessary to run on x86_64, as pointers have different size. Add preprocessor error to warn that x86_64 FSP isn't supported by the current code. Tested on Intel Skylake. FSP-M no longer returns the error "Invalid Parameter". Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.hSubrata Banik
The recent merge of Intel ADL FSP 2017.00 appears to have introduced a new dependency within the file MemInfoHob.h. Adding required macros to resolve the dependency. BUG=b:178846328 Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50254 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04vc/google/chromeos: Drop <acpi/vpd.asl>Kyösti Mälkki
This was used as a means to read the MAC address and dynamically return it to the ethernet driver via ACPI. The kernel team ended up going another direction so this became obsolete. Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 23:17:43 +0000