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2018-08-06vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt ConfigKane Chen
From doc 571118, the bit 5 of OdtConfig is nWR config. If the bit 5 is set, MRC will set MR1 nWR field to 24. If the bit 5 is clear, MRC will set MR1 nWR field to 6. Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/27814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-31src/vendorcode/amd/pi/00670F00: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove all stoney IMC files and functions from vendor code. BUG=b:111780177 TEST=Build grunt and gardenia Change-Id: I06e993fa498cc0978c1d037bc6001682407f7fac Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27652 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-25vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.5John Zhao
Update FSP header files to match FSP Reference Code Release v2.0.5 for Geminilake BUG=b:111683980 CQ-DEPEND=CL:*653835 Change-Id: Ib5ac532843fdb30ac3269fb6ed96dd05ef5736cc Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27623 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17vendorcode/cavium/include: Make bdk_pop and dpop staticMartin Roth
Fix an undefined reference error with GCC 8.1 /cb- build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk /libbdk-dram/bdk-dram-size.o: In function `bdk_dram_get_size_mbytes': /home/coreboot/slave-root/workspace/Testing_coreboot/src/vendorcode/cavium/bdk /libbdk-dram/bdk-dram-size.c:198: undefined reference to `bdk_pop' /cb- build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk /libbdk-dram/bdk-dram-test.o: In function `bdk_get_num_cores': /home/coreboot/slave- root/workspace/Testing_coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal /bdk-utils.h:164: undefined reference to `bdk_dpop' /cb- build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk/libdram /dram-init-ddr3.o: In function `init_octeon3_ddr3_interface': /home/coreboot/slave- root/workspace/Testing_coreboot/src/vendorcode/cavium/bdk/libdram/dram-init- ddr3.c:7550: undefined reference to `bdk_pop' /cb- build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk/libdram /dram-l2c.o: In function `bdk_get_num_cores': /home/coreboot/slave- root/workspace/Testing_coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal /bdk-utils.h:164: undefined reference to `bdk_dpop' make[1]: *** [src/arch/arm64/Makefile.inc:119: /cb- build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/cbfs/fallback/romstage.debug] Error 1 Change-Id: Ifcde5476c6f347c0eac7ca44bac88d3fa4017fb7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/27493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2018-07-17cavium/bdk: Poke the watchdog while PCIe initPatrick Rudolph
Prevent a reboot loop due to slow PCIe init. Poke the watchdog a few times. Change-Id: I03739d7dbad3072ccf77364fa4caba42c66ac643 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27455 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17cavium/bdk: Fix reference clockPatrick Rudolph
Swap 100Mhz and 156Mhz reference clock. Correct values are taken from __bdk_qlm_sff81xx_set_reference(). Tested on Cavium's cn8100_sff_evb. Change-Id: I312ce7379b361594249f9f26f4e561ebf57347df Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27454 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17cavium/bdk: Fix possible divide by zeroPatrick Rudolph
Fix Coverity CID1393970 Change-Id: I5db6866b8e51eaea201a4c03e59d7d00f4f826e7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-17cavium/bdk: Fix coverity and remove hardcoded DRAM speedPatrick Rudolph
* Fix CID1393963 (Uninitialized variables) * Comment in working code * Remove workaround to limit DDR speed Change-Id: I96289da43c1018c2fdf9d013ce7f21d7511ba595 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27452 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17cavium/bdk: Read DDR freq from memory controllerPatrick Rudolph
The BDK config subsystem can't store values in romstage. Read frequency from DDR memory controller instead from BDK config. Fixes memory info showing always 0 MT/s. Change-Id: Iaee33e57e27ca182f41be923cf950868f66d3638 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27451 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17cavium/bdk: Fix possible buffer overrunPatrick Rudolph
Fix Coverity CID1393975 Change-Id: I275cabf55fba464be7bd4c21dfe5826ea554ac84 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-17bdk: Use Kconfig options instead of getenv()Patrick Rudolph
* Use Kconfig options instead of unusable getenv * Select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS on CN81XX * Fix Coverity CID 1393976 (DEADCODE) Tested on Cavium's cn8100_sff_evb. Change-Id: Ia16c0161b0e9cf5d06418e46556c0fb45532a5b1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-13intel/wifi: Add WGDS ACPI method for Geo Aware SARPratik Prajapati
To comply with all relevant bodies throughout the world, SAR settings take into account the lowest common denominator Tx power settings. This setup may lead to non-optimal performance when the user location is in a country that may allow higher power setting. The purpose of Wireless Geo Delta Settings (WGDS) is to provide offset settings for FCC, Europe, Japan and Rest of the world. These offsets would be added (by Intel wifi driver) to the base SAR Tx Power as defined in WRDS and EWRD BUG=b:65155728 BRANCH=none TEST=WGDS ACPI table gets created as expected. Change-Id: I4f602e3f95ff3545db6cc6e428beb9a36abd9296 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-12Coverity: Fix CID1393978Patrick Rudolph
Fix a typo. Only memcpy into target buffer if pointer is not NULL. Change-Id: I1aa4b2ce1843e53ab6ed2224eaa928fc79ea3b83 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-10cavium: Add CN81xx SoC and eval board supportDavid Hendricks
This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-03soc/cavium: Integrate BDK files into corebootDavid Hendricks
* Make it compile. * Fix whitespace errors. * Fix printf formats. * Add missing headers includes * Guard headers with ifdefs Compile DRAM init code in romstage. Compile QLM, PCIe, RNG, PHY, GPIO, MDIO init code in ramstage. Change-Id: I0a93219a14bfb6ebe41103a825d5032b11e7f2c6 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/25089 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-13vc/amd/00670F00: Sync AGESA.h with PI blobMarshall Dawson
Add a new callout definition for AgesaGetTempHeapBase and displace AgesaHeapRebase (which was merged too soon) in the ordering. Also add its structure. AGESA will be modified to ask coreboot for the location for temporary storage of heap data at the end of InitPost. The old methodology is to use 0xb0000 but the change will allow coreboot to determine the location. BUG=b:74518368 Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26145 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-24Remove leftover AMD CIMX RD890 vendorcodeKyösti Mälkki
Change-Id: Ic7d80b25c0815f3816ae40646d024e0d9fe61f08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-22vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.3Srinidhi N Kaushik
Update FSP header files to match FSP Reference Code Release v2.0.3 for Gemimilake CQ-DEPEND=CL:*627827 Change-Id: I17438f18fc3a1ea7ad9bd69a06adb1330d917257 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/26285 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22stonyridge: Add TP_Perf_STRUCT structRaul E Rangel
The TP_Perf_STRUCT was missing from pi/00670F00. So I copied the file from src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h and removed everything that we don't need. I did have to change MAX_PERFORMANCE_UNIT_NUM so it matches the size used by pi/00670F00. This struct is used to extract the timestamps from AGESA. BUG=b:64549506 TEST=built on grunt Change-Id: I06ec82348e3d10f2430c1192a925a49389ae4414 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26235 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18intel/fsp: Update Cannonlake FSP headerLijian Zhao
Update Cannonlake FSP header to version 7.x.2E.50, the following changes were made, Memory Init UPD: 1. Add GDXC configuration options. 2. Remove some internal graphics memory selections. 2. Remove Fixed mid option for SaGv. 3. Add DualDimm per channel board type. 4. Remove PEG IMR options. Silicon Init UPD: 1. Add CD clock selections of 675MHz. 2. Remove Pcode PreWake/Rampup/RampDn time selections. 3. Remove C3 state demotion/unDemotion selections. BUG=None TEST=Build and boot up on meowth platform. Change-Id: I08ffb14df9f32089dbf44fa5bd3fc58a5bedb90d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/26148 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-10AGESA f14: Remove OPTION_DDR2Kyösti Mälkki
Was never used for the boards in our tree. Change-Id: Ib9e9ab25ccb8d1d556fdeb8bb4c6558f25bb81b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-10AGESA f14 vendorcode: Only have f14 Ontario configKyösti Mälkki
Change-Id: I8cf2f23d785e934371dfa687483491cd22b9863d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-09vendorcode/amd/pi/00670F00: Control which procedure buildsRichard Spiegel
Vendor code is compiled as a library, thus the whole library is included into the final image. However, not all procedures are required, they are there because original AGESA code had them. We cannot remove them, in order to facilitate porting of fixed AGESA code. Therefor add #if throughout the code to allow the control if unneeded procedures will be build. BUG=b:78610011 TEST=Build and boot grunt; build kahlee and gardenia. Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26135 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09vendorcode/amd/pi/00670F00: Remove unneeded includesRichard Spiegel
Vendor code has several headers included into source code that are not needed in order to build them. Remove unneeded #include. This is part of controlling the build of unneeded procedures within vendor code. BUG=b:78610011 TEST=Build grunt. Change-Id: Id7d451b6be564632836fc64fd343131edb85183a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-06AGESA: Remove remains of HT recoveryKyösti Mälkki
While built, this code was never called. Change-Id: Ie8216d8f4636330d38ea02aab83bc9e440864f17 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-06AGESA f14: Remove early HT initKyösti Mälkki
Syncronise HT init code with f12 vendorcode. Constructor for HT init is not required since init itself is not called. Change-Id: I0552c4d019c700f84d98473978afb18fe4eea1e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-06AGESA: Run ar with DTKyösti Mälkki
Create libagesa as a thin and deterministic archive file, this could reduce build time and used space. Change-Id: Icfd1f3fbf54f7e61ab528fa7686331182959c7d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/22068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-03vendorcode/amd/agesa: Fix variable length array declarationKyösti Mälkki
Fix (assumed) regression with commit ac63b41 vendorcode/amd/agesa: Fix variable length array declaration The code used sizeof() on the struct where array length was previously adjusted, but only f14 case was fixed accordingly. Change-Id: Ib83660d5e102e13b4ffad19fb78f695ac4a871dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26036 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03vendorcode/amd/agesa: Fix variable length array declarationPaul Menzel
Definition of S_PSTATE only allowed PStateStruct[0], while it is effectively used as a flexible array. Since sizeof(S_PSTATE) is reduced here by sizeof(S_PSTATE_VALUES), we have to account for that when calculating PStateLevelingSizeOfBytes. In S_PSTATE context, PStateStruct[PStateMaxValue] is valid reference. GCC 7.2.0 warns about an out of bounds array subscript. ``` CC libagesa/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.o src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c: In function 'PStateLevelingMain': src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c:524:65: error: array subscript is above array bounds [-Werror=array-bounds] PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html Change-Id: If9598a951c6b882432689b677a956c44650c7083 Found-by: gcc (Debian 7.2.0-2) 7.2.0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21297 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-27vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.2Srinidhi N Kaushik
Update FSP header files to match FSP Reference Code Release v2.0.2 for Gemimilake CQ-DEPEND=CL:*594651,CL:*598345 Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-25vendorcode/amd/pi/00670F00: Remove include headerGarrett Kirkendall
Remove Fch.h from being included in src/vendorcode/amd/pi/00670F00/agesa_headers.h. It is not needed. BUG=b:69220826 BRANCH=master TEST=build Gardenia and Grunt systems. Change-Id: Ifde58421d20c813ae5708b1d9c6ec76433051d33 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-16vendorcode/amd/pi/00670F00: Remove unused headersGarrett Kirkendall
Remove unused header files in src/vendorcode/amd/pi/00670F00/agesa_headers.h. This is a first clean up. Hopefully more headers will be removed in other commits. Header files cannot be removed at this time. They are used by files in vendorcode/amd/pi/00670F00/. BUG=b:77944801 BRANCH=none TEST=build Gardenia and Grunt Change-Id: I99b77f6ba41ded30122a01bbe709681312561436 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25644 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16vendorcode/amd/pi/00670F00: Remove unused headersGarrett Kirkendall
Remove unused AGESA header files from vendorcode/amd/pi/00670F00/binaryPI/AGESA.c BUG=b:77905293 BRANCH=none TEST=build Gardenia. Change-Id: Ic38424d489dcc37a4074159e33fca0d49c71f701 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-11Correct "MTTR" to "MTRR"Jonathan Neuschäfer
The term MTRR has been misspelled in a few places. Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-06fsp/fsp2_0/coffeelake: Add Coffeelake FSP UPD HeadersNg Kin Wai
Header files based on FSP 7.0.25.34 BUG=none BRANCH=none TEST=built coreboot without build error. Change-Id: Id92d99915bda89dd475f393a48adee60bbaee80f Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com> Reviewed-on: https://review.coreboot.org/25335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-04-06soc/cavium: import raw BDK sourcesDavid Hendricks
This imports common BDK sources that will be used in subsequent patches. The BDK is licensed under BSD and will be reduced in size and optimized to compile under coreboot. Change-Id: Icb32ee670d9fa9e5c10f9abb298cebf616fa67ad Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/25524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-04-06vc/amd/stoneyridge: Add definition for AGESA heap rebaseMarshall Dawson
AgesaHeapRebase is an optional callout that allows AGESA to use a coreboot-managed heap base address. Its internal default location is determined by AMD_HEAP_START_ADDRESS which is defined as 4 MB. Add a #define that AGESA may use once the feature is available. BUG=b:74518368 Change-Id: Id23455779b1c8c4931ad1a3122587e09ad237ecc Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-04-05intel/fsp: Update cannonlake fsp headerLijian Zhao
Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17 Offset 15h Speed report incorrectly issue. BUG=None TEST=Boot up with meowth platform and run dmidecode to see two dimm entries under Type 17. Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25378 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23vendorcode/intel: Update FSP Header files per v2.0.0Srinidhi N Kaushik
Update FSP header files to match GLK FSP Reference Code Release v2.0.0 Change-Id: I93d95e1977a4e31981e8b91882059611d91f78a5 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-22intel/fsp: Update Cannonlake FSP headerLijian Zhao
Update Cannonlake FSP header to version 7.x.2A.20, the following changes were made: 1. Add MemtestonWarmBoot option. 2. Add enable8254clockgatingonS3 option. 3. Default disable Tccoffsetlock BUG=None TEST=None Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-03-16stoneyridge: Update AGESA binary and AGESA.hRichard Spiegel
AGESA.bin was updated in the binary repo, so update the submodule pointer. Among other changes, this added a callback "AGESA_HALT_THIS_AP", which requires updated header files. BUG=b:70338633 TEST=build kahlee. Change-Id: I5a07f1c539d00aed34cfe45d6d7ef60c1dc56566 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25183 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-14intel/fsp: Update cannonlake fsp headerLijian Zhao
Update Cannonlake FSP header to revision 7.x.25.31. Following changes had been made: 1. Add PeciSxRest option. 2. Add Thermal Velocity Boost option. 3. Add VR power deliver design option. 4. Match MrcChannelSts. TEST=NONE Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6 Reviewed-on: https://review.coreboot.org/23677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12vc/amd/00670F00: Introduce S3FinalRestore helperMarshall Dawson
The Arch2008 spec describes an AmdS3FinalRestore Entry Point that coreboot has been missing. Add the helper function that can call into the blob to execute this. BUG=b:69614064 Change-Id: Ic72feb0406cd1d0d5c23e391c2464e12c9e10007 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-01vendorcode/amd/pi/00670f00: Update headers to AGESA 1.3.0.9Marc Jones
Update the shared AGESA headers to 1.3.0.9. This depends on 3rdparty/blobs/pi/amd/00670F00/ binaries updated to the same version. BUG=b:72679320 TEST=build and boot Grunt Change-Id: I783b7318e8273913f753b70f12bfe8b71274e27f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31vendorcode/intel/fsp/fsp2_0: Add CannonLake FirmwareVersionInfoHob headerSubrata Banik
Base patch to create Firmware Version Info (FVI) for CannonLake coreboot platform using CannonLake FSP new feature. Expectation is that, FSP will provide version information of all Firmware ingredient its equip with (i.e. CPU Ref Code, uCode version, MCH Ref Code, CSE Sku type, CSE version, System Agent Ref Code, OpRom Version, GOP version, PCH Ref Code version etc.) Change-Id: Ic388e036709190e8d5c5010f4ea87223291f21d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31intel/fsp: Update cannonlake fsp headerLijian Zhao
Update Cannonlake FSP header to revision 7.x.20.52. Following changes had been made: 1. Hide internal EV related options. 2. Add GT voltage override options. 3. Add PEG IMR selection. 4. Add PCH DMI ASPM options. TEST=NONE Change-Id: If186a1eb440266f1eaeb03505fe0ff4c6a521be6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-31vendorcode/intel/fsp: Remove TODOs and make use of EDK2 headerSubrata Banik
This patch ensures MemInfoHob.h file can make use of existing UEFI headers as is rather than redefining the same structure locally. TEST=Download BIOS_Version_122.3 from external github and build MemInfoHob.h without any compilation error. Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31vendorcode/intel: Add Kconfig option to get UDK_VERSIONSubrata Banik
This patch ensures if required SoC/FSP driver code can retrieve UDK version for a platform. Change-Id: I3120ce512255ed6f2a40413e8e6d8000c7285b39 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31vendorcode/intel: Add UDK2017 supportSubrata Banik
This patch includes (edk2/UDK2017) all required headers for UDK2017 from EDK2 github project using below command >> git clone https://github.com/tianocore/edk2.git vUDK2017 commit hash: 66833b2a87d98be8d81d1337c193bcbf0de47d47 Change-Id: If0d5a3fef016c67e9eed6aed9b698b3b13b930c4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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