summaryrefslogtreecommitdiff
path: root/src/vendorcode
AgeCommit message (Collapse)Author
2015-09-09verstage: use common program.ld for linkingAaron Durbin
There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin@chromium.org> Reviewed-on: http://review.coreboot.org/11516 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-26Chromeos: Remove Kconfig workaround for VIRTUAL_DEV_SWITCH warningsMartin Roth
With VIRTUAL_DEV_SWITCH moved under 'config CHROMEOS' in all of the mainboards, this is no longer needed. Change-Id: I5fbea17969f6b0c3b8a5dcd519ab9d36eb2ad6f1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11337 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-11chromeos: Allow for VB_SOURCE overridePaul Kocialkowski
One may prefer to include vboot from another directory than 3rdparty for convenience. This is especially the case in Libreboot, where 3rdparty is not checked out at all. Change-Id: I13167eb604a777a2ba87c3567f134ef3ff9610e4 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11116 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-10chromeos: vboot: Adaptations for using a separate object out directoryPaul Kocialkowski
$(obj) might be defined either as a relative or an absolute path. Thus, it has to be filtered out before adding $(top) to it (in case of an absolute path) when building vboot. It is then provided separately in CFLAGS (as an absolute path). In addition, VB2_LIB inherits $(obj), so it might also already be an absolute path, and prefixing $(top) to it doesn't apply. Thus, the absolute path to it should be passed to the vboot make command. Change-Id: I13e893ebdf22c4513ee40d9331a30ac7de8f9788 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11120 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09f10/f12: Remove whitespace from gcccar.incStefan Reinauer
:'<,'>s,\ *$,, Change-Id: I9fca0e12f02d6fff4644abacecd4a31cea64bbc1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-07vendorcode: Move AMD sources from blobs to vendorcodeMarc Jones
The AMD AGESA binaryPI sources were incorrectly committed to 3rdparty/blobs. Move them from blobs to vendorcode and fix Kconfig and Makefile.inc to match. Change-Id: I55a777553c1203464d7f7f4293b361fedcfa3283 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10982 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-05vendorcode: Fixup AGESA PI Kconfig variablesMarc Jones
The *_SELECTED Kconfig variables are not needed with the options contained within "if CPU_AMD_AGESA_BINARY_PI" introduced in e4c17ce8. It also removes the need to source and select the default prior to selecting the AGESA source or AGESA PI option. Change-Id: Iffa366f575f7f155bd6c7e7ece2a985f747c83be Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10981 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-30vendorcode: 64bit fixes for AMD CIMX SB800Stefan Reinauer
Make SB800 code compile with x64 compiler These fixes probably apply 1:1 to the other SB components in that directory. Change-Id: I9ff9f27dff5074d2faf41ebc14bfe50871d9c7f7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10573 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-30vendorcode: Port AMD Agesa for Fam14 to 64bitStefan Reinauer
Change-Id: Ic6b3c3382a6d3fdc6d716ea899db598910b4fe3e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10581 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-07-30amd/bettong: Enable fan controlWANG Siyuan
1. Use enable_imc_thermal_zone to enable fan control. 2. The ACPI method ITZE works on Ubuntu 14.04 and Windows 7 but does not work on Windows 8, so I didn't use it. After this issue is fixed, I'll add ACPI_ENABLE_THERMAL_ZONE in bettong/Kconfig. 3. Fan control works on Bettong. I used "APU Validation Toolkit" to test on Windows 8. This tool can put load to APU. The fan's behaviour is just like bettong/fchec.c defined. When the temperature is 40 Celsius, the fan start to run. Change-Id: I0fc22974a7a7cf3f6bdf5f1c66be95219a177e12 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10721 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-30AMD binary PI: add vendorcode support for fan controlWANG Siyuan
Binary PI doesn't provide fan control lib. HwmLateService.c and ImcLib.c are ported from Kabini PI. I have tested on AMD Bettong. The two files work. Change-Id: Ia4d24650d2a5544674e9d44c502e8fd9da0b55d3 Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10719 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-07-29arm, arm64, mips: Add rough static stack size checks with -Wstack-usageJulius Werner
We've seen an increasing need to reduce stack sizes more and more for space reasons, and it's always guesswork because no one has a good idea how little is too litte. We now have boards with 3K and 2K stacks, and old pieces of common code often allocate large temporary buffers that would lead to very dangerous and hard to detect bugs when someone eventually tries to use them on one of those. This patch tries improve this situation at least a bit by declaring 2K as the minimum stack size all of coreboot code should work with. It checks all function frames with -Wstack-usage=1536 to make sure we don't allocate more than 1.5K in a single buffer. This is of course not a perfect test, but it should catch the most common situation of declaring a single, large buffer in some close-to-leaf function (with the assumption that 0.5K is hopefully enough for all the "normal" functions above that). Change one example where we were a bit overzealous and put a 1K buffer into BSS back to stack allocation, since it actually conforms to this new assumption and frees up another kilobyte of that highly sought-after verstage space. Not touching x86 with any of this since it's lack of __PRE_RAM__ BSS often requires it to allocate way more on the stack than would usually be considered sane. BRANCH=veyron BUG=None TEST=Compiled Cosmos, Daisy, Falco, Blaze, Pit, Storm, Urara and Pinky, made sure they still build as well as before and don't show any stack usage warnings. Change-Id: Idc53d33bd8487bbef49d3ecd751914b0308006ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8e5931066575e256dfc2295c3dab7f0e1b65417f Original-Change-Id: I30bd9c2c77e0e0623df89b9e5bb43ed29506be98 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236978 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-23vboot: set software write protect flagDaisuke Nojiri
TEST=built for samus and veyron_jerry Change-Id: I7173f46d2ed2e323bff227a484c32c4bb6f6c828 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/11028 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-21intel/fsp_baytrail: Support Baytrail FSP Gold4 releaseYork Yang
Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION structure to include these new PCD options and initialized the setting when given in devicetree.cb. Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/10838 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-15cbfs: hardcode file alignmentPatrick Georgi
Assume that it's 64 byte. Change-Id: I168facd92f64c2cf99c26c350c60317807a4aed4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10919 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-15intel/fsp_baytrail: Remove PcdEnableLan optionYork Yang
Bay Trail SOCs do not integrate LAN controller hence Baytrail FSP has no LAN control function. Remove PcdEnableLan option from UPD_DATA_REGION structure. Change-Id: I9b4ec9d72c8c60b928a6d9755e94203fb90b658f Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/10837 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-08vboot: Don't count boot attempts if lid is closedPatrick Georgi
This can be a problem with freshly updated devices that are periodically powered on while closed (as explained in the bug report). In this case, just don't count down. In case of actual errors (where we want the system to fall back to the old code), this now means that the retries have to happen with the lid open. Bump vboot's submodule revision for the vboot-side support of this. BUG=chromium:446945 TEST=to test the OS update side, follow the test protocol in https://code.google.com/p/chromium/issues/detail?id=446945#c43 With a servo, it can be sped up using the EC console interface to start the closed system - no need to wait 60min and plugging in power to get to that state. Change-Id: I0e39aadc52195fe53ee4a29a828ed9a40d28f5e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10851 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-08vendorcode/intel/edk2: Fix EFI_PEI_GRAPHICS_INFO_HOB structureLee Leahy
Change the FrameBufferSize field from UINT64 to UINT32 to match the Platform Initialization 2.4 specification. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I28dc0608675ed5840863ecd15bd2f57e6b2f4c1d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10834 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-07x86: Drop -Wa,--divideStefan Reinauer
Fix up all the code that is using / to use >> for divisions instead. Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10819 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-30vboot: move vbnv_* sources around a bit more.Patrick Georgi
The many different places to put vboot verification in can be confusing. Instead of using libverstage (which isn't enough since those functions are sometimes called outside that, too), mention all stages where it can resides explicitly. Change-Id: I9360face822ada7018a1cfdfced8da29b347cbb4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10722 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30chromeos: push vbnv_* accessors from verstage to libverstagePatrick Georgi
That way they're available wherever the verstage code ends up, bootblock, verstage or romstage. Change-Id: I6e59a40761f95a98d96a9b72e3bbcc59caae9b1a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-30Add Kconfig flag to specify if there's a lid switchPatrick Georgi
Not all devices have a lid switch, so we need to state this somehow. Since the alternative would be to extend get_lid_switch()'s semantics to become a tri-state (open, closed, N/A), do this through Kconfig. BRANCH=none BUG=chromium:446945 TEST=none Change-Id: Icc50f72535f256051a59925a178fb27b2e8f7e55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d20a1d1a22d64546a5d8761b18ab29732ec0b848 Original-Change-Id: Ie8ac401fbaad5b5a9f1dec2b67847c81f4cc94aa Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273850 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-29vboot2: Enable VBOOT_DYNAMIC_WORK_BUFFER on x86Stefan Reinauer
Change-Id: Iaadbd52d948000d1ed46865b83bdb0f4926ca429 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10677 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-29vboot2: consolidate vboot2 buffer initializationPatrick Georgi
Instead of calling the init function to clear out vboot2 data structures in multiple places, move the function and call close to verstage_main(). Change-Id: If42e18a8e4581f22f7a7aced70ccbe3188bb0cd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10701 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-26google/chromeos: always enable VBOOT_VERIFY_FIRMWARE with CHROMEOSPatrick Georgi
Change-Id: Icc3cf64f259d4ebd7900ad91163276774e5422ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10661 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-26vboot: Init vb2 work memory area before calling verstagePatrick Georgi
Otherwise it'll determine some offsets from uninitialized data and hilarity ensues. Change-Id: I6a671987857cfd3f3cd6078aebd13dd09fc79020 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10660 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24Intel vendorcode: Add FSP_SMBIOS_MEMORY_INFO_GUIDLee Leahy
Add new GUID for FSP. BRANCH=none BUG=None TEST=Build and run on strago Change-Id: I539a59b513f67535436f581e0a79ab53f05682ca Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10587 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-23vendorcode: Use cross archiver for libagesa.a on AMD f14Stefan Reinauer
Change-Id: I61a9f65a1ac4c95096d0ff071a95984cf219caa8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10593 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2015-06-23chromeos: vpd: properly null terminate valuesStephen Barber
VPD strings are not null terminated, so we can't use strcpy on them in cros_vpd_gets. BUG=none BRANCH=none TEST=add serial_number followed by cam_calib_data to VPD on smaug; make sure that smaug boots and serial number matches exactly (no garbage) Change-Id: Id72885517b3d0b1934ba329c1ef0d89a67bd2bb4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 56bbe6688b11043360a046a250d1ea93db4d9f0e Original-Change-Id: I811dfc2f0830a91410eb69961a6565080ff78267 Original-Signed-off-by: Stephen Barber <smbarber@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280836 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: http://review.coreboot.org/10627 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-06-13vendorcode/amd: unify amdlib for binary piStefan Reinauer
Instead of having three copies of amdlib, the glue code for Agesa, let's share the code between all implementations (and come up with a versioned API if needed at some point in the future) Change-Id: I38edffd1bbb04785765d20ca30908a1101c0dda0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10507 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-13AMD Merlin Falcon: Add binary PI vendorcode filesWANG Siyuan
Add all of the PI source that will remain part of coreboot to build with a binary AGESA PI BLOB. This includes the gcc makefiles, some Kconfig, and the AGESA standard library functions. Change vendorcode Makefile and Kconfig so that they can compile AMD library files and use headers from outside the coreboot/src tree. Change-Id: Iad26689292eb123d735023dd29ef3d47396076ea Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Reviewed-on: http://review.coreboot.org/10416 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-09vboot: add new firmware indiciesAaron Durbin
Some patches landed that didn't introduce the Kconfig options for additional firmware components. Add them. Change-Id: I0a0b7f0291389d126a7c491f710618a278cfb5d7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-07Removed unused SOUTHBRIDGE_INTEL_FSP_I89XX expressionsMartin Roth
The SOUTHBRIDGE_INTEL_FSP_I89XX symbols are never defined in any Kconfig file or used anywhere in the existing coreboot tree. Removing them as unnecessary. If the southbridge code ever gets uploaded, these can be re-added at that point. Change-Id: I36f9ca8e25e08ce154d10ea9d764a73095590244 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10436 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-02assets: abstract away the firmware assets used for bootingAaron Durbin
As there can be more than one source of firmware assets this patch generalizes the notion of locating a particular asset. struct asset is added along with some helper functions for working on assets as a first class citizen. Change-Id: I2ce575d1e5259aed4c34c3dcfd438abe9db1d7b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10264 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-06-02cbfs: new API and better program loadingAaron Durbin
A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. The program loading takes advantage of those very properties by allowing multiple sources for locating a program. Because of this we can reduce the overhead of loading programs because it's all done in the common code paths. Only locating the program is per source. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9134 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-02vboot: Increase max parsed fw components to 6Furquan Shaikh
With addition of bl31 and trusty, we need to increase the number of parsed fw components in vboot to 6. CQ-DEPEND=CL:273866 BUG=chrome-os-partner:40713 BRANCH=None TEST=Compiles successfully and vboot finds trusty and bl31. Change-Id: I3597e98370bbaef4d2e563c868eed59b2e18adca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ff87fdbc7779e6ee410905d1618281411b38a93 Original-Change-Id: Ia403f895b50cc5349bb700d01f62e13c679f68f4 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273865 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10391 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-05-29UEFI: Conditionally define the ASSERT macroLee Leahy
Only define the ASSERT macro when it is not already defined. This change allows the UEFI/FSP definitions to be included with most other coreboot includes. BRANCH=none BUG=None TEST=Build and run on sklrvp Change-Id: Iccfeb83eb1e52623ae0a0fe2a96b587ce61f82d7 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-29chromeos: always enable timestampsStefan Reinauer
Timestamps should not be forced on by a subset of chipsets. However, they are a requirement on Chrome OS platforms, so have CONFIG_CHROMEOS select it. Change-Id: I408c6b17aa8721a3abec69020084174e414a8940 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/10357 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-26vboot: move to region_devicesAaron Durbin
Now that vboot is using offsets for everything remove the pass through vboot_get_region() and use region_devices as first class citizens. Change-Id: I1a86f3725e5bce38e6ca31e9641b1a8f4ac50e96 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10225 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26fmap: new API using region_deviceAaron Durbin
Instead of being pointer based use the region infrastrucutre. Additionally, this removes the need for arch-specific compilation paths. The users of the new API can use the region APIs to memory map or read the region provided by the new fmap API. Change-Id: Ie36e9ff9cb554234ec394b921f029eeed6845aee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9170 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-26vboot: use only offsets for tracking firmware componentsAaron Durbin
Because of the fmap API returning pointers to represent regions within the boot device a vboot_region structure was used to track the case where offsets could be pointers on x86 but not on !x86. Normalize this tracking to use offsets only as it provides consistency in the code. Change-Id: I63c08b31ace3bd0e66ebc17e308f87eb5f857c86 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10221 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19vboot: remove vboot_context.hAaron Durbin
The vboot_context.h file hasn't been used since commit 6d65f796db. Remove it. Change-Id: I57a6c619c6e1f57be6963da2954329bc9c007dd8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10223 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-13vboot: fix die() hang for recovery pathAaron Durbin
When we are taking the recovery path there is no slot or components to fill out. Change-Id: Ic97a247629365ef54a340c4398cb7491935edc11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10198 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-13amd/pi: Move AGESA cbfs access into the wrapperMarc Jones
The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10058 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-13vboot: indicate verstage loading on consoleAaron Durbin
There was no indication of verstage being loaded. Provide this output so that one can follow the flow from console messages. Change-Id: I67ae6bb334608fe10a4a12fe690498afaf6b8366 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10195 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-13vboot: handle RELOCATABLE_RAMSTAGEAaron Durbin
The support for RELOCATABLE_RAMSTAGE was accidentally omitted in the vboot loader. Add said support. Change-Id: I569918823253c33f698acefd6a619133543c7aef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10184 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-05-11vboot: allow for dynamic work buffersAaron Durbin
The vboot library currently relies on link-time known address and sizes of the work buffer. Not all platforms can provide such semantics. Therefore, add an option to use cbmem for the work buffer. This implies such platforms can only do verification of the firmware after main memory has been initialized. Change-Id: If0b0f6b2a187b5c1fb56af08b6cb384a935be096 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10157 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-11vboot: add vb2_working_data_size()Aaron Durbin
Instead of using the symbols directly provide a size function to provide symmetry between getting the work data and size. It also allows for an abstraction where the linker symbols may not be the only source of this information. Change-Id: I4568064a0050d118c3544ab1ea59a08eb0bad8e4 Signed-off-by: Aaron Durbi <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 19:47:44 +0000