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2020-09-09vendorcode/intel/fsp/fsp2_0/adl: Add FSP header file version 1332Subrata Banik
List of changes: 1. Select FSP_HEADER_PATH 2. Select FSP_FD_PATH 3. Select PLATFORM_USES_FSP2_2 4. Select UDK_202005_BINDING Change-Id: Ic5b09bad3c23b84c6ff6b1ea9e1dc684d7463c27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-09-08vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM definition in SystemMemoryMapHobJohnny Lin
Most of them are needed for SMBIOS type 17 creation. Tested=With FSP WW36 verified the printed hob values match with FSP hob data. Change-Id: I02f4600f1be39e2576d7c84a5a6b6672ebb7034b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08vendorcode/intel/FSP2_0/CPX-SP: update to ww36Jonathan Zhang
Intel CPX-SP FSP ww36 release has following changes: * Update FSP header version to change among FSP releases. * Add SPDRegVen field in memory map HOB, to facilitate SMBIOS type 11 (OEM strings) generation. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45100 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08vendorcode/intel/fsp/fsp2_0/cpx_sp: Set correct stack number for IOU3Johnny Lin
PSTACK2 (IOU3) should be stack number 4, mainboard uses stack number as the index to access the bus number array read by get_stack_busnos(). Without the fix it would get the wrong bus number (0xb1). Tested=On OCP Delta Lake, dmidecode -t 9 to verify slots bus number on IOU3 are correct (0xb2). Change-Id: I1c9e49bbc9a00de82d1fc67b3b4ed47e03eacdda Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3333Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3333. Previous version was 3313. Changes Include: 1. Update comments 2. Add new UPD for Gpio Override support BUG=b:166790597 BRANCH=none TEST=build and boot volteer proto2 Cq-Depend:chromium-internal:3240396,chromium-internal:2870145 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie3f0688143eef532946c7a2141909c1ac173fc2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44912 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-01{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistentSubrata Banik
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-31vendorcode/google: Add error handlingJohn Zhao
Coverity detects missing error handling after calling function tlcl_lib_init. This change checks the function tlcl_lib_init return value and handles error properly. Found-by: Coverity CID 1431994 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ib831646b6a231ad57e3bfef85b801b592d572e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-28vc/amd/fsp/picasso: Add FSP-M UPD enable_sata to 0xC7 to match FSPNikolai Vyssotski
BUG=b:162302027 BRANCH=zork Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I4b5c3b351b6232f8b0418ead47d87aaddd350668 Cq-Depend: chrome-internal:3201648 Cq-Depend: chrome-internal:3202602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44863 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt socJonathan Zhang
Intel CPX-SP FSP ww34 release added some features: a. change DDR frequency limit. b. define MRC debug message verbosity level. c. enable/disablee of PCH DCI. In addition, there are some changes to HOB data structures. Update UPD and HOB header files and adapt soc accordingly. TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27symbols: Change implementation details of DECLARE_OPTIONAL_REGION()Julius Werner
It seems that GCC's LTO doesn't like the way we implement DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than having a normal DECLARE_REGION() in <symbols.h> and then an extra DECLARE_OPTIONAL_REGION() in the C file using it, you just say DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead of the usual DECLARE_REGION()). This basically looks the same way in the resulting object file but somehow LTO seems to like it better. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-08-26vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab tableMike Banon
This unlocks 1866 MHz frequency for AMD boards of f15tn family. Tested on ASUS A88XM-E with A10-6700 and Crucial BLT8G3D1869DT1TX0. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I547d7e9ca89524d66ee0ee307de41699d991f9fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/40490 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-25vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295Ronak Kanabar
The FSP-M/S headers added are generated as per FSP v2295. Previous FSP version was 2194. Changes Include: - Update comments - UPD offset updates - add FSPS_ARCH_UPD BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3221772 Change-Id: I569987427cccefc1c5015bdabb10b41f29f2624a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-24vc/google/chromeos: load wifi_sar_defaults.hex as the main WiFi SAR CBFS sourceKevin Chiu
Each variant WiFi SAR CBFS will be added with the default name "wifi_sar_defaults.hex". so we just need to look up the default CBFS file as the WiFi SAR source. BUG=b:159304570 BRANCH=zork TEST=1. cros-workon-zork start coreboot-private-files-zork 2. emerge-zork chromeos-config coreboot-private-files-zork \ coreboot chromeos-bootimage Change-Id: Idf859c7bdeb1f41b5144663ba1762e560dcfc789 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44672 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24nb/amd/agesa: define DDR3_SPD_SIZE as a common valueMike Banon
Move a size of DDR3 SPD memory (always 256 bytes) to a common define. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-24edk2-stable202005/IntelFsp2Pkg: Add FSP*_ARCH_UPD.Ronak Kanabar
Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events and multi-phase silicon initialization. For backward compatibility the original structures are kept and new ARCH_UPD structures will be included only when UPD header revision equal or greater than 2. ref: - https://bugzilla.tianocore.org/show_bug.cgi?id=2781 BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3221772 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: I728aff1df3d361e21e4617647c4ec0e2d345a8c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-23vc/amd/fsp/picasso: add FSP-M UPD to disable the HD Audio controllerFelix Held
BUG=b:158535201,b:162302028 BRANCH=zork Change-Id: If4886591b7d73293773e4d36ec653ef42e8b2f54 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44679 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-23Revert "vc/amd/fsp/picasso: add FSP-M UPD to disable the SATA controller"Felix Held
This reverts commit 65605276a4cd08fd2e38f87cd80e3362265f9091. This patch shouldn't have been merged yet, since the issues on the FSP side aren't sorted out yet, so the FSP-side changes haven't landed yet. This byte will be used for an audio-related setting instead to have the audio settings grouped together. BRANCH=zork Change-Id: If79900f3a92fd949d7653001e1ca2faac7061e3c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44678 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-22vendorcode/google/chromeos: Introduce helper for CSE board resetKarthikeyan Ramasubramanian
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset. BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP. Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-08-20vc/amd/agesa/f16kb: raise the UDIMM Freq limit 1333MT/s values to 1600MT/sMike Banon
AMD f16kb boards are perfectly capable of working at 1600MT/s RAM speeds even with two DDR3 UDIMM modules per channel. AM1I-A only supports a single-channel operation, with at most two DIMMs per channel, so raising these limit values is required to let it and similar boards run faster. Successfully tested on AM1I-A and two Crucial BLT8G3D1869DT1TX0 UDIMMs, together with related AMD_XMP changes - also required to get a 1600MT/s with this set of modules which have only 1333MT/s at JEDEC part of SPD. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44461 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19vc/amd/fsp/picasso: update pci descriptor commentsMatt Papageorge
Update fsp_dxio_descriptor comments to be more comprehensive of the currently available data fields. Most of these are not currently utilized with Zork but may be in future projects. BUG=b:161218965 TEST=Build test Trembyle Change-Id: I8eb79fa7807dcf5b28b7b0ec60953ef857d51972 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44554 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTableMike Banon
This fix is required to avoid the division-by-zero error described at https://mail.coreboot.org/pipermail/coreboot/2014-March/077418.html while trying to run the DDR3 memory at 1866 MT/s (933 MHz). With this fix in place, ASUS A88XM-E boots fine with RAM at 1866 MT/s. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I8e7d00e362879b1247ecf2ab828936268bf9075f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40485 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17vc/amd/fsp/picasso: add FSP-M UPD to disable the SATA controllerFelix Held
BUG=b:162302027 Change-Id: Iff9a09cb59fdc16be8b4ea41303704166a97172e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-14vendercode/intel/fsp/fsp2_0/glk: Update FSP header file per v2.2.0Seunghwan Kim
Update FSP header file to match GLK FSP v2.2.0 BUG=none BRANCH=none TEST=none Change-Id: I515b4c44439e3404d3b06d587f0846457000fdb4 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marx Wang <marx.wang@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-13vc/amd/picasso/bl_uapp: Update header fileMarshall Dawson
Update to match the 0.8.6.7B release of PSP blobs. BUG=b:163857965,b:137123167 TEST=Boot Trembyle, run SST Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I728dc17ba2cfb40bc6eaaa30556a3f6bc57d18f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-13vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3313Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3313. Previous version was 3274. Changes Include: 1. Update comments 2. Fix comment typos 3. UPD offset updates BUG=b:163582213 BRANCH=none TEST=build and boot volteer proto2 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I2784c5b7c8f71c1355c1c36a27cc88080c7c2647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-08-11vendorcode/intel/fsp/fsp2_0/CPX-SP: remove non-existing PSTACKsJonathan Zhang
CPX-SP has a CSTACK and 3 PSTACKs. Clean up the HOB header file to remove reference to non-existing PSTACKs. Adjust mainboard code accordingly. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic52b01cd89fb5b3fce64686d91f017f405566acd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-08vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt socJonathan Zhang
Intel CPX-SP ww32 release has a number of bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the onboard PCIe NIC device not working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to VT-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable VT-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. [CB:44075] was submitted to enable it in coreboot. e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel not working. There is a change in IIO UDS Hob. TESTED=booted YV3 config A, and rebooted it. Access the target OS remotely. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-05vendorcode/amd/fsp/picasso Fix type 17 smbios misalignmentJason Glenesk
Add __packed to TYPE17_DMI_INFO structure to remove padding. Remove reserved fields that are no longer required. Corresponding change will also be made within fsp to pack the structure. BUG=b:154046847 TEST=Boot a trembyle with and without the reserved fields and confirm type 17 table is unchanged. Cq-Depend: chrome-internal:3194239 Change-Id: I9ba7e2a4fb82c7b0b77ee7c6c075e6211d4f6adf Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-08-02vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignmentsFelix Held
Also document the maximum nuber of lanes for the different platforms. Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44069 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31vc/amd/fsp/picasso: document DXIO lane number mappingFelix Held
Haven't found the official documentation for the DXIO lane mapping on Pollock, so I had to guess that from the working configurations used in google/dalboz and amd/cereme. Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44063 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30vc/amd/picasso/bl_uapp: Update header fileMarshall Dawson
Update to match the 0.8.5.7B release of PSP blobs. BUG=b:162057232 TEST=Boot Trembyle with, and without, new blobs. Inspect vboot using a serial-enabled bootloader Change-Id: I03f11cfc1dc8f511661def1c81421f8558dcd1f5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44041 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28vc/cavium: Fix up license headersAngel Pons
Drop a leading blank line in the license header comment. Change-Id: Ic3d7568303f9d816a8727a2960270e7667d41104 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-07-26amd/picasso: rework USB2 PHY tune parameter handlingFelix Held
BUG=b:161923068 Change-Id: I67f23c0602e345fbd806e661a4462cf07f93ef64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24vc/amd/fsp/picasso: update UPD headerFelix Held
A new version of UPD headers generated from the FSP tree. This adds UPDs for downcoring and increases the number of DXIO descriptor slots. BUG=b:161152720 TEST=SATA on Mandolin works now. Cq-Depend: chrome-internal:3175393 Change-Id: I1e27597e22af4df65d206a38b67c4920298b30b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43659 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23amd/picasso: rename PCIe descriptor to DXIO descriptorFelix Held
Most of the DXIO descriptors are used to configure PCIe engines and lanes, but on Picasso system some of the DXIO lanes can also be configured as SATA or XGBE ports. Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23vc/amd/fsp/picasso: add logical to lane number in port descriptor structFelix Held
The lane numbers in the PCIe/DXIO descriptor are the logical and not the physical ones, so add logical to the corresponding field names of the fsp_pcie_descriptor struct. Change-Id: I7037fed225119218e87593932815aff815e83ff8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-23soc/intel/xeon_sp/cpx: display SystemMemoryMapHob fieldsJonathan Zhang
SystemMemoryMapHob is necessary for SMBIOS type 17 among other things. It is a fairly large structure, so the pointer to the data instead of the structure itself, is included in the HOB. Use pointer to SystemMemoryMapHob structure to interpret SystemMemoryHob HOB body. Adjust the structure definition to match with CPX-SP ww28 release. Display more fields to ensure the structure definition is correct. TEST=Boot DeltaLake server, and check field values of SystemMemoryMapHob to make sure they are correct: 0x7590a090, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION f8870015-6994-4b98-95a2bd56da91c07f: FSP_SYSTEM_MEMORYMAP_HOB_GUID ================== MEMORY MAP HOB DATA ================== hob: 0x777f7000, structure size: 0x6c88 lowMemBase: 0x0, lowMemSize: 0x20, highMemBase: 0x40, highMemSize: 0x5d0 memSize: 0x600, memFreq: 0xb76 NumChPerMC: 3 SystemMemoryMapElement Entries: 2, entry size: 16 memory_map 0 BaseAddress: 0x0, ElementSize: 0x20, Type: 0x1 memory_map 1 BaseAddress: 0x40, ElementSize: 0x5d0, Type: 0x1 BiosFisVersion: 0x0 MmiohBase: 0x80000 0x777f7000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ ... Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I271bcbd6030276b8fcd99d5b4f2c93f034dd9b52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43336 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22vc/amd/fsp/picasso: mark remaining UPD header structs as __packedFelix Held
Change-Id: I5a97de69bfda201e039587c67037bfb93ca16c15 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43658 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3274Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3274. Compared to the current version 3197, v3274 adds most of the legacy UPDs in both FSPM and FSPS. BUG=b:159151231 BRANCH=none TEST=build and boot volteer proto2 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Id3f957aa9d9ad9710a3c930717c22f485699315e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43473 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15amd/picasso: rework DXIO and DDI UPD handlingFelix Held
Turning the DXIO and DDI descriptor fields in the FSP_S_CONFIG struct into arrays allows to properly iterate over the fields. BUG=b:158695393 TEST=Mandolin still boots. Change-Id: I85debe4d52399e933768b89b665ff10c9f7779f8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15vc/amd/fsp/picasso: replace #pragma pack(1) with __packed attributeFelix Held
Forgetting to add the #pragma pack() at the end of the header file can lead to hard to debug breakage, so get rid of the #pragma pack usage and add a __packed to the structs that need to be packed which has less possibly unwanted side effects. Since commit d44221f9c8f3686e040ff9481829315068b321a3 coreboot always includes commonlib/compiler.h which provides __packed. TEST=Timeless build results in identical binary. Change-Id: Icc53168f4fbc3a63a859f686b18e7023d225f8d2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-12soc/intel/xeon_sp/cpx: use HOB_TYPE_GUID_EXTENSION to interpret platform HOBsJonathan Zhang
Platform HOBs (in particular IIO_UDS and MemoryMap HOBs) are of HOB type HOB_TYPE_GUID_EXTENSION, therefore they do not have resource structure. Remove the erroneous code related to resource structure. Remove unnecessary function prototypes from header files, and define them as static in hob_display.c. Since we have the HOB pointer, there is not need to search HOB by GUID. Remove unnecessary calling of fsp_find_extension_hob_by_guid(). Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: Ib99bce39e6eb2aeb95242dfba36774653bbe91fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/43335 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12vc/amd/fsp/picasso: add DMI data structure definitionsAaron Durbin
Provide the data structures for parsing SPD information supplied by FSP. BUG=b:160947978 Change-Id: If847646625448547599018a823712d5c14e4bd76 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43350 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12vendocode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww28 release and adapt socJonathan Zhang
CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX. Also update IIO UDS HOB definition file accordingly. Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG. Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel is that they will converge to use FSPM_CONFIG over time. So both will co-exist for some time. Today coreboot common code expects FSP_M_CONFIG. Accomodate this situation in FspmUpd.h. The CPX-SP soc code is updated accordingly. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-10vc/amd/pi/00660F01: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I14c575ac20cd94af1cfbb1204e2923149ef2920d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43259 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09vc/amd/agesa/f15tn: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I9ceb37186e3622f2eac37393fa7ac5ced8efadf3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43258 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09vc/amd/fsp/picasso: add comment on logical lane numbers in descriptorFelix Held
The expected lane numbers in the fsp_pcie_descriptor struct are the logical and not the physical ones. Change-Id: I14166bbd397a9e5f5c5370717e039b9e71cbdb07 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43311 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt socJonathan Zhang
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also update memory map HOB definition file accordingly. The CPX-SP soc code is updated to direct FSP log to SOL. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194Ronak Kanabar
The FSP-M/S headers added are generated as per FSP v2194. BUG=b:159193895 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: TBD Change-Id: I0cd84fdb0089bf8ea3f4440e89fdee7f11119751 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42471 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 17:39:42 +0000