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2018-01-31device/pci_rom: Write _ROM method for VGA devicesPatrick Rudolph
Write _ROM method and store PCI Option ROM in CBMEM. Allows an EFI compatible OS to retrieve the Option ROM without the need to access the PCI BAR. As the Option ROM is no longer present in the legacy VGA area it's required for mobile platforms. On hybrid devices, like Lenovo Thinkpads supporting NVIDIA Optimus it's the only way to retrieve the Option ROM, even with legacy BIOS, as there's no PCI BAR to map. Tested on: * Lenovo T530 * Linux Kernel 4.13.7 * nouveau Change-Id: I548b730fb64833083cc05af5b21dd6959804224b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31arch/x86/acpigen: Add generator for _ROMPatrick Rudolph
Generate ACPI AML code for _ROM method. This function takes as input ROM data and ROM length. Arguments passed into _DSM method: Arg0 = Offset in Bytes Arg1 = Bytes to return Example: acpigen_write_rom(0xdeadbeef, 0x10000) AML code generated would look like: Method (_ROM, 2, NotSerialized) // _ROM: Read-Only Memory { OperationRegion (ROMS, SystemMemory, 0xdeadbeef, 0x00010000) Field (ROMS, AnyAcc, NoLock, Preserve) { Offset (0x00), RBF0, 524288 } Local0 = Arg0 Local1 = Arg1 If (Local1 > 0x1000) { Local1 = 0x1000 } If (Local0 > 0x00010000) { Return (Buffer (Local1) { 0x00 }) } If (Local0 > 0x0f000) { Local2 = 0x10000 - Local0 If (Local1 > Local2) { Local1 = Local2 } } Name (ROM1, Buffer (Local1) { 0x00 }) Local1 *= 0x08 Local0 *= 0x08 CreateField (RBF0, Local0, Local1, TMPB) ROM1 = TMPB /* \_SB_.PCI0.GFX0._ROM.TMPB */ Return (ROM1) /* \_SB_.PCI0.GFX0._ROM.ROM1 */ } Change-Id: Ie118b15257295b7133c8e585c0fd5218249dec8d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-31soc/intel/cannonlake: CannonaLake make use of FVI informationSubrata Banik
Select DISPLAY_FSP_VERSION_INFO Kconfig to get all required firmware information right after FSP-S. TEST=Display FW information as below >> Display FSP Version Info HOB Reference Code - CPU = 7.1.20.52 uCode Version = 0.0.0.16 Reference Code - ME 11.0 = 7.1.20.52 MEBx version = 0.0.0.0 ME Firmware Version = Consumer SKU Reference Code - CNL PCH = 7.1.20.52 PCH-CRID Status = Disabled CNL PCH H A0 Hsio Version = 2.0.0.0 CNL PCH H Ax Hsio Version = 9.0.0.0 CNL PCH H Bx Hsio Version = 5.0.0.0 CNL PCH LP Ax Hsio Version = 13.0.0.0 CNL PCH LP B0 Hsio Version = 7.0.0.0 CNL PCH LP Bx Hsio Version = 6.0.0.0 CNL PCH LP Dx Hsio Version = 2.0.0.0 Reference Code - SA - System Agent = 7.1.20.52 Reference Code - MRC = 0.5.1.19 SA - PCIe Version = 7.1.20.52 SA-CRID Status = Disabled SA-CRID Original Value = 0.0.0.0 SA-CRID New Value = 0.0.0.0 Change-Id: Ibfcac0002998e8a6594bb6dfc68b2577f62ddbff Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23387 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31drivers/intel/fsp2_0: Add support to display FSP version info HobSubrata Banik
This patch locates FSP FVI hob in order to extract all firmware ingredient version information. So far this feature is only supported for CannonLake SoC onwards. Change-Id: Ib749e49a9f263d85947b60d4c445faf8c37f5931 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23386 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31vendorcode/intel/fsp/fsp2_0: Add CannonLake FirmwareVersionInfoHob headerSubrata Banik
Base patch to create Firmware Version Info (FVI) for CannonLake coreboot platform using CannonLake FSP new feature. Expectation is that, FSP will provide version information of all Firmware ingredient its equip with (i.e. CPU Ref Code, uCode version, MCH Ref Code, CSE Sku type, CSE version, System Agent Ref Code, OpRom Version, GOP version, PCH Ref Code version etc.) Change-Id: Ic388e036709190e8d5c5010f4ea87223291f21d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31intel/fsp: Update cannonlake fsp headerLijian Zhao
Update Cannonlake FSP header to revision 7.x.20.52. Following changes had been made: 1. Hide internal EV related options. 2. Add GT voltage override options. 3. Add PEG IMR selection. 4. Add PCH DMI ASPM options. TEST=NONE Change-Id: If186a1eb440266f1eaeb03505fe0ff4c6a521be6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-01-31vendorcode/intel/fsp: Remove TODOs and make use of EDK2 headerSubrata Banik
This patch ensures MemInfoHob.h file can make use of existing UEFI headers as is rather than redefining the same structure locally. TEST=Download BIOS_Version_122.3 from external github and build MemInfoHob.h without any compilation error. Change-Id: Ic1e0ad94d8e40ac2aefe9fbcea7d684a97c864b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31drivers/intel/fsp2_0: Make use of Resource Type macro from EDK codeSubrata Banik
Users are getting build error due to duplicate macro definitions of same resource type between fsp driver code and UEFI headers. Hence this patch ensures to refer a single source location for macro definitions to avoid compilation error. Change-Id: If022eb29550a9310b095bff6130b02fb0a25ef7a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31vendorcode/intel: Add Kconfig option to get UDK_VERSIONSubrata Banik
This patch ensures if required SoC/FSP driver code can retrieve UDK version for a platform. Change-Id: I3120ce512255ed6f2a40413e8e6d8000c7285b39 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driverSubrata Banik
Now SOC code can select the require UDK support package for any platform going forward with FSP2.0 model. Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-31vendorcode/intel: Add UDK2017 supportSubrata Banik
This patch includes (edk2/UDK2017) all required headers for UDK2017 from EDK2 github project using below command >> git clone https://github.com/tianocore/edk2.git vUDK2017 commit hash: 66833b2a87d98be8d81d1337c193bcbf0de47d47 Change-Id: If0d5a3fef016c67e9eed6aed9b698b3b13b930c4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-31mb/google/poppy/variants/nautilus: Add gpio-keys ACPI node for PENHFurquan Shaikh
This change uses gpio_keys driver to add ACPI node for pen eject event. BUG=b:71329519 TEST=Verified using evtest that pen eject event results in events as expected. Change-Id: Ib293c2ca532c8ed9e2587143b1a69300cd9fa4e9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-31drivers/gpio_keys: Add driver for handling gpio-keysFurquan Shaikh
This change adds the required device node in SSDT for defining gpio-keys/gpio-keys-polled. Currently, it supports only one gpio-key per device node. BUG=b:71329519 TEST=Verified by adding details to devicetree that device node is added to SSDT: Device (PENH) { Name (_HID, "PRP0001") // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionInputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x002B } }) Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "compatible", "gpio-keys" } }, ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), Package (0x01) { Package (0x02) { "button-0", "EJCT" } } }) Name (EJCT, Package (0x02) { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x04) { Package (0x02) { "linux,code", 0x0F }, Package (0x02) { "linux,input-type", 0x05 }, Package (0x02) { "label", "pen_eject" }, Package (0x02) { "gpios", Package (0x04) { \_SB.PCI0.I2C0.PENH, Zero, Zero, One } } } }) } Change-Id: I6f11397b17d9de1c87d56f6a61669ef4052ec27b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23236 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30mainboard/google/zoombini/variant/meowth: enable FCAM_PWR_ENNick Vaccaro
Turn on power for front camera at startup in coreboot (needs to be set for factory scan). BUG=b:69011806 BRANCH=master TEST=none Change-Id: I2f31b19dfef5fe386b485dd675f0ff981288acf4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/23503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-30mainboard/google/zoombini/variant/meowth: fix SPD issuesNick Vaccaro
Fix incorrect settings in the Hynix 4GB and Samsung 2GB SPD files for meowth. BUG=b:69011806 BRANCH=none TEST=Confirm meowth with Hynix 16GB and meowth with Samsung 8GB solutions boot. Change-Id: Ia2ac564541b57647c3b605ce3389d74251490ca0 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23388 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-30mainboard/google/zoombini/variants/meowth: enable I2C bus #2Nick Vaccaro
Enable I2C #2 for display backlight controller. BUG=b:69011806 BRANCH=none TEST=none Change-Id: I5440bd4265414c55458a73e293a9931145a158cc Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-30mainboard/google/zoombini/variants/meowth: Add rev 2 gpio changesNick Vaccaro
Change GPIO settings for meowth rev 2 boards. Changes include: - GPP_B7 set to no-connect - GPP_C1 set to no-connect - GPP_D8 set to no-connect - GPP_D9 (PP3300_WLAN_EN) set as output with initial value high - GPP_E9 (DCI_CLK) set to no-connect - GPP_E10 (DCI_DATA) set to no-connect BUG=b:72202352 BRANCH=none TEST=none Change-Id: I2e6d049faaa0a70b40ceb47aaf81a81d820dd4c1 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-30mainboard/google/zoombini/variants/meowth: Fix USB OC settingsNick Vaccaro
Set USB2 port 0 & 1 to use OC2 and OC3 respectively. Previous settings were causing false overcurrent conditions as OC0 and OC1 were used for other purposes. Remove initialization of unused usb3 ports, and configure the ports we use (usb3 ports 0 & 1) to use OC2 and OC3, respectively. BUG=b:72250084 BRANCH=none TEST=Verify meowth can recognize and boot off a kernel on USB drive. Change-Id: I528b67d80a1da84e5307facb40de545089979f57 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-30mb/google/poppy/variants/soraka: Update _PSV for TCPUFurquan Shaikh
This change updates the passive setting for TCPU as per factory team recommendation. BUG=b:65467566 Change-Id: I081f63bdf811ff021c398f60efec9e6cccf462d5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23494 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30mb/google/poppy/variants/soraka: Enable mode-aware DPTFFurquan Shaikh
This change selects EC tablet event and provides trip point temperatures for tablet and non-tablet mode so that DPTF can be supported depending upon device mode. BUG=b:65467566 TEST=Verified by changing modes that the trip point temperatures are updated in the OS (/sys/devices/virtual/thermal/thermal_zone{2,3,4,5}). Change-Id: I071868982fa87821550b870a6d8050cf2a030b49 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23463 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-30soc/intel/skylake: Add support for mode-aware DPTFFurquan Shaikh
This change adds support for: 1. Handling thermal trip points change event handler based on device mode. 2. Returning thermal trip point temperatures based on the device mode. BUG=b:72554519 Change-Id: Ife48af76ceb7a39abd1fac8ef1f77db7e65ab43e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-30chromeec: Decouple EC tablet event and TBMC deviceFurquan Shaikh
This change decouples EC tablet event and TBMC device by guarding TBMC definition and notification using EC_ENABLE_TBMC_DEVICE. It allows mainboards to use tablet events without having to define a TBMC device. BUG=b:72554519 Change-Id: Ie38b6d68486e8e644dd0d6d406def3ae7fdb5152 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-30drivers/i2c/tpm: Add irq_gpio support to tpm.Justin TerAvest
Grunt (a amd-stoneyridge based platform) uses a GPIO to interface with the tpm. This change allows devicetree entries to use a irq_gpio entry to describe the interface with the TPM. BUG=b:72655090 Change-Id: I08289891408d7176f68eb9c67f7a417a2448c2de Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-30mb/google/kahlee: correct comments in baseboard gpio.cAaron Durbin
The gpios for 147 and 148 are connected to PCH_I2C_HUB_SCL and PCH_I2C_H1_TPM_SDA, respectively. Fix the comment. BUG=b:64140392 Change-Id: Ibebf6ce7d9fb26276b12b9c9844c260413f0337e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30mb/google/kahlee: mark h1 bus as early init for gruntAaron Durbin
Since the h1 i2c bus is required for verstage mark the bus as needing to be initialized early. That way, the bus is initialized in bootblock prior to verstage. BUG=b:70232394,b:69250772 Change-Id: Ice8525e08ccb438bc468d4c8bd311f72eddc7eb6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30soc/amd/stoneyridge: initialize i2c buses marked as early initAaron Durbin
Initialize the i2c buses that are marked as early init in the device tree. BUG=b:70232394,b:69250772 Change-Id: Iced1797f3bb4765646736c423b081cdc33c12a48 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30soc/amd/stoneyridge: fix gpio_acpi_path()Aaron Durbin
The path for the GPIO devices needs to be '\_SB', not '\SB'. Fix the path so that it references the system bus. BUG=b:72121803 Change-Id: I7c6c38ecea0f8f95ff52b3390f92c5b7e79bcd6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23501 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30soc/amd/stoneyridge: use new host controller programmingAaron Durbin
The SPI controller on stoneyridge apparently has a large fifo and an alternate method for programming the controller. The fifo is directly accessible as well as the rx and tx pointer in addition to the execute bit. Remove the unneeded #defines and program the host controller with the above changes in mind. In addition, add debug hooks to the driver so one can dump the state of the controller when in operation. The time it took to read 4KiB of flash in the elog driver went from 20593 microseconds to 5693 microseconds on cdx03/kahlee. BUG=b:65485690 Change-Id: Ie7ea9d18cef5511686700ad9b2b9fdfeb6d5685b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23493 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30soc/amd/stoneyridge: utilize full SPI flash controller fifoAaron Durbin
The spi flash host controller has a dedicated register for the opcode. Therefore, indicate to the spi subsystem that the opcode size should not be taken into account when determining maximum payload size in spi_crop_chunk(). This allows the full use of the fifo when doing transfers. BUG=b:65485690 Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23492 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-30drivers/spi: support cmd opcode deduction for spi_crop_chunk()Aaron Durbin
spi_crop_chunk() currently supports deducting the command length when determining maximum payload size in a transaction. Add support for deducting just the opcode part of the command by replacing deduct_cmd_len field to generic flags field. The two enums supported drive the logic within spi_crop_chunk(): SPI_CNTRLR_DEDUCT_CMD_LEN SPI_CNTRLR_DEDUCT_OPCODE_LEN All existing users of deduct_cmd_len were converted to using the flags field. BUG=b:65485690 Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23491 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-29google/scarlet: Add initialization sequence for Innolux P097PFG panelLin Huang
Innolux didn't deliver a working init sequence yet for devices without OTP programming. The sequence in this change has been derived from a register dump of a mostly working panel with OTP. It is not meant to be final, but to make devices with unprogrammed OTP work, while Innolux is figuring out a proper sequence. There is a known issue with an artifact line in the lower third of the display. Change-Id: I7096506208e4cb29c5f31a7ac502231a6c23ac92 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-29rockchip/rk3399: Support LONG_WRITE type in MIPI DSILin Huang
Some panels need to transfer initial code, and some of them will be over 3 bytes, so support LONG_WRITE type in driver. Refactor mipi dsi transfer function to support it. Change-Id: I212c14165e074c40a4a1a25140d9e8dfdfba465f Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/23299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-01-29google/fizz: Adjust PL2 and PsysPl2 values for power lossShelley Chen
Set PsysPl2 values to 90% of max adapter power for all types of adapters (typeC and barrel jack) to account for a 10% power loss from the adapter to the soc. BUG=b:71594855 BRANCH=None TEST=reboot device and make sure Pl2 and PsysPl2 MSRs are properly set with iotools rdmsr command on both U42 and U22 skus with both typeC and barrel jack power adapters. Change-Id: I8425c6d4d669449eccb9324ff58ff6d1662c5c43 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-29mb/google/kahlee: Fix I2C bus 1 timing for GruntJustin TerAvest
I measured the rise and fall times for I2C bus 1 from userspace manually, using "i2cdetect 1" called from userspace and an oscilloscope. This commit fixes the values there to reflect reality. BUG=b:72442912,b:70232394 Change-Id: I4f593cb2674006060cad9a77753c23f7d9828c9b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23459 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-29intel: Prepare registers so Windows drivers are happierPatrick Georgi
Change-Id: I12ebed30de4df9814ccb62341c7715fc62c7f5b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/23431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-28soc/intel/denverton_ns: Rename HARCUVAR macros to DENVERTONJulien Viard de Galbert
Harcuvar is the board name, Denverton is the SoC. So macros in files under soc/ should be named after the SoC not the board. Change-Id: I1c7d5b93fba386b8e9bd86cf599508e642e21a75 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shine Liu <shine.liu@intel.com> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-28amd/stoneyridge: Add NV storage to ramtopMarshall Dawson
The scratch registers in northbridge used for storing the top of cacheable memory are volatile. Use the BiosRam storage in the FCH instead. TEST=Suspend and resume Kahlee with complete S3 patch stack BUG=b:69614064 Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26drivers/spi/spi_flash: honor spi controller fifo size for readsAaron Durbin
The spi_flash_cmd_read_fast() and spi_flash_cmd_read_slow() were just passing full size buffers to the spi controller ops. However, the code wasn't honoring what the spi controller can actually perform. This would cause failures to read on controllers when large requests were sent in. Fix this by introducing a spi_flash_cmd_read_array_wrapped() function that calls spi_flash_cmd_read_array() in a loop once the maximum transfer size is calculated based on the spi controller's settings. BUG=b:65485690 Change-Id: I442d6e77a93fda411cb289b606189e490a4e464e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-26soc/intel/cannonlake: Add Cannonlake D0 support in mpinit and reportLijian Zhao
Both early platform information reporting in bootblock and common code CPU driver will add support for cannonlake D0 stepping processor. BUG=None TEST=Boot up system with D0 stepping CPU installed, check serial log that can display as D0 stepping. Change-Id: I76ee974ee027100d7853a110f95b1601987492e4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26soc/intel/apollolake: select NO_UART_ON_SUPERIORavi Sarawadi
If not, legacy COM ports will be enumerated by kernel and console will not work. localhost ~ # cat /proc/tty/driver/serial serinfo:1.0 driver revision: 0: uart:16550A port:000003F8 irq:4 tx:0 rx:0 1: uart:16550A mmio:0xC112D000 irq:4 tx:764 rx:0 RTS|DTR 2: uart:16550A mmio:0xC112F000 irq:6 tx:0 rx:0 3: uart:unknown port:000002E8 irq:3 With this fix: 0: uart:16550A mmio:0xC112D000 irq:4 tx:0 rx:0 1: uart:16550A mmio:0xC112F000 irq:6 tx:858 rx:42 RTS|DTR 2: uart:unknown port:000003E8 irq:4 3: uart:unknown port:000002E8 irq:3 Change-Id: Iac5bf65900e090d4e785e0cd828272ebff209458 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/23219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-26amd/stoneyridge: Convert BiosRam access to MMIOMarshall Dawson
Change the BiosRam read/write functions to use the fixed MMIO range at 0xfed80500. This is faster than two accesses per byte when using I/O 0xcd4/0xcd5. Note that BiosRam may only be accessed byte-by-byte. It does not decode normally. Change-Id: I9d8baf2bd5d9d48a87bddfb6a0b86e292a8fdf7d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23436 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-01-26nb/intel/sandybridge: Use common mrc cache functionsArthur Heymans
This uses the functions in include/mrc_cache.h instead of northbidge/intel/common/mrc_cache.h Tested working on Lenovo Thinkpad x220, mrc_cache region gets written and S3 resume still works fine. Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26ec/google/chromeec: Add _PRW property to CREC deviceFurquan Shaikh
This change adds _PRW property to CREC device that allows Linux kernel to identify CREC as a wakeup source. BUG=b:69118395 TEST=Verified following steps: 1. Under sys devices for CREC: "echo enabled > wakeup" 2. Lid close/Lid open -- Verified that wakeup_count increases 3. Mode change -- Verified that wakeup_count increases Change-Id: Ib0a687e171c7e5c81325b39f47c9a2462553fe3e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-01-26mb/*/*/cmos.layout: Fix the values for the console levelArthur Heymans
Fix the values that were off by one. This was discovered when using postcar stage that prints with debuglevel BIOS_NEVER. Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-26smbios: handle DIMM of 32G or moreJulien Viard de Galbert
According to SMBIOS Reference Specification (1) section 7.18.5 Memory Device — Extended Size When the size cannot be represented in the size field, it must be set to 0x7fff and the real size stored in the extended_size field. 1: https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.1.pdf Change-Id: Idc559454c16ccd685aaaed0d60f1af69b634ea2e Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-01-26mb/google/poppy/variants/soraka: Configure unused pins as NCFurquan Shaikh
This change configures unused pins as not connected. Change-Id: I6779d9fba73da8fb2faa08ad5d2236b813105720 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23416 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-26mb/google/poppy/variants/nautilus: Update camera power enable GPIOsFurquan Shaikh
This change updates the camera power enable GPIOs as per the latest schematics. With this update, since one of the enable GPIOs is using a UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that FSP-S does not re-configure the UART0 GPIOs. BUG=b:68964831 Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26mainboard/google/zoombini/variant/meowth: add PCH_WP_ODNick Vaccaro
Configure GPP_H12 as an input for PCH_WP_OD. BUG=b:72202352 BRANCH=none TEST=none Change-Id: Ie5b60644a24d745add4d0d38c1421974b8a0017b Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/23389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-26soc/amd/stoneyridge: fix compilation errorAaron Durbin
The following two patches were independent, but they were merged together. However, the first one changed the API that the second was originally was written against. Fix build. b94a2750 (i2c/designware: reduce API complication for bus config) 13101a7b (soc/amd/stoneyridge: Add I2C devicetree support) BUG=b:72121803 Change-Id: I3678a8f414572dd2227c42ce5585daf6bc933df5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23445 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25soc/amd/stoneyridge: remove dependence on TSCAaron Durbin
The TSC rate is empirically swinging during early boot. That leaves timestamps and udelay()s to not be correct. To rectify this stop using TSC for all of these time sources. Instead use the performance TSC which is at a fixed 100MHz clock. That provides stable time sources and legit timestamps. BUG=b:72378235,b:72170796 Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-25 18:35:46 +0000