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2019-07-13mb/google/octopus: Add custom SAR values for BluebirdSeunghwan Kim
Bluebird needs to use different SAR values than Casta. Bluebird sku id is 2. CQ-DEPEND=CL:*1435310 BUG=b:129725065 BRANCH=octopus TEST=build Change-Id: I107a8519832fcf906b94f958a3dc508d19bb4727 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34080 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13intel/i945: Fix udelay() prototypesKyösti Mälkki
Change-Id: Ia157c6417bdd9c4ffbdf07683c51d0680e9356c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-13intel/haswell: Replace monotonic timerKyösti Mälkki
Remove implementation of 24 MHz clock, available only on Haswell ULT SKUs. Use TSC_MONOTONIC_TIMER instead for all boards. Change-Id: Ic4aeb084d1b0913368f5eaa46e1bd68411435517 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-13soc/rockchip/rk3288/include/soc: Add missing include <types.h>Elyes HAOUAS
Change-Id: Ibde48d7cff582c91f55ad5f1328aac64d018b3c5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34235 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13soc/qualcomm: Remove unneeded '#include <lib.h>'Elyes HAOUAS
Change-Id: I39db73014c0a4456750210c002787abf9bc79fce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-13console/Kconfig - only print UART addresses for I/O based UARTsMartin Roth
It doesn't make sense to print these values for memory-mapped UARTs. Change-Id: Ie2d9cf95f0b0fdcf601e74de799b1390c08f2335 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-13fit_payload: Always set DT sizeJulius Werner
CB:32870 changed FIT loading code to make an FDT mandatory (because the platforms that can use FIT images always need an FDT). Remove one left-over conditional that is now dead code. Found by Coverity. Change-Id: Ia7765d45f068ab4bdc720ea7ae87dcc62a4b7d3d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-13soc/intel/cannonlake: Remove unused header files from southbridge.aslAamir Bohra
Change-Id: I1f970db22f87e8eba0129ca049f75d16539644a5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-13soc,southbridge/intel: Avoid preprocessor with HAVE_SMI_HANDLERKyösti Mälkki
Change-Id: Id375999adad71d95d4968398e90bc3c07f65ea83 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34254 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13intel/fsp_rangeley: Avoid preprocessor with HAVE_SMI_HANDLERKyösti Mälkki
Change-Id: Id9abc239a92fa7d3e29738f08f2ccdaf3232dfb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-13drivers/elog: Fix ELOG_GSMI dependencyKyösti Mälkki
SMM_TSEG is a qualifier between TSEG and ASEG only, while HAVE_SMI_HANDLER currently tells if SMM will be installed. Move rest of the file under same 'if ELOG' block. Change-Id: I620d3ce5aa9632d862d6480922144f002cf6423b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34195 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13cpu/x86: Move smm_lock() prototypeKyösti Mälkki
The function implementations are in local platform scopes. Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13intel/e7505,i82801dx: Fix SMM_ASEG lockKyösti Mälkki
In our codebase, this is only coupled with intel/e7505. The PCI registers reference here were for intel/i945. Also aseg_smm_lock() was previously not called. Change-Id: I21d991c8c2f5c2dde1f148fd80963e39d9836d3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34149 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSPNico Huber
We got rid of the dangerous reconfiguration of arbitrary pads in coreboot, but FSP still overrode that. Make sure that it doesn't enable a UART for debug output when it isn't configured in core- boot. This, again, shows how dangerous it is to leave any FSP UPD at its binary default. Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-12arch, include, soc: Use common stdint.hJacob Garber
There are only minimal differences between the architecture specific stdint.h implementations, so let's tidy them up and merge them together into a single file. In particular, - Use 'unsigned long' for uintptr_t. This was already the case for x86 and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64 used 'unsigned long long'. This change allows using a single integer type for uintptr_t across all architectures, and brings it into consistency with the rest of the code base, which generally uses 'unsigned long' for memory addresses anyway. This change required fixing several assumptions about integer types in the arm code. - Use _Bool as the boolean type. This is a specialized boolean type that was introduced in C99, and is preferrable over hacking booleans using integers. romcc sadly does not support _Bool, so for that we stick with the old uint8_t. - Drop the least and fast integer types. They aren't used anywhere in the code base and are an unnecessary maintenance burden. Using the standard fixed width types is essentially always better anyway. - Drop the UINT64_C() macro. It also isn't used anywhere and doesn't provide anything that a (uint64_t) cast doesn't. - Implement the rest of the MIN and MAX numerical limits. - Use static assertions to check that the integer widths are correct. Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-12src: Add missing include <device/pci_ops.h>Elyes HAOUAS
Change-Id: Iae73fc1557fb310dacbbf8bc486dc3cc5249d9e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33526 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12mb/siemens/mc_apl3: Enable LPSS UART 1Mario Scheithauer
By setting the GPIOs 42 and 43 to native function 1 the LPSS UART 1 is activated. Change-Id: I74abd1b6fb5459cf11a5bdee182c99462f613b7a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-12vendorcode/amd/agesa/f15tn: Fix condition that has identical branchesElyes HAOUAS
This fixed function is never used. Change-Id: Ia004756a0b301278f813067ab0ea580c5ea837d3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34225 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12device/oprom: Replace uses of dev_find_slot()Kyösti Mälkki
The call to dev_find_slot() may return PCI devices that are disabled or unaccessible, as PCI enumeration does not remove nodes from all_devices linked list. Use PCI topology search instead. Change-Id: I00233177e5572ca79002a7d141cda1b94b966330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34083 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12pci_ids: Drop a block of unused, redundant definitionsNico Huber
These didn't align with the usual naming conventions and contained some errors beside. Change-Id: I45033d4cb998a85fc0bec00c54e207226f42de4e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-12soc/intel/common: Add Coffee Lake H 6+2 Xeon graphics idNico Huber
Change-Id: Ibf72a8db2e4292e5d5bb67b8778e1d1ebfa19632 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34164 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12soc/intel/common: Add CM246 LPC device idNico Huber
Change-Id: Ic57ccf48988afbbba256172a7540bb02b88d1bbd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34163 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-12device/pci: Declare pcidev_path_on_bus()Kyösti Mälkki
It is recommended to never reference PCI busses using a static number. There is exception with OPROM execution, where we want to translate the bus number captured from the actual IO operation into a matching device node in the devicetree. Change-Id: I733c645ac5581c000b4cd6cdc05829cd039324d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-12device/pci: Replace use of dev_find_slot() for IRQsKyösti Mälkki
Change-Id: I48c0de73338430282ce1a4442bbeb7c867dc174c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-12Kconfig: Remove HAVE_RAMSTAGE dependency from RELOCATABLE_RAMSTAGESubrata Banik
CONFIG_RELOCATABLE_RAMSTAGE is something more than ramstage specific kconfig hence its better to remove HAVE_RAMSTAGE dependency till stage_cache cleaner implementation lands here. Change-Id: I3c238d727dc13014e2b77544d05099be95c22bab Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-11cpu/x86: Declare smi_release_lock() staticKyösti Mälkki
Change-Id: I535ff1b16b1fa7c3c8c14b2be7eac32568f16077 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34194 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch: Update AC/DC loadline valuesRizwan Qureshi
Update the AC/DC loadline values for all domains. Using the same values as in arcada. BUG=None BRANCH=None TEST=Build and Boot hatch EVT Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11mb/asus/p8h61-m_pro: Add comment about PCH GPIO46Angel Pons
GPIO46 is wired to a tiny switch on the board labelled "GPU Boost". Since coreboot could make use of it, add a comment about it on gpio.c. Change-Id: I0efa85e6d8235711521b10e56b7c89a25c4b2b7f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-11mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix GPIO_168Mario Scheithauer
This GPIO is corrected with reference to the Apollo Lake SoC EDS Vol 4 revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be used in Function 0 (GPIO) mode. Change-Id: I98628ade3a1e19730ca6e6b4a63c28e6816176ce Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-11mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed modeMario Scheithauer
We need to reduce the eMMC bus speed for these Apollo Lake mainboards because of a limitation on Intel side for industry use cases. Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-11google/kukui: Adjust LCM ID voltagesYu-Ping Wu
Currently some of the LCM ID voltage gaps are below 100mV. For example, the voltage difference between ID 2 and 3 is 503-440=63mV. To reduce the risk of misrecognition from the hardware level, the voltages are adjusted so that all the voltage gaps are larger than 100mV. The RD2 resistor values are also updated. BUG=b:136987483 TEST=emerge-kukui coreboot Change-Id: Ib5c1f927fb54d8c9579f030e42eeec5a27daaceb Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34192 Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mediatek: Fill in input_hertz to coreboot tableTristan Shieh
Set input_hertz to 26 MHz. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: I7f9c329ae5d610f2516e60f06b2ac96ebbeaa897 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-07-11board/kukui: Remove ADC tolerance from boardidHung-Te Lin
The tolerance of ADC is +-10mV, but the resistors may also introduce 1% variation, and causing the final measured voltage to vary around 5%. By the advisory from hardware team, checking the tolerance seems not really solving or helping anything so we should just ignore that and try to find best matched ID (this also aligns to what Gru did). BUG=b:136990271 TEST=Booted on Krane and no longer seeing ADC out of range BRANCH=None Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: You-Cheng Syu <youcheng@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11sdm845: Add AOP firmware supportT Michael Turney
TEST=build & run Change-Id: I9845c8638e4b905de5d6985dc9f1fddd8b1a8942 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25210 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch/variants: Fix nonworking touch padFrank_Chu
Correct ELAN Touch pad IRQ GPIO to GPP_A21 BUG=b:135507215 BRANCH=none TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33954 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch: Enable/disable GPIO clock gatingTim Wawrzynczak
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off. BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called. Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11soc/intel/cannonlake: Add GPID and CGPM methods to GPIO ASLTim Wawrzynczak
The GPID method returns the PCR Port ID of the given GPIO community. The CGPM method alters the given GPIO community's PM bits, given in Arg1. Change-Id: I098ee08573eb4f8a45d9b5ae84f2d85ce525c9b8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11soc/intel/intelblocks/gpio: Always expose GPIO PM constantsTim Wawrzynczak
These constants are needed in some ASL files, even when __ACPI__ is defined. Change-Id: I0f4f00b93d5d45794b7c9e0f72b51f3191eb3902 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34177 Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch: Enable LPIT inclusion in DSDTTim Wawrzynczak
Include the lpit.asl file in Hatch's DSDT definition. BUG=b:130764684 BRANCH=none TEST=S3 suspend/resume and S0ix entry/exit work correctly. Ran > 200 iterations of suspend_stress_test and no issues found. Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-11mb/google/hatch: Disable GPIO community dynamic clock gatingTim Wawrzynczak
The dynamic clock gating is causing boards to miss interrupts whose pulses are shorter than 4us. Disable it using FSP UPDs. BUG=b:130764684 BRANCH=none TEST=Compiles Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-11soc/intel/cannonlake: Make EC S0ix notification optional in LPITTim Wawrzynczak
Only call the \_SB.PCI0.LPCB.EC0.S0IX method if it exists. Change-Id: Idf465f8ad7cb016f3ad3d9710b46e35f66f8939b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-11mb/intel/coffeelake_rvp: Add cpu count for CFL S62Lean Sheng Tan
Increases CPU max core count to 16 for coffeelake Refresh-S Platform. TEST: boot to linux OS on CFL-S refresh Intel RVP and verified the output of cat /proc/cpuinfo shows no of processor=16. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I579ff6ae8227844741406c503d3994408ec2b617 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34156 Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11soc/intel/common: Check bios_size and window_size after MIN operationJohn Zhao
Clang Static Analyzer version 8.0.0 detects that the result of log2_ceil(bios_size) and log2_ceil(window_size) is undefined if the value of bios_size and window_size are negative. Add negative value Check for bios_size and window_size after MIN operation. Change-Id: I28577b6e0ba0ab45bb7804c17ba1f26c4b078b15 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-11mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)Furquan Shaikh
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since it needs to trigger on both edges. With GPIO IRQ, it is necessary to configure the trigger type in coreboot to match the ACPI configuration. This is because: 1. ACPI configuration is used by intel-pinctrl driver in Linux kernel to re-configure the trigger type for the pad in GPIO DW0 config register. This is done when kernel driver probes and requests irq for its device. 2. On resume from S3, the pad configuration gets reset and coreboot sets the trigger type to LEVEL. However, kernel driver does not probe again. This results in the trigger type being configured incorrectly. This change updates the GPIO configuration for GPP_H0 to set the same trigger type as advertised in ACPI for the kernel. BUG=b:132672011 TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0 works fine on boot as well as after suspend/resume. Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timerSubrata Banik
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer for better code sharing. Also ported CB:33512 for SPT and ICP PCH. Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-10console: Correct printing of hexadecimal integersJacob Garber
Commit b19946cc62 (console: Remove support for printing extra bases) truncated the digits string to only print integers of up to base 16. However, that string was also used to print the leading 'x' or 'X' for hexadecimal integers and is now too short. Fix this to prevent an out of bounds read. Change-Id: Iab6470cc88f445f074cf7c0b675346b37f3f2375 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402999 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-10sb/nvidia/ck804: Remove old debugging codeJacob Garber
These printk() statements were added in commit cdc526e582 (southbridge/nvidia/ck804: Fix boot hang on ASUS KFSN4-DRE w/ K8 CPU) when debugging another issue. They have undefined reads if ck804_num is 0 and aren't needed anymore, so drop them. Change-Id: I80b775370ac6485958948f0bff4510755a6cd2b8 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 137058{1,3} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33459 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10drivers/intel/fsp1_1/raminit.c: Always check FSP HOBsFrans Hendriks
Check for FSP HOBs is depending on CONFIG_DISPLAY_HOBS. Use the CONFIG_DISPLAY_HOBS for display HOB info only and always check HOBs. Use BIOS_ERR of printk() for FSP errors. BUG=N/A TEST=Check console output on Facebook FBG1701. Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-10arch/cpu/x86: Update AMD detectionMarshall Dawson
AMD Picasso, and later, will not use CPU_AMD_AGESA or CPU_AMD_PI. Those two symbols indicate an Arch2008 system. Add SOC_AMD_COMMON to cause cpu_is_amd() to return TRUE on Picasso. This removes an error message of "Unknown CPU". The patch also assumes AMD Family 10h and non-AGESA Family 15h devices were seeing the "Unknown CPU" message. No functionality has been verified on these devices. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I3357606c37082f3587ff91924bf7a0e0f8af9625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34146 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10mb/google/octopus: Remove LPDDR4 RAMID index 5,6 CH[1] only SKUKevin Chiu
From Intel EDS: Table 3-5. LPDDR4 Configurations CH00 CH01 CH10 CH11 "x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA" "Unpopulated" "Unpopulated" CH[1](CH10/CH11) can't use alone without CH[0] BUG=b:135498646,b:136694293 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I03af74301aad3e688c97992b37c59b20a4fff58a Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34069 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-26 20:03:19 +0000