summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2019-09-24device/mmio.h: Add bit field helpersHung-Te Lin
When accessing register with multiple bit fields, the common approach is to use clrsetbits_le32, for example: clrsetbits(&reg, (1 << 0) | (0x3 << 1) | (0x7 << 10), (1 << 0) | (0x1 << 1) | (0x5 << 10)); This hard to maintain because we have to calculate the mask values manually, make sure the duplicated shift (offset) was set correctly. And it may be even worse if the value to set will be based on some runtime values (that many developers will do a if-block with two very similar argument list), and leaving lots of magic numbers. We want to encourage developers always giving field names, and have a better way of setting fields. The proposed utility macros are: DEFINE_BITFIELD(name, high_bit, low_bit) EXTRACT_BITFIELD(value, name) WRITE32_BITFIELDS(addr, name, value, [name2, value2, ...]) READ32_BITFIELD(addr, name) Where a developer can easily convert from data sheet like BITS NAME 26:24 SEC_VIO Into a declaration DEFINE_BITFIELD(SEC_VIO, 26, 24) Then, a simple call can set the field as: WRITE32_BITFIELDS(&reg, SEC_VIO, 2); That is much easier to understand than clrsetbits_le32(&reg, 0x7 << 24, 0x2 << 24); And to extract the value: READ32_BITFIELD(&reg, SEC_VIO) That is equivalent to: (read32(&reg) & 0x3) >> 24 Change-Id: I8a1b17142f7a7dc6c441b0b1ee67d60d73ec8cc8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35463 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24mainboard/ocp/monolake: Hide internal NICAndrey Petrov
Disable root port IOU0 to which built-in NIC is attached. TEST=on OCP monolake, hide built-in NIC and make sure OS does not report built-in NIC Change-Id: I2384e7dd073355f0ced2902ac2d8418996b1c5aa Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-09-24soc/fsp_broadwell_de: Add devhide functionalityAndrey Petrov
Add function to hide IIO PCIe root ports. TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3] and make sure OS does not detect built-in NIC. Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-24emulation/qemu-i440fx: use fw_cfg_dma for fw_cfg_readHimanshu Sahdev
- configure DMA fw_cfg - add support to read using fw_cfg_dma - provide fw config version id info in logs BUG=N/A TEST=Build and boot using qemu-i440fx. Change-Id: I0be5355b124af40aba62c0840790d46ed0fe80a2 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-24mb/google/kohaku: Update DPTF parameters and TCC offset settingSeunghwan Kim
This change applies fine-tuned DPTF parameters and TCC offset setting for kohaku. Also enables EC_ENABLE_MULTIPLE_DPTF_PROFILES for tablet mode. BUG=b:137688474 BRANCH=none TEST=built and verified the setting values Change-Id: I92e268b2e07ca5a04e29bda84ddb8fc21eb23251 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-24mediatek/mt8183: Use different DRAM frequencies for eMCP DDRHuayang Duan
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps) while those with discrete DRAM can only run at 3200Mbps. This patch enables 3600Mbps for eMCP DDR for better system performance. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test passes on Kukui Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-23vendorcode/cavium: Replace use of __PRE_RAM__Kyösti Mälkki
Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-23lib/trace: Replace __PRE_RAM__ useKyösti Mälkki
Change-Id: I957be92594aced2e8465e7f94d8d42e44c3418d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35399 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-23mb/up/squared: Fill LPDDR4 dimm infoPatrick Rudolph
Fill the dimm info struct to make SMBIOS type 17 appear. TESTED=Up Squared Change-Id: I4de63362c8fea8a886594cdcf0eec48421afb605 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34564 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-23lib/fmap: Cache FMAP in cbmemPatrick Rudolph
For platform independend exposure of FMAP through a kernel module cache the FMAP in CBMEM. In addition add a pointer in coreboot tables pointing to the introduced CBMEM area. To not waste the allocated DRAM, use the cached CBMEM in RAM enabled stages if possible. Tested on qemu using https://github.com/9elements/linux/commits/google_firmware_fmap2 Tested on QEMU and Supermicro X11SSH-TF. Change-Id: I4e01c573c3edfa34dbba5fe7604d4f6e18b584d5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-22mb/gigabyte/ga-h61m-s2pv: Improve LPC decodingAngel Pons
Drop unused CNF2_LPC_EN, as there is no device which uses IO 0x4e/4f. Do not use the mainboard model to set COMA_LPC_EN. Make use of NO_UART_ON_SUPERIO instead, as it is more future-proof. Change-Id: Iac49250b0f509a42012f82db8aa85ba85559c66f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-22mb/mainboard/hatch: add spd: 8G_3200 for AkemiPeichao Wang
BUG=b:140545732 TEST=build bios and spd index set to 6, verify DUT bring up normally Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I337b0bdcd37a9c4baacccbc6786968031a41b31e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35511 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-22mb/ocp/monolake: Add vboot RO only supportPhilipp Deppenwiese
Change-Id: I28a21d64e2781af294670a94c1fc88fb81e80f9e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35492 Reviewed-by: Andrey Petrov <anpetrov@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-22mb/google/hatch: Add G2Touch Touchscreen supportWisley Chen
Add G2Touch Touchscreen support for dratini BUG=b:141281841 TEST=emerge-hatch coreboot chromeos-bootimage, and check touchscreen work. Change-Id: I0dbde7f8396da6335b22aeb4a9703336e2b862b8 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-09-22mb/facebook/watson: Enable vboot for measurementsPhilipp Deppenwiese
Signed-off-by: Philipp Deppenwiese <philipp.deppenwiese@9elements.com> Change-Id: I8287d475301aaaae736df9cc95fcd18cc04b40fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/35232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <anpetrov@fb.com>
2019-09-22sb/intel/i82870: Drop unused fileKyösti Mälkki
Change-Id: I024805769ad05f995a23669a82f5482ce3e7ae70 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-22device/cardbus: Remove unnecessary bridge_ctrl bitmaskKyösti Mälkki
The bits PARITY and SERR are set unconditionally below. Change-Id: I03f53fe7f436f8feed7b34756439077f02a85565 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
2019-09-22device/cardbus: Fix use of PCI_CB_BRIDGE_CONTROLKyösti Mälkki
Read-modify-write needs to access the same register. Numerically both used defines are 0x3e, while register implementations are not identical but only similar. Change-Id: I9348b855320f86868e2d3ef76d3b8d7a4ab7fae0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
2019-09-22device/pci: Replace add with bitwise-orKyösti Mälkki
Change-Id: I9fbefac3bef7425d6f5ea1bcc01eb21485315c36 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-22mb/supermicro/x11ssh: remove unnecessary fsp setting CdClockMichael Niewöhner
CdClock does not need to be set because the board does not use IGD. Change-Id: I6835ccdf80530f9efc6fdeb0363dcf9267f99d21 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-22soc/intel/skylake: lock down TCO on pch finalizeMichael Niewöhner
Change-Id: I5bd95b3580adc0f4cffa667f8979b7cf08925720 Signed-off-by: Michael Niewöhner <michael.niewoehner@8com.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-09-21soc/fsp_broadwell_de: Move function to get CPUBUSNO(1) into common fileAndrey Petrov
Change-Id: I189eb8ffce2f0735ad9ba603b1d96786aa00fafb Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-09-21mb/ocp/monolake: Implement bank/locator schemeAndrey Petrov
Implement Locator and Bank fields (as reported by dmidecode) to match vendor BIOS. TEST=on OCP monolake, run dmidecode tool and see that "Locator" field matches expectation. Change-Id: Ia271ff1e596ba469cf42e23d8390401c27670a27 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-21soc/fsp_broadwell_de: Use DIMM numbers relative to channelAndrey Petrov
Currently "DIMM numbers" increase monotonically for all the channels. However, commonly DIMMS are numerated on per-channel basis. This change makes numeration match the convention. TEST=on OCP monolake, run dmidecode tool and see that "Locator" field matches expectation. Change-Id: I3e7858545471867a0210e1b9ef646529b8e2a31c Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35318 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-21soc/amd/picasso: Use new common SPI codeRichard Spiegel
Use the new SPI code from common folder, delete spi.c. SPI related macros must be single defined, in southbridge.h if they are used by files other than the common SPI code, fch_spi.h if they are only used by the common SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h, because it can change between SOC. BUG=b:136595978 TEST=None, code already tested with grunt. Change-Id: I68008ce076d348adbdabf7b49cec8783dd7134b4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-21soc/amd/stoneyridge: Use new common SPI codeRichard Spiegel
Use the new SPI code from common folder, delete spi.c. SPI related macros must be single defined, in southbridge.h if they are used by files other than the common SPI code, fch_spi.h if they are only used by the common SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h, because it can change between SOC. BUG=b:136595978 TEST=Build and boot grunt using new SPI code, with debug enabled. Check output. Change-Id: I639973d993316a10daa7564462e689b2c183f536 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-21soc/amd/common/block: Create new SPI codeRichard Spiegel
Create a new SPI code that overrides flash operations and uses the SPI controller within the FCH to its fullest. Reference: Family 15h models 70h-7Fh BKDG revision 3.06 (public) BUG=b:136595978 TEST=Build and boot grunt using this code, with debug enabled. Check output. Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-21drivers/wifi/generic.c: Upper case the AML WiFi name as required by specAndrew McRae
ACPI 6.3, ASL 20.2.2 (Name Objects Encoding) states: LeadNameChar := 'A'-'Z' | '_' NameChar := DigitChar | LeadNameChar Hence, the Intel WiFi names generated in ASL are required to be upper-cased letters. BUG=b:141206986 TEST=Reflash and confirmed SSDT table has correct name. Change-Id: I803b9bc81804eec7bd5220b9dbc6ddd0bb0ecbcc Signed-off-by: Andrew McRae <amcrae@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35466 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-21vboot: extend BOOT_MODE_PCR to SHA256 bank on TPM2Andrey Pronin
With the support of various algorithms and banks in tlcl_extend(), digest_algo parameter of tpm_extend_pcr() started defining the target PCR bank in TPM2 case. The OS expects coreboot to extend the SHA256 bank of BOOT_MODE_PCR. The value that the OS expects coreboot to extend into BOOT_MODE_PCR is the SHA1 digest of mode bits extended to the length of SHA256 digest by appending zero bytes. Thus the correct value for digest_algo passed into tpm_extend_pcr() for BOOT_MODE_PCR is TPM_ALG_SHA256. This didn't matter until adding the support for multiple digest introduced by patches like https://review.coreboot.org/c/coreboot/+/33252, as tlcl_extend always used SHA256 bank before. Change-Id: I834fec24023cd10344cc359117f00fc80c61b80c Signed-off-by: Andrey Pronin <apronin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35476 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20sb/intel/common/fw: Make make aware that it needs binariesNico Huber
As we redirect all `dd` output to /dev/null (it would clutter the console otherwise), there is no error message if a binary to be added isn't found. If we add them as dependency, OTOH, `make` will complain properly. Change-Id: I40c3979b84341cb88c7e9a5084c1a97230ea5503 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33327 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20mediatek/mt8183: Support more DRAM frequency bootupHuayang Duan
Add more DRAM frequency bootup to support DRAM frequencies 1600Mbps, 2400Mbps, 3200Mbps and 3600Mbps. BUG=b:80501386 BRANCH=none TEST=Memory test passes on eMCP platform Change-Id: Ic1378ca43fb333c445ca77e7dc0844cdf65f2207 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-20mediatek/mt8183: Implement the dramc init settingHuayang Duan
This patch implements the dram init setting by replacing the hard-coded init sequence with a series of functions to support calibration for more frequencies. These functions are modified from MediaTek's internal DRAM full calibration source code. BUG=b:80501386 BRANCH=none TEST=1. Kukui boots correctly 2. Stress test (/usr/sbin/memtester 500M) passes on Kukui Change-Id: I756ad37e78cd1384ee0eb97e5e18c5461d73bc7b Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-20mb/supermicro/x11ssh-tf: correct CBFS_SIZEMichael Niewöhner
The specified CBFS_SIZE does not make sense. The boards BIOS region is 0xb00000. Correct the value. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia3014c7fd081030607790ced6bb55323086f1161 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35458 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20soc/qualcomm/ipq40xx: Remove unnecessary allocationJacob Garber
The bus variable doesn't live outside the scope of this function, and is only used as a convenient way for passing the pointers to all the sub-functions, so it doesn't need to be allocated. Put it on the stack instead. A similar fix for ipq806x was done in 0f33d8c29a (soc/qualcomm/ipq806x: Remove unnecessary allocation). Change-Id: Ibb1129b92e38a105e100f59e03d107de340b925c Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1294801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-20nb/intel/nehalem: Enabled VBOOT supportPatrick Rudolph
Tested on Lenovo T410. Change-Id: I86100be79bf2337d65b688edba34b87f3ac18cb6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-20soc/intel/common/intelblocks: Remove PAD_CFG_GPI_GPIO_DRIVER_SCITim Wawrzynczak
Intel's EDS says "1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked." Therefore, the GPI_GPIO_DRIVER_SCI option for pad configuration is meaningless, as any GPE will be masked if the GPIO driver is set as owner. Change-Id: Ia0cd0041dfc985cbe388cb89a4026038c7fb4383 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35460 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configurationTim Wawrzynczak
A closer read of the EDS indicates that when GPIO Driver mode is selected, GPIO input event updates are limited to GPI_STS only. GPI_GPE_STS updates are therefore masked, and we don't want to enable this behavior. It masks the GPE and does not allow us to see this GPE as a wake source, obscuring the reason that the system woke up. Also switch the IRQ from level-triggered to edge-triggered, otherwise the system will auto-wake from any sleep state when the pen is ejected from the garage. BUG=b:132981083 BRANCH=none TEST=Wake up system from S0ix using pen eject, verify that mosys eventlog shows GPE#8 as the S0ix wakeup source. Wake up system from S3 via pen eject, and verify that the wakeup source shows as GPE#8. Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35459 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20mb/google/hatch: override smbios manufacturer name from CBIWisley Chen
BUG=none TEST=emerge-hatch coreboot, use ectool to write oem name in CBI, and checked smbios manufacturer name. Change-Id: I9be85fbc47031d049b5bd51cfaf6232cab24e9fe Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-19sb/intel/ibexpeak: Add define for PRSTS registerAngel Pons
Change-Id: Ia9a6b0c7f2a07796f850acd2349067ba5e5eb735 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-19mb/google/drallion: add sku id base on sensor detectionEric Lai
Implementing logic base on sensor detection to determine SKU id. BUG=b:140472369 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5e71ae6b97378b78055735bbf4b6b55ffe38b978 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35366 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19mb/google/drallion: Add memory init setup for drallionThejaswani Putta
This implementation adds below support 1. Add support to read memory strap 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-19cpu/intel/common: Extend FSB detection to cover TSCKyösti Mälkki
Use the same CPUID switch block to resolve the multiplier to derive TSC from FSB/BCLK frequency. Do not return 0 as base frequency. Change-Id: Ib7f1815b3fac7a610f7203720d526eac152a1648 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31340 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19cpu/x86/lapic: Refactor timer_fsb()Kyösti Mälkki
Common apic_timer code in cpu/x86 should not depend on intel header files. Change-Id: Ib099921d4b8e561daea47219385762bb00fc4548 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34091 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASEKyösti Mälkki
To add a common tsc_freq_mhz() implementation, we need to guard againts soc-specific duplicate definitions. Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31341 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19cpu,mb,soc: Init missing lb_serial struct fieldsJacob Garber
Initialize the input_hertz and uart_pci_addr fields of the lb_serial struct to prevent later undefined reads in lb_add_serial(). This was done for exynos5420 in commit ff94e00362 (soc/samsung/exynos5420/uart.c: Init new serial struct variables), and this patch finishes the rest. Note that not all of the drivers can have the UART PCI address configured at build time, so a follow-up patch will be needed to correct those ones. Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1354778 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34548 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-19src/soc/intel/common/block/cse: Add hmrfpo related functions to cse libSridhar Siricilla
Below new functions are added: * send_hmrfpo_enable_msg() - Sends HMRFPO Enable command to CSE. This API sets ME in SEC_OVERRIDE mode. The mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks the CSE region to perfom updates to it. * send_hmrfpo_get_status_msg() - Sends HMRFPO Get Status command to CSE TEST=Verified sending HMRFPO_ENABLE & HMRFPO_GET_STATUS HECI commands on CML RVP & hatch board Change-Id: I559bc4641e12df7ed39b1c97097bf068f9a232db Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-09-18mb/google/hatch/variants/helios: Add DPTF control for ambient sensorSumeet Pawnikar
Add DPTF based thermal control for ambient sensor for CML based Helios system. Also, update other sensor names information. BUG=b:139335207 BRANCH=None TEST=Build and Boot on Helios board and check all sensor details. Change-Id: I322d53536fbdf6db70f5a24afb322d9f206eaeac Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-18mb/google/hatch/variants/helios: Update DPTF parametersSumeet Pawnikar
Update DPTF thermal temperature threshold values for CML based Helios system. This updates CPU active cooling temperature threshold to appropriate values which addresses the issue of running the Fan at lower CPU temperature as per bug. Also, added active cooling temperature thresholds for other TSR sensors. BUG=b:141087272 BRANCH=None TEST=Build and boot on Helios board to check the fan functionality. Change-Id: I5c8502f8c9e6121c18024d2a8d5a4f7680797b8d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35446 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18cpu/via/nano: Enable TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: Iea51a480fd7c696a6bbccc0b668acdbff6abffb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34203 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18cpu/qemu-x86: Enable TSC_MONOTONIC_TIMERKyösti Mälkki
Change-Id: I72afb0c0d34157d1d2d9fe4ae6704cd2502f724d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34202 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-26 12:32:41 +0000