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2018-04-10soc/amd: Add "halt this AP" callback to romstageRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, callback function AGESA_HALT_THIS_AP must be available at romstage. BUG=b:74236170 TEST=Build and boot grunt, actual test will be performed at a later patch. Change-Id: I0992b2de5856881c19191ec4f637168727686524 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25527 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mainboard: Make OemCustomize.c available at romstageRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, OemCustomize.c of all boards using stoneyridge must be available at romstage. BUG=b:74236170 TEST=Build grunt and kahlee, actual test will be performed at a later patch. Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25528 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10mb/google/poppy/atlas: Fix SPD index in commentJonathan Neuschäfer
Fixes: ba49c09b2f ("mb/google/poppy: Add variant for Atlas") Change-Id: I9c5c10abf8129ff61b97312a70ed4749606a3090 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25556 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-10cpu/amd/microcode/microcode.c: Remove unneeded whitespaceElyes HAOUAS
Change-Id: Ib6f73dc0b0d11f6b66b7dbdd33cd6785359191ab Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-10mb/google/poppy: Disable rear camera for all vayne skuAmanda Huang
Since there are two cameras on Nami and only one camera on Vayne. We need to disable rear camera on all Vayne sku. BUG=b:75073617 BRANCH=master TEST=Verify if only front camera shown on Vayne Change-Id: I6e7c1e8791462f00ad8336372954ee0a9465d9b8 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-10cpu/intel/sandybridge: Put stage cache into TSEGArthur Heymans
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. The code is mostly copied from src/cpu/intel/haswell. TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used. Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09cpu/x86/mtrr: Use single code path with/without holesNico Huber
Now that calc_var_mtrrs_with_hole() always chooses the optimal allocation, there is no need for calc_var_mtrrs_without_hole() any more. Drop it and all the logic to decide which one to call. Tests performed compared to "upstream" (before "cpu/x86/mtrr: Optimize hole carving strategy") on a Lenovo/X200s with 48MiB GFX stolen memory. 2GiB total RAM: 3 MTRRs saved MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007ac00000 size 0x7ab40000 type 6 0x000000007ac00000 - 0x00000000d0000000 size 0x55400000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 upstream: MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/8 > 6. MTRR: default type WB/UC MTRR counts: 4/7. MTRR: WB selected as default type. MTRR: 0 base 0x000000007ac00000 mask 0x0000000fffc00000 type 0 MTRR: 1 base 0x000000007b000000 mask 0x0000000fff000000 type 0 MTRR: 2 base 0x000000007c000000 mask 0x0000000ffc000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0 patched: MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x000000007ac00000 mask 0x0000000fffc00000 type 0 MTRR: 2 base 0x000000007b000000 mask 0x0000000fff000000 type 0 MTRR: 3 base 0x000000007c000000 mask 0x0000000ffc000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 4GiB total RAM: no MTRRs saved but slightly more accurate alignment MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007cc00000 size 0x7cb40000 type 6 0x000000007cc00000 - 0x00000000d0000000 size 0x53400000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000017c000000 size 0x7c000000 type 6 upstream: MTRR: default type WB/UC MTRR counts: 7/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 2 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 3 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000000f00000000 type 6 patched: MTRR: default type WB/UC MTRR counts: 7/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 MTRR: 1 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 2 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 3 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 4 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000000f80000000 type 6 8GiB total RAM: possible savings but WB still beats UC MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000007cc00000 size 0x7cb40000 type 6 0x000000007cc00000 - 0x00000000d0000000 size 0x53400000 type 0 0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 0x0000000100000000 - 0x000000027c000000 size 0x17c000000 type 6 upstream: MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/11 > 6. MTRR: default type WB/UC MTRR counts: 4/10. MTRR: WB selected as default type. MTRR: 0 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 1 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0 patched: MTRR: Removing WRCOMB type. WB/UC MTRR counts: 7/7 > 6. MTRR: default type WB/UC MTRR counts: 4/6. MTRR: WB selected as default type. MTRR: 0 base 0x000000007cc00000 mask 0x0000000fffc00000 type 0 MTRR: 1 base 0x000000007d000000 mask 0x0000000fff000000 type 0 MTRR: 2 base 0x000000007e000000 mask 0x0000000ffe000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000000f80000000 type 0 Change-Id: Iedf7dfad61d6baac91973062e2688ad866f05afd Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09cpu/x86/mtrr: Optimize hole carving strategyNico Huber
For WB ranges with unaligned end, we try to align the range up and carve a hole out of it which might reduce MTRR usage. Instead of trying an arbitrary alignment, we try all and choose an optimal one. Also, restructure the cases when we try to find a hole. Which leads us to the following three: 1. WB range is last in address space: Aligning up, up to the next power of 2, may gain us something. 2. The next range is of type UC: We may align up, up to the _end_ of the next range. If there is a gap between the current and the next range, it would have been covered by the default type UC anyway. 3. The next range is not of type UC: We may align up, up to the _base_ of the next range. This is the end of the gap, if there is one. Change-Id: Iefb064ce8c4f293490a19dd46054b966c63bde44 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09mb/google/octopus: Enable EC wakeShaunak Saha
This patch sets the wake for EC to proper gpios. BUG=77605178 TEST=Test that lidopen wakes up the system from S3. Change-Id: Icbf30007403191005396027e74b9b6fb7319e006 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25539 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09soc/intel/apollolake: Fix GPIO group to GPE mapping for GLKHannah Williams
BUG=b:77605178 TEST=Tested EC wake sources Change-Id: Id879b3e91d4c0794662cf3d8204bd077117db23c Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-04-09soc/intel/apollolake: enable MONITOR/MWAIT for GLKCole Nelson
MONITOR/MWAIT had an irremediable hardware bug for Apollolake. This has been fixed for GLK. Therefore, make MONITOR/MWAIT based C-states the default for GLK and disable IO-Redirection based C-states used for Apollolake. Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state residencies with and without load. Tested for S0ix entry and exit using: "echo freeze > /sys/power/state" and "suspend_stress_test -c 500". BUG=b:77639897 Change-Id: If648c25a9b26c04b278dce4af241d439790288ca Signed-off-by: Cole Nelson <colex.nelson@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/19718 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09soc/intel/common: Add funtion to modify PAT & NXE bitNaresh G Solanki
Add function to modify NXE bit & PAT. BUG=None BRANCH=None TEST=Make sure build for Glkrvp is successful. Change-Id: I265d6d5ca538496934a375eb8d99d52879522051 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25480 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09mb/google/octopus/variants/baseboard: Add DPTF parametersSumeet Pawnikar
This patch adds the DPTF parameters for Octopus baseboard. These parameters are copied from reef/coral as initial reference values. BUG=None BRANCH=None TEST=Build coreboot for Octopus board. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Change-Id: I069bae8c9ef43ebd1ee20945ef34a7f51991f621 Reviewed-on: https://review.coreboot.org/25339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09ACPI S3: Drop too early resume backupKyösti Mälkki
No longer needed as low memory backup is implemented as part of the ramstage loader, when the actual requirement of the ramstage to load is known. Change-Id: I5f5ad94bae2afef915927b9737c79431b6f75f22 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15477 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09intel/nehalem post-car: Use postcar_frame for MTRR setupKyösti Mälkki
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-09lib/lzmadecode: Add block around `UpdateBit1()`Paul Menzel
Fix the error below. ``` src/lib/lzmadecode.c: In function 'LzmaDecode': src/lib/lzmadecode.c:77:2: error: macro expands to multiple statements \ [-Werror=multistatement-macros] Range -= bound; \ ^~~~~ src/lib/lzmadecode.c:300:7: note: in expansion of macro 'UpdateBit1' UpdateBit1(prob); ^~~~~~~~~~ src/lib/lzmadecode.c:299:8: note: some parts of macro expansion are not \ guarded by this 'else' clause } else ^~~~ cc1: all warnings being treated as errors ``` The macro is defined as below. #define UpdateBit1(p) \ Range -= bound; \ Code -= bound; \ *(p) -= (*(p)) >> kNumMoveBits Found-by: gcc-8 (Debian 8-20180402-1) 8.0.1 20180402 (experimental) [trunk revision 259004] Fixes: 35af5c47 (src/lib: Fix spacing) Change-Id: Ife0688541e23c05e26e429a6d8caee7e2d425b1b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/25549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-04-09amd/stoneyridge: Add GNB IOAPIC initMarc Jones
Use standard coreboot function to set virtual wire mode on the GNB IOAPIC. BUG=b:74104946 TEST=Check GNB IOAPIC debug output on serial. Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-04-09device/dram/ddr2.c: Add methods to compute to identify dramArthur Heymans
DDR2 DIMMs are uniquely defined by SPD byte 64 till 72 and 93 till 98. Compute a crc16 over that data to provide a solid way to check DIMM identify. Reuse the crc16 function from ddr3.c to do this. Change-Id: I3c0c42786197f9b4eb3e42261c10ff5e4266120f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-09ioapic: extend definition name to avoid collisionMarc Jones
Change EN/DISABLED to INT_EN/DISABLED to avoid collision with other EN/DISABLE definition. Change-Id: I85b1c544d0f31340a09e18f4b36c1942ea0fa6ef Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25540 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09soc/intel/{apl,glk}: Move flush_l1d_to_l2 function to common locationNaresh G Solanki
Move flush_l1d_l2 function to common location within the SoC. BUG=None: BRANCH=None TEST= Build for glkrvp. Change-Id: I4aaaaccc4f343bc4926111258a33e09e79c76141 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09vboot: Add support for reading GBB flagsFurquan Shaikh
This change adds basic support for reading flags from GBB header located in "GBB" section on SPI flash. Change-Id: I35ecb5ba964511379baa4e9f458ba2e8c6b74b4e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-09console: Expose vsnprintfDavid Hendricks
It's a standard function. Change-Id: I039cce2dfc4e168804eb7d12b76a29af712ac7a1 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06mb/lenovo/w520: Add ThinkPad W520 supportNico Rikken
Tested and working: * 4 RAM-slots * Speakers * PCIe Wifi * Camera * Fan * Touchpad, trackpoint and keyboard * Ethernet * Keyboard ACPI events * USB 3.0 * SD-card reader * Native graphics (LCD panel) * Harddisk in Ultrabay * SeaBIOS payloads ** Debian Live ** Debian testing 4.14.0-3-amd64 * GRUB ** Debian Live ** Debian testing 4.14.0-3-amd64 Not working: * Displayport and VGA output (requires VGA option ROM and ACPI switch call) Not tested: * Intel VGA option ROM * ACPI events related to ultrabay * Smart card reader * Docking station Change-Id: I1deb0436a807950c605dcd590deedcb3169bf8c5 Signed-off-by: Nico Rikken <nico@nicorikken.eu> Reviewed-on: https://review.coreboot.org/23564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-06mainboard: Add ASUS Maximus IV GENE-ZTristan Corrick
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.3 with kernel 4.9. This code is based on the output of autoport. Working: - S3 suspend/resume - USB - Gigabit Ethernet - integrated graphics - PCIe - SATA - eSATA - PS/2 port (only a mouse has been tested) - hardware monitor - onboard audio - front panel audio - native raminit (2 x 4GB + 2 x 8GB, DDR3-1333) - native graphics init with libgfxinit - EHCI debug. The debug port is the port closest to the HDMI port. - flashrom, using the internal programmer. Tested with coreboot, untested with the vendor firmware. - NVRAM settings. Only `gfx_uma_size` and `debug_level` have been tested with values different from the default. Untested: - VGA BIOS for graphics init - PCIe graphics - S/PDIF audio Not working: - "clear CMOS" button The CPUTIN sensor on the Super I/O is not connected. The PECI agent is likely connected instead to give CPU temperature readings. However, there does not appear to be enough information in the publicly available datasheets to fully set up the PECI agent. As a result, there is currently no accurate, automatic fan control via the Super I/O. Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/24971 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06fsp/fsp2_0/coffeelake: Add Coffeelake FSP UPD HeadersNg Kin Wai
Header files based on FSP 7.0.25.34 BUG=none BRANCH=none TEST=built coreboot without build error. Change-Id: Id92d99915bda89dd475f393a48adee60bbaee80f Signed-off-by: Ng Kin Wai <kin.wai.ng@intel.com> Reviewed-on: https://review.coreboot.org/25335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-04-06mb/intel/glkrvp: Unselect Chrome EC specific config when using Intel ECNaresh G Solanki
When building with Intel EC selected, unselect Chrome EC specific options i.e., LID switch to prevent build error. BUG=None BRANCH=None TEST=Build with Intel EC selected, Build should be successful. Change-Id: I39d6d65bbfd08d684af43972b89ca78fcbd58567 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/25479 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06fsp_broadwell_de: Provide valid address and size for DCACHE rangeWerner Zeh
On Broadwell-DE the FSP sets up DCACHE in the early call. The address does not match the default FSP 1.0 address defined in src/drivers/intel/fsp1_0/Kconfig which leads to errors when this range is used in pre-ramstage stages. This patch provides the matching DCACHE_RAM_BASE value among with a suitable DCACHE_RAM_SIZE for the FSP based Broadwell-DE implementation. The include order of Kconfig files makes sure that the Kconfig file in the soc directory is sourced first and the defined values will override the ones in src/drivers/intel/fsp1_0/Kconfig. Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/25535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-06fsp_broadwell_de: Provide valid ACPI path names for domain and LPCWerner Zeh
Provide ACPI path names for PCI domain and LPC device so that generated ACPI tables have valid device paths. Change-Id: I5a97e45ef50ec5ee9d64c5d2834968a02455cf72 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/25534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06mb/google/octopus: Edge trigger cr50 interruptJustin TerAvest
Interrupts from cr50 are edge-triggered, not level-triggered. This change updates the GPIO configuration accordingly. BUG=b:75306520 BRANCH=None TEST=None Change-Id: I0c5fb4495b404412a78965c2de7f00248d0c684b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25538 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06sb/intel/common/firmware: Allow CONFIG_USE_ME_CLEANER on Kaby LakeNicola Corna
Some users have reported a successful boot with me_cleaner on Kaby Lake with OEM firmware: https://github.com/corna/me_cleaner/issues/3 It should work as well on coreboot. Change-Id: Ifc47f19deee5c39ca27b427c9406da7f6e3e9f15 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25507 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06mb/google/octopus/variants/baseboard: Enable DPTF supportSumeet Pawnikar
This patch enables DPTF support for Octopus baseboard. BUG=None BRANCH=None TEST=None Change-Id: I88a94c73ef0c9da708c0440f7edadd85488edfdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-06soc/cavium: import raw BDK sourcesDavid Hendricks
This imports common BDK sources that will be used in subsequent patches. The BDK is licensed under BSD and will be reduced in size and optimized to compile under coreboot. Change-Id: Icb32ee670d9fa9e5c10f9abb298cebf616fa67ad Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/25524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-04-06drivers/intel/gma: Depend less on default fb valuesNico Huber
Instead of hard-coding a lot of default values of the framebuffer config, we use the values provided by Display_Probing.Scan_Ports() and only overwrite what is necessary. This way we are more independent from changes inside libgfxinit. Change-Id: I121bbd926532c27321446282aa334cc45cdbeef1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-06drivers/intel/gma: Amend stride calculation of linear fbNico Huber
Aligning the stride up to a multiple of 64 pixels was flawed: We want to actually align up to one cacheline (64 bytes) as that's the mini- mum what the hardware supports. Change-Id: I3f824ffd7d12835935e4e4bde29fe82dc3e16f9d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/25451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-06amd/common/block/pi: Make agesa_heap_base() staticMarshall Dawson
Convert agesa_heap_base() to static since it's unused outside of heapmanager.c. Change-Id: I3ee162985ca1ea36461ea413416d98451a700f8c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-04-06vc/amd/stoneyridge: Add definition for AGESA heap rebaseMarshall Dawson
AgesaHeapRebase is an optional callout that allows AGESA to use a coreboot-managed heap base address. Its internal default location is determined by AMD_HEAP_START_ADDRESS which is defined as 4 MB. Add a #define that AGESA may use once the feature is available. BUG=b:74518368 Change-Id: Id23455779b1c8c4931ad1a3122587e09ad237ecc Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-04-06amd/stoneyridge: Use defined value for SPI flash MTRRMarshall Dawson
Replace an absolute value with a #define value in bootblock. This is in preparation for using an additional MTRR in a subsequent patch. Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-04-06purism/librem_skl: Add AC/DC LoadLine to VR ConfigYouness Alaoui
The FSP 2.0 needs to set the ac_loadline and dc_loadline for each VR config. Without it, the Loadline is considered to be 0 mOhm and this causes CPU temp to jump all over the place whenever the CPU is used. This is necessary since there are no VR_CONFIG icc mappings for Skylake SKUs, only KabyLake. These values were copied from the Google Poppy devicetree. Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06purism/librem_skl: Set TCC Activation at 95CYouness Alaoui
Set the Thermal Control Circuit (TCC) activaction value to 95C even though FSP integration guide says to set it to 100C for SKL-U (offset at 0), because when the TCC activates at 100C, the CPU will have already shut itself down from overheating protection. This was tested on Purism Librem 13 v2. A bisect showed that the immediate shutdowns happened after commit [1] was merged which led to this solution. [1] ec5a947b (soc/intel/skylake: make tcc_offset take effect) Change-Id: Idfc001c8e46ed3b07b24150c961c4b9bc9b71a62 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06purism/librem_skl: Enable VMX and Intel SpeedStep in devicetreeYouness Alaoui
Although VmxEnable is currently ignored by FSP, a forthcoming patch explicitly enables it in coreboot, so set it in anticipation of that. Enable Intel SpeedStep to ensure the ACPI tables are generated for the C-states/P-states which are required for the xen-acpi-processor module to be loaded. Without it, the Qubes 4.0-rc4 installer will complain at boot about modules that could not be loaded. Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06purism/librem_skl: Enable TPM supportYouness Alaoui
Change the GPIO to match the TPM-enabled motherboards, and add TPM support in devicetree and enable the config. After changing the GPIO table, the librem 13v2 and librem 15v3 now have the same GPIOs, so use a single gpio.h file instead of one file per variant. Change-Id: I425654c1c972118aa81c27961246238c2eef782d Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/23683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-05soc/intel/cannonlake: Add VT-d and VMX programmingLijian Zhao
Add FSP option to enable/disable VT-d (Intel Virtualization Technology for Directed I/O) and VMX (Virtual Machine Extensions), VMX will be disabled once VT-d got disabled. Bug=b:73655383 TEST=Build and flash image on meowth board with debug build FSP, in serial log search for "VMXEnable" and "VtdDiable". Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-05intel/fsp: Update cannonlake fsp headerLijian Zhao
Fsp revison 7.x.2A.20 also updated MemInfoHob.h to fix SMBIOS Type 17 Offset 15h Speed report incorrectly issue. BUG=None TEST=Boot up with meowth platform and run dmidecode to see two dimm entries under Type 17. Change-Id: Ie1c4df162e75535ad458709452a76de01e31907e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25378 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05soc/intel/cannonlake: Clear EMMC timeout when boot source is not EMMCBora Guvendik
Clear EMMC timeout register to avoid EMMC issue according to cannonlake bios writer guide. _PS0 is not called by kernel when boot source is not EMMC but kernel still initializes emmc. Add _INI to EMMC,SD asl code to cover cases that the system doesn't boot from EMMC. BUG=b:76202699 TEST=Install OS into EMMC Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/25290 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05sb/intel/bd82x6x: Let mainboard override SPI opmenuNico Huber
For some SPI chips (e.g. those with AAI writes), the default OPMENU definitions don't work well. Thus, provide an option to override the defaults in the devicetree. Writing the OPMENU now happens in ramstage instead of the SMM finalize handler. If you let coreboot call the finalize handler, nothing should change. If you call the handler from your payload, OTOH, the OPMENU might have been changed in between, so be careful what you lock. Change-Id: I9ceaf5b2d11365e21a2bebc9c5def1fcf0be8aad Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-04-05mb/google/poppy/variants/nami: Add SPD file for Vaynechriszhou
Add SPD file for sdp hynix_dimm_H5AN8G6NAFR-UHC (ram id: 6). BUG=b:77290144 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace Signed-off-by: chriszhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2018-04-05mb/amd/gardenia/gpio.c: Convert GPIO to new formatRichard Spiegel
New macros were developed that replace previous way of defining GPIO, with pin and intention very clear while keeping the table mostly identical to previous method (there's no pull up or pull down when a GPIO is set as an output). Change current gardenia table to use the new macros. BUG=b:72875858 TEST=Build Gardenia. Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-05soc/qualcomm/sdm845: Add MMU supportT Michael Turney
Initialize 1st 4GB as Device Memory, except: * 1st page: NULL address * System_IMEM: Cached SRAM * Boot_IMEM: Cached SRAM TEST=build Change-Id: Ic6cf022b08bb2568fdf956cea8bad46da89236c5 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25201 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05soc/qualcomm/sdm845: remove hole in memlayout.ldT Michael Turney
Removed 33KB hole in SSRAM TEST=build & run Change-Id: I6851860f878d9a0688975fa855980870d657ee1a Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25391 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05soc/intel/skylake: Generate ACPI DMAR tableNico Huber
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 16:12:14 +0000