coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-11-07	mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers	V Sowmya
2020-11-07	mb/intel/adlrvp: Configure the HPD GPIO's	V Sowmya
2020-11-07	vc/intel/FSP2_0/CPX-SP: update to ww45 release and add watermark option	Jonathan Zhang
2020-11-06	sc7180: Correct mmu configuration for AOP SRAM regions	T Michael Turney
2020-11-06	soc/amd/picasso: add Raven1 GPU PCI ID	Felix Held
2020-11-06	soc/amd/picasso/cpu: add Raven1 CPUID to CPU table	Felix Held
2020-11-06	zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board	Lucas Chen
2020-11-06	mb/purism/librem_mini: Set unused GPIO pads to PAD_NC	Matt DeVillier
2020-11-06	soc/amd/picasso: Set vboot hashing block size to 36k	Martin Roth
2020-11-06	soc/amd/picasso: Up stack size to 40k for vboot hash buffer	Martin Roth
2020-11-06	mb/google/volteer/var/elemi: Update gpio and devicetree	Wisley Chen
2020-11-06	mb/google/variant/elemi: config CSE LITE	Wisley Chen
2020-11-06	mb/google/variant/elemi: Select USE_CAR_NEM_ENHANCED_V2 for elemi	Wisley Chen
2020-11-06	security/vboot: Add Kconfig symbol to set hashing block size	Martin Roth
2020-11-06	soc/intel/xeon_sp/skx: Fix MADT CPU indexes	Marc Jones
2020-11-06	soc/intel/xeon_sp: Move CPU helper functions	Marc Jones
2020-11-06	soc/intel/xeon_sp/cpx: Reorder cpu.c .h includes	Marc Jones
2020-11-06	amdfwtool: Use shell command to get depend file list	Zheng Bao
2020-11-06	soc/amd/picasso: Update coreboot UPD variable names to include units	Zheng Bao
2020-11-06	mb/google/octopus/variants/garg: Add new LTE SKU	Kevin Chiu
2020-11-05	soc/intel/tigerlake: Disable C1 C-state Demotion	Ravi Sarawadi
2020-11-05	soc/amd/picasso: move MAX_CPUS setting from mainboard to SoC Kconfig	Felix Held
2020-11-05	ec/google/chromeec: Remove the check for Internal TypeC MUX	Karthikeyan Ramasubramanian
2020-11-05	mb/msi/ms7707/Kconfig: Drop invalid defaults	Angel Pons
2020-11-05	mb/purism/librem_mini: Drop DW0/DW1 from GPIO config comments	Matt DeVillier
2020-11-05	mb/intel/adlrvp: Add support for DDR5 memory	Subrata Banik
2020-11-05	soc/intel/xeon_sp: Use common cpu/intel romstage entry	Arthur Heymans
2020-11-04	haswell: Add Intel TXT support in romstage	Angel Pons
2020-11-04	mb/purism/librem_cnl: Set SaGv to FixedHigh	Angel Pons
2020-11-04	sec/intel/txt: Add support for running SCLEAN in romstage	Angel Pons
2020-11-04	sb/intel/lynxpoint/acpi/gpio.asl: Simplify constants	Angel Pons
2020-11-04	sb/intel/lynxpoint: Align LP GPIO ACPI with Broadwell	Angel Pons
2020-11-04	sb/intel/lynxpoint/acpi: Put together LP GPIO code	Angel Pons
2020-11-04	soc/intel/broadwell: Merge `device_nvs.asl` into `globalnvs.asl`	Angel Pons
2020-11-04	soc/intel/broadwell: Include EC and IRQ links ACPI early	Angel Pons
2020-11-04	sb/intel/*/acpi/lpc.asl: Drop unnecessary RCBA offset	Angel Pons
2020-11-04	sb/intel/lynxpoint: Expose full LPC device ID in ACPI	Angel Pons
2020-11-04	soc/intel/broadwell/pch: Use common PCIe ACPI code	Angel Pons
2020-11-04	soc/intel/broadwell/pch/acpi: Add PCIe register offsets	Angel Pons
2020-11-04	soc/intel/broadwell/gma.c: Align struct with Haswell	Angel Pons
2020-11-04	sb/intel/common/acpi/pcie.asl: Generalise file comment	Angel Pons
2020-11-04	sb/intel/common/acpi/irqlinks.asl: Clean up cosmetics	Angel Pons
2020-11-04	soc/intel/broadwell: Use common irqlinks.asl	Angel Pons
2020-11-04	soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs	Angel Pons
2020-11-04	soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint	Angel Pons
2020-11-04	nb/intel/haswell: Place CTDP ASL code in a separate scope	Angel Pons
2020-11-04	nb/intel/haswell/acpi: Align with Broadwell	Angel Pons
2020-11-04	mb/purism/librem_mini: Drop community comments in GPIO config	Matt DeVillier
2020-11-04	mb/purism/librem_mini: Update GPIO config	Matt DeVillier
2020-11-04	mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPs	Matt DeVillier