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2012-12-05Conditionally include mc146818rtc in console.cDavid Hendricks
get_option() is used to get a config option (debug loglevel) from CMOS. However, not all machines have CMOS, so define a dummy inline function that will return an error code so the caller (console_init()) will use the default loglevel. Change-Id: I6adf371d79164178f40a83f7608289a6a7673357 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1962 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-01Drop TINY_BOOTBLOCKKyösti Mälkki
Change-Id: I38ea2ed2be4d9240ec8cb6d5dc5b3cc578cdaefb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-01Add include files for samsung s5p-commonRonald G. Minnich
These are from u-boot but have been cleaned up somewhat to remove references to linux include files. Change-Id: I5fe3954a11d8c4aa792620ef5e1a5ee8932b8578 Signed-off-by: Hung-Ti Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1930 Tested-by: build bot (Jenkins)
2012-11-30Rename devices -> deviceStefan Reinauer
to match src/include/device Change-Id: I5d0e5b4361c34881a3b81347aac48738cb5b9af0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1960 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30Drop boot directoryStefan Reinauer
It only has two files, move them to src/lib Change-Id: I17943db4c455aa3a934db1cf56e56e89c009679f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1959 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-30src/lib/Makefile.inc: Add license headerStefan Reinauer
Change-Id: If8bce4ebde9101ac9087fcbd43adc0e08c26352d Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/1957 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30Make set_boot_successful depend on PC80_SYSTEMStefan Reinauer
Set_boot_successful depends on CMOS parts that non-PC80 platforms do not have. For now, make the current path depend on CONFIG_PC80_SYSTEM, and make the alternative empty. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I68cf63367c8054d09a7a22303e7c04fb35ad0153 Reviewed-on: http://review.coreboot.org/1954 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30Only compile PC80 drivers when CONFIG_PC80_SYSTEM is setStefan Reinauer
Change-Id: Iac2f3ebf68c9c1df296fc81d10ee97053a9d5469 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1956 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30build system: Treat cmos.default as text filePatrick Georgi
It's a more easily maintainable format than a 128 byte binary blob Change-Id: Ic9b9f53cd025b5f89a21971930fabf6592f95d67 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1867 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30Supermicro h8scm: add agesa version of supermicroSiyuan Wang
Supermicro h8scm has a C32 CPU socket, the details of this board is: http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm We are planning to replace legacy C32 code with agesa and the h8scm_fam10 do not support family 15 CPU, so we update this mainboard with this patch. This code supports memory at 800M Hz of f10 CPU, bu f15 CPU does not has this limitation. If you want to change the frequency of memory, please edit the macros "BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT" and "BLDCFG_MEMORY_CLOCK_SELECT" in src/mainboard/supermicro/h8scm/buildOpts.c Change-Id: I9ca9e70d7f3e82c07e7d36695bf31008db152afb Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/1510 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30AMD SB800: Interrupt routine for PCI slots on PersimmonZheng Bao
Set the correct device number in the pcie interrupt routine in ACPI asl. The device number is decided by which address pin is connected to IDSEL. Table 3-1: IDSEL Generation Primary Address AD[15::11] Secondary Address AD[31::16] 0 0000 0000 0000 0000 0001 0 0001 0000 0000 0000 0010 0 0010 0000 0000 0000 0100 0 0011 0000 0000 0000 1000 0 0100 0000 0000 0001 0000 0 0101 0000 0000 0010 0000 0 0110 0000 0000 0100 0000 0 0111 0000 0000 1000 0000 0 1000 0000 0001 0000 0000 0 1001 0000 0010 0000 0000 0 1010 0000 0100 0000 0000 0 1011 0000 1000 0000 0000 0 1100 0001 0000 0000 0000 0 1101 0010 0000 0000 0000 0 1110 0100 0000 0000 0000 0 1111 1000 0000 0000 0000 1 xxxx 0000 0000 0000 0000 On persimmon, PCI slot 0's IDSEL is connected to AD19, so the device number is 3. Slot 1's IDSEL is connected to AD20, so the device number is 4. Change-Id: Ic0fb7ac1c87ec306bf314e4d2b8c2bdc9031081b Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30Persimmon: Disable the unused PCI clocksDave Frodin
Change-Id: I4b735fe4e6441f99236e43b34695fdac95b8888a Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1875 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30AMD S3: Leverage the public SPI routineZheng Bao
Remove the old, unflexible code for storing S3 data in SPI flash. Refer to flashrom. Tested on Parmer. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-30Create a a new configuration variable for PCIRonald G. Minnich
Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1947 Tested-by: build bot (Jenkins)
2012-11-30Add mainboard hook to bootblockKyösti Mälkki
Change allows to override default bootblock_mainboard_init() with mainboard-specific code. If the default bootblock_mainboard_init() handler is replaced, with one from file BOOTBLOCK_MAINBOARD_INIT, one needs to take care the replacement calls all the necessary bootblock_x_init() functions. Change-Id: Ie8c667cdba7cafe9ed2d4b19ab2bd21d941ad4ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1845 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-30Refactor bootblock initialisationKyösti Mälkki
Makes it a bit easier to implement mainboard-specific behaviour while executing the bootblock. Change-Id: I04e87f89efb4fad1c0e20b62ea6a50329a286205 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-30Add multi-architecture support to cbfstoolDavid Hendricks
This is an initial re-factoring of CBFS code to enable multiple architectures. To achieve a clean solution, an additional field describing the architecture has to be added to the master header. Hence we also increase the version number in the master header. Change-Id: Icda681673221f8c27efbc46f16c2c5682b16a265 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1944 Tested-by: build bot (Jenkins)
2012-11-30Lumpy: Need byteorder.h in romstageStefan Reinauer
Not sure why this never triggered an error before. Change-Id: I85d8b3b862492df04163a5f751c7ea4288406860 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1946 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-11-30Make libgcc wrappers arch-specific, add ARMv7David Hendricks
Change-Id: Ia0bbd3bec6588219ce24951c0bcebefc6b6ec80e Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1940 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-30Add dummy Kconfig options for armv7David Hendricks
This adds a dummy config for ARMV7 for developing various follow-up patches which rely on ARCH_ARMV7. Change-Id: Id913054d916f41607d10ebc02aaf74082e14b554 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1939 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2012-11-29Add the maxim MAX77686 power controller.Ronald G. Minnich
Create a new directory in drivers for power controllers. Add the MAXIM MAX77686 power control support. Accessing this controller requires I2C support. Note that this will not build until the I2C usage is changed for coreboot. I'm putting it in mainly because we need it soon and I want to see if the new directory is acceptable. Change-Id: I6c2a6d2165f33b41d2c8e4813222b21d2385e879 Signed-off-by: David Hendricks <dhendrix@chromium.org> SIgned-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1938 Tested-by: build bot (Jenkins)
2012-11-29Drop empty mainboard.cKyösti Mälkki
Change-Id: Idcf9349d96297b8cb0ea1e68769e02659ac16ab8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1933 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29Drop empty mainboard_opsKyösti Mälkki
Change-Id: I24866142eebcb8fdbc7e21f5b2f364a8d1b264b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1932 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29Make mainboard_ops and mainboard.c file optionalKyösti Mälkki
This provides weak empty declaration for mainboard_ops. The struct chip_operations is not defined for __PRE_RAM__ so the declaration is also moved upwards in the output. Change-Id: I101f0b8b9f0a55fb51a7c6475d53cc588c84026d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1931 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29pirq_route_irqs is privatePatrick Georgi
Change-Id: I120913dac3150a72c2e66c74872ee00074ee0267 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1936 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-29Minor changes to .h files for samsung ARM partRonald G. Minnich
With these changes we have a mostly compiling target. I'm still removing and pruning .h files, but hopefully later today I'll do the last few .h commits and move on to .c Change-Id: Ia82d787496184e028f37d7b67336d61fda75aa94 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1937 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-28Remove assembly coded log2 functionRonald G. Minnich
As we move to supporting other systems we need to get rid of assembly where we can. The log2 function in src/lib is identical to the assembly one (tested for all 32-bit signed integers :-) and takes about 10 ns to run as opposed to 5ns for the non-portable assembly version. While speed is good, I think we can spare the 15 ns or so we add to boot time by using the C version only. Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1928 Tested-by: build bot (Jenkins)
2012-11-28add .h files for common exynos 5Ronald G. Minnich
Change-Id: I48497adc29a1b8ca11d1e0a5d879cab5b6b55dcd Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1926 Tested-by: build bot (Jenkins)
2012-11-28Add .h files for samsung exynos 5250Ronald G. Minnich
Per a conversation with Stefan, these chip-dependent files are moved to the src tree, in the manner of other chips (north and southbridge). Change-Id: I12645ba05eb241eda200ed06cb633541a6a98119 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Reviewed-on: http://review.coreboot.org/1925 Tested-by: build bot (Jenkins)
2012-11-28amdk8/amdfam10: Use CAR_GLOBAL for sysinfoPatrick Georgi
This gets rid of the somewhat unstructured placement of AMD's sysinfo structure in CAR. We used to carve out some CAR space using a Kconfig variable, and then put sysinfo there manually (by "virtue" of pointer magic). Now it's a variable with the CAR_GLOBAL qualifier, and build system magic. For this, the following steps were done (but must happen together since the intermediates won't build): - Add new CAR_GLOBAL sysinfo_car - point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR - remove DCACHE_RAM_GLOBAL_VAR_SIZE - from CAR setup (no need to reserve the space) - commented out code (that was commented out for years) - only copy sizeof(sysinfo) into RAM after ram init, where before it copied the whole GLOBAL_VAR area. - from Kconfig Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1887 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Drop driver-y from GM45/ICH9/RK9Stefan Reinauer
This broke because those components were not yet committed when the patch to drop the driver class was made. Change-Id: I29948223503a6c4b196eafa169c064cd26da1be1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27Remove AMD special case for LAPIC based udelay()Patrick Georgi
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27Fix technexion tim5690 board VGA handlerStefan Reinauer
When dropping ramstage.a, unused functions with unresolved symbols are not silently dropped anymore. This makes the tim5690 compilation fail. This fix makes sure we don't compile in the int15 handler code when we don't set CONFIG_VGA_ROM_RUN Change-Id: If6872c983d9fd811eb33259421f94b551f3b9b34 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1929 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-27Enable the FCH GPP port prior to device enumerationDave Frodin
Change-Id: Ib4401897570f9e4d31c18d05144b5deb6f4523bc Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1873 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-27Drop duplicate files that prevent building without ramstage.aStefan Reinauer
When dropping ramstage.a duplicate symbols in ramstage will start breaking the build. Hence drop all the duplicate functions implemented by mainboards that have those functions in generic or component code already. Change-Id: I5cf8245c67b6f0f348388db54256d28f47017a61 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1865 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2012-11-27build system: Eliminate special case for c_startPatrick Georgi
c_start.o has a special case in the build system, which we can eliminate, somewhat simplifying the build. To ensure that the entry point is at the beginning, introduce a new section .textfirst that is placed appropriately. In principle the ENTRY() definition in the linker script should be enough, but better be safe. Change-Id: I9737f7f5731e12ceb2119eb432b0e09832bc53fa Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1909 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27Get rid of drivers classPatrick Georgi
The use of ramstage.a required the build system to handle some object files in a special way, which were put in the drivers class. These object files didn't provide any symbols that were used directly (but only via linker magic), and so the linker never considered them for inclusion. With ramstage.a gone, we can drop this special class, too. Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27Drop ramstage.aPatrick Georgi
ramstage.a has two issues: 1. duplicate source filenames don't survive the ar(1) treatment properly (so files aren't considered) 2. ld doesn't resolve symbols if it isn't forced to, in particular no overrides of weak symbols Downside: The resulting binaries get slightly larger. Link time optimizations should fix that, as would tighter rules in the build system (to not compile unused code in the first place). Change-Id: Iaae771ec8f92b42069237acd3b79c14e5bf9c03d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1566 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27Provide weak empty declarations of all chip_ops used on a boardPatrick Georgi
sconfig creates empty defaults for all chip_ops, which can be overridden by drivers simply by providing a concrete implementation. Change-Id: Ib37515f0b0747bdbf4da780d28690a1e719944b2 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/1567 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27roda/rk886ex: Correct COMB irq reading / reduce warningsNico Huber
The calculation of COMB's irq reading was wrong by the 4-bit shift. Also, the asl compiler warned about the splitting in lo/hi bytes which seems unnecessary. Change-Id: Ia5101d5a19f68c2da827d7e37a18922f959604c7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1923 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27roda/rk9: Fix for VGABIOS changesPatrick Georgi
Forgot to update the rk9 for the unified VGABIOS handling. This applies to rk9 what is done for other boards in commits 3c84261e84318708c9c16ee5df5c2549c609dd0a d5d340695b84ef6351818236dc514cd9734e87b1 Change-Id: I892b7d81927e277778c1c5251d27416fa79c9868 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1924 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)Zheng Bao
For SST chips, the Write-Status-Register instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction, instead of Write-Enable. Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1919 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27roda/rk9: New mainboardPatrick Georgi
Roda RK9 is a notebook based on the GM45/ICH9 platform using DDR3 memory. http://roda-computer.com/products/notebooks/rk9/ Tested with various Linux versions, known to work: - 2x4GB RAM - IGD - HD Audio - UHCI, EHCI - AHCI - NIC - PCI - PS/2 keyboard - serial console - ACPI lid switch - ACPI battery/AC events - power off, reboot Change-Id: I7299dccbff2eea3544363fdd4f49f05aa3dae7bc Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1691 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27intel/i82801ix: new southbridge, ICH9Patrick Georgi
Add support for ICH9 southbridge Change-Id: I70612431101bf48d9dcc96ee1b37d257c9ad2ee2 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1690 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27intel/gm45: new northbridgePatrick Georgi
The code supports DDR3 boards only. RAM init for DDR2 is sufficiently different that it requires separate code, and we have no boards to test that. Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27Add initialization hook for chipsNico Huber
Add an init() function to the chip_operations which will be called before bus enumeration. This allows to disable unused devices before they get enumerated. Change-Id: I63dd9cbfc7b5995ccafb7bf7a81dc71fc67906a0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1623 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27Conditionally #include mc1468181rtc if CMOS_POST is enabledDavid Hendricks
This will omit the mc1468181rtc header if it is not needed. Currently it contains a lot of inlined functions which depend on architecture- specific IO. Change-Id: I4ef1bc1362c159e0c780c3eade01af04f029f949 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1916 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2012-11-27Make POST codes written to IO port optionalDavid Hendricks
This adds more configurability to POST codes. The current assumption is that POST codes should be written to an IO port (e.g. LPC) if POST codes are enabled. This changes the assumption so that POST codes can be written to the serial console without being written to an IO port. This enables POST codes by default using "default y" to avoid changing current behavior. Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/1685 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24Remove duplicate VGA BIOS interrupt handlersPatrick Georgi
Some boards have two instances of the int15 handler that supports the onboard VGA BIOS, for YABEL and realmode. These are now similar enough that they can be deduplicated. Due to minor differences this requires manual effort. Change-Id: I03ae314cb90dd65d96591ce448504aa961cbeb88 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1893 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-24yabel: Use X86_* instead of the more verbose M.x86.REG_*Patrick Georgi
Makes it more similar to what realmode looks like. Change-Id: I4407431f2d979c43dd186114d67ed11845907afe Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1892 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 23:52:37 +0000