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2015-04-15storm: adjust rombase startup to vboot2Vadim Bendebury
Memory needs to be initialized before rombase proceeds. BRANCH=storm BUG=chrome-os-partner:34161 TEST=boots into depthcharge Change-Id: Id16b17685ff15c2a69d630eb8042e15549ae8b21 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e8aeb38206b806d5656052d0f210faa769e28b8 Original-Change-Id: I0616c7dc7f08332ac0d96d4baf2618b067606fdf Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234544 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9689 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15storm: use different CBFS caches before and after DRAM is availableVadim Bendebury
Booting depthcharge requires much larger CBFS cache, but by the time depthcharge is being booted DRAM is already initialized. Use different memory spaces for CBFS cache before and after DRAM is available. Also, make sure that CBMEM uses memory below CBFS cache in DRAM. BRANCH=storm BUG=chrome-os-partner:34161 TEST=with this change on Storm ramstage finds and boots depthcharge in recovery mode Change-Id: Icd1bbf4bcc5f9d92b2653b5a8891409105a25353 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e1e0b029b7fb09b84784373150cc4ce9eea7b3f5 Original-Change-Id: I33fd97806b2db6fab2adc44b67e5f54258642967 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234543 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15storm: configure/enable vboot2 supportVadim Bendebury
Select vboot NV driver. BRANCH=stotm BUG=chrome-os-partner:34161 TEST=with caches disabled Storm starts up and initializes DRAM successfully. Change-Id: Ib2e509e0c32a7a836a0fc6c0d5d05cc9bf68cbf6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a4cf8b26be99b04774ee3d1eb4b28039813e020 Original-Change-Id: Ie220aade420e1e54e2fa46295d03af494466ab43 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234645 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9687 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15ipq8064: add DRAM initialization codeVadim Bendebury
Read two blobs from CBFS: cdt.mbn (memory configuration descriptor) and ddr.mbn (actual memory initialization code). Pointer to CDT which starts right above the MBN header is passed to the memory initialization routine. Zero return value means memory initialization succeeded. BRANCH=storm BUG=chrome-os-partner:34161 TEST=with upcoming patches memory initialization succeeds. Change-Id: Ia0903dc4446c03f7f0dc3f4cc3a34e90a8064afc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1d79dadd7d47dd6d01e031bc77810c9e85dd854b Original-Change-Id: Ib5a7e4fe0eb24a7bd090ec3553c57cd1b7e41512 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234644 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15ipq806x: add i2c driverVadim Bendebury
this change ports i2c and other relevant drivers from depthcharge for ipq806x. BUG=chrome-os-partner:33647 BRANCH=ToT TEST=Booted storm using vboot2 Change-Id: I3d9a431aa8adb9b91dbccdf031647dfadbafc24c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a0c615d0a49fd9c0ffa231353800882fff6ab90b Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Id7cc3932ed4ae54f46336aaebde35e84125ebebd Original-Reviewed-on: https://chromium-review.googlesource.com/229428 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9685 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15google/storm: prepare enabling vboot2Vadim Bendebury
This change sets up the list of source files for vboot2's verstage without enabling it. BRANCH=storm BUG=chrome-os-partner:34161 TEST=not much testing yet, just successful compilation. Change-Id: I4052c20795459bf0e057c0f0952226ea4a8c89f1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 48847ab8acfbe4b33d61d3d012c72c025cd8f364 Original-Change-Id: I1d7944e681f8a4b113a90ac028a0faba4423be89 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234643 Reviewed-on: http://review.coreboot.org/9684 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15ipq806x: modify imem layoutDeepa Dinamani
With introduction of uber-sbl SRAM usage pattern is changing, this introduces the new memory layout. This patch overlays DDR initialization code with uber-sbl, as uber-sbl goes out of scope as soon as bootblock starts. A 4K block at offset 0x3f000 added in the comments, this is a shared structure used by different QCA modules. This suggested layout is not final, but will allow to move closer to the production image. BRANCH=storm BUG=chrome-os-partner:34161 TEST=with other patches applied Storm boots all the way to rombase and initializes DRAM. Change-Id: I46af81b39b09935aa7fffdabda223e7e64c7a446 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a20c0570361038c0ae406dcb1f4bc657eea120f6 Original-Change-Id: I927f6ffc524fc8f0effd7b91d3f5d1e8d6be1530 Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229023 Reviewed-on: http://review.coreboot.org/9683 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15soc/ipq806x: Disable LPAE mode.Deepa Dinamani
LPAE (large physical address extension) is not available on this SOC core, do not enable it. [pg: we already had this one, but somehow LPAE slipped in again] BUG=chrome-os-partner:27784 TEST=coreboot still comes up on AP148 Change-Id: Iaa80022c611f7377d8f4100487d32654150836d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6e12c39efd54e4fcbd444134bf30e211948a71b Original-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198023 Original-Reviewed-by: deepa dinamani <deepad@quicinc.com> Reviewed-on: http://review.coreboot.org/9682 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15storm: add code for detecting rec/dev/write protect switches' statusDaisuke Nojiri
The gpio access code has been moved to a separate file to match other platforms. Accessor functions are added to read different switches state. They will be read by verstage, when it is enabled, and by ramstage, for passing the values to depthcharge. It is unfortunate that the gpio values are not being cached and can change by the time CBMEM table is filled, but we have to live with that for now. BUG=chrome-os-partner:33756,chrome-os-partner:34161 BRANCH=storm TEST=none yet. Change-Id: I229fed0e35d643912f929671d5fc25aee5d1d167 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e15aa281a1dbf2c463650b6c04991436022d8d4 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I940b54cd3cf046b94d57d59d370e634a70a8bbeb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229426 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9681 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15ipq806x: set architecture to ARMV7Vadim Bendebury
BUG=chrome-os-partner:33646 BRANCH=ToT TEST=Built storm. Change-Id: I4b2cb54369dee7e6e61c2173d2be0f50430123fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0aab7fe31b78bae264cc2e6fa04fe7047315d08f Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ic509e1fd375a320b8e37a07a7f5b9a6fa211ace3 Original-Reviewed-on: https://chromium-review.googlesource.com/229427 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15broadwell: Fixes for _SWS supportDuncan Laurie
- These should be 64bit values so when they try to return -1 it is interpreted properly by the kernel. - The GPE value needs to be reset at the start so it does not return stale data from a previous resume. - If a GPE register is zero the value should only be updated if it has not yet found a set bit. BUG=chrome-os-partner:34532 BRANCH=samus,auron TEST=build and boot on samus, suspend/resume with various wake sources and ensure the reported _SWS values are correct in every case. Original-Change-Id: Ic6897f20ad2f321f3566694c032b75a3db120556 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235012 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit be3c79b87b81563f744eb885708a52730debaccb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I801c6e4f90dde0f5f69685f987a9831ee5e99e4a Reviewed-on: http://review.coreboot.org/9699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-15broadwell: Remove unused bootblock codeDuncan Laurie
This code that stores the initial timestamp is not being used, instead the timestamp is passed to romstage_main(). BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Original-Change-Id: I0e0fa1ba74ab93d4454fdfa12208e712d2ae913c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234402 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 838112cf79e2b4d51e5dc87d5ac9cd7e03807f29) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fd7ba72c14c1e39f7bfa3a1ae8d03289a2abf73 Reviewed-on: http://review.coreboot.org/9698 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-15broadwell: Clean up ME device and add new ME10 flowDuncan Laurie
In order to avoid a 300ms timeout waiting for mbp_cleared flag to be set there is a new flow for the ME10 1.5MB firwmare that we can follow which will save significant boot time. This requires sending new commands that do not generate an ACK message, and ensuring an HMRFPO LOCK message is sent. In addition now that the delay is removed clean up the ME path to do the work in init() step and add a final() step that does the disabling of the PCI device. BUG=chrome-os-partner:30637,chrome-os-partner:34134 BRANCH=samus,auron TEST=build and boot on samus, measure ~300ms speedup in boot time Original-Change-Id: I753087ecd65f6ebed9f812318a359f893e01da9f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234400 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 25aff4b188dc94a99af30869a162e01e3fa8dee7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia35373548a902a718155a1a57057f55067d2f3ac Reviewed-on: http://review.coreboot.org/9697 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-15soc/baytrail: Use microcode from the blobs repositoryMarc Jones
Remove the blobs from the coreboot tree and get them from 3rdparty. Change-Id: I0798091530be9654d7e073839b4efeb3f9c0302c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-15soc/broadwell: Use microcode from the blobs repositoryMarc Jones
Remove the blobs from the coreboot tree and get them from 3rdparty. Change-Id: I4938b5c47e6ae7059eda144b664aeafdd674f0fb Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-15veyron: Add "backlight" GPIO to coreboot tableJulius Werner
This patch adds a new "backlight" output GPIO to the coreboot table in order to avoid redundantly defining that GPIO in the payload. BRANCH=veyron BUG=chrome-os-partner:34713 TEST=Tested together with corresponding depthcharge CL. Change-Id: Ia997beb1a400136ad65d8f0217781c9782f6e8a5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 04ce4c23573cf926aeef3d817d3ab00835f897c7 Original-Change-Id: I69b3c7ac6be4b9723b6a0dfecef5e1c4ea681aff Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242400 Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9652 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15brain: remove sdmmc_power_off() in romstageDavid Hendricks
LDO4 and LDO5 are not turned on with the boot0 and boot1 RK808 strappings that we use on Brain. BUG=none BRANCH=none TEST=built and booted on brain Change-Id: I00393ca54958d9fff926606405edcd84901e4048 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c4c1862585fd058a8a9c8237c701b3bbf3b8aa83 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I846ef9d67a780cc07414d545524b9ec0b8490cf1 Original-Reviewed-on: https://chromium-review.googlesource.com/241734 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9648 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron_danger: Enable EDP display initDavid Hendricks
Danger has EDP, the original code was copied from Brain which didn't. BUG=none BRANCH=none TEST=built and booted on danger Change-Id: Ib8e48078cc51fe0e1fb7049f70e810b8f0a7690a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 25fc6b4d82fb4bd80798cc809af4dacc6208109e Original-Change-Id: Ic8b3f685e08bb96125c57d42db6a10e348a1a096 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/245161 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9679 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15Danger: Apply differences between Brain and DangerDavid Hendricks
This applies the differences between Brain and Danger: - Danger has an SDMMC slot - Danger has a USB hub (TODO) - Danger has LVDS (TODO) - Add workaround for incorrect RAM_ID strapping BUG=none BRANCH=none TEST=emerge-veyron_danger coreboot works Change-Id: Idec527744de2583613b290e3e88850b33ff1c23d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 89278c2eeae4bae989a3549da627c5bbd5dd0d5a Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Iae3f85d4f41e04465a5046f2334c693337d006a4 Original-Reviewed-on: https://chromium-review.googlesource.com/241712 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9647 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15Danger: Initial mainboard importDavid Hendricks
This adds a directory with files copied over from Brain along with build-related changes so that emerge-veyron_danger works. The next patch will account for other differences. BUG=none BRANCH=none TEST=emerge-veyron_danger coreboot works Change-Id: I7ebd431cd48e257dfa761d32013d0e251b4f155d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a0f7d2f96540df6fdcd7a99d9e0fa02bbc6c1f73 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id265a7715f07a647a449f00097bf40f7c9b4c068 Original-Reviewed-on: https://chromium-review.googlesource.com/241711 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9646 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15rk3288: send correct EDID buffer sizehuang lin
decode_edid() parses the whole EDID buffer, regardless of whether there is an extension buffer, so we pass the size of the EDID actually read to prevent EDID parser getting the wrong data. BUG=chrome-os-partner:35053 TEST=Boot from jerry BRANCH=veyron Change-Id: I5951b670f129cf4765a5199cb58ac6abff5478a6 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 4d508647efc0a9d48b2a4b23c12a54b63af2813e Original-Change-Id: I8cd8e09025520322461fe940b01e4af3995b5ecd Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240643 Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: http://review.coreboot.org/9645 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15rk808: Implement RTC driverDavid Hendricks
This adds RTC functions to the existing RK808 driver. BUG=chrome-os-partner:34436 BRANCH=none TEST=with eventlog patches applied to pinky, booted and saw eventlog entries generated with correct timestamps: localhost ~ # mosys -k eventlog list entry="0" timestamp="2015-01-06 13:45:33" type="Log area cleared" bytes="4096" entry="1" timestamp="2015-01-06 13:45:33" type="System boot" count="0" entry="2" timestamp="2015-01-06 13:45:33" type="Chrome OS Developer Mode" Change-Id: I1df70a2ca94ff463ffea8d9f02d951d6c62e6b08 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: a304f7e6954f585f04feef54c4902dcb25a39fcc Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I3a240e342a54b2e7023da71708d0d70f5131f0b9 Original-Reviewed-on: https://chromium-review.googlesource.com/238525 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9643 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron_*: Move PMIC_BUS to a Kconfig variableDavid Hendricks
This moves PMIC_BUS from each mainboard's board.h file to a per- mainboard Kconfig variable. To prevent humans from forgetting to set a valid value, an invalid default is set in the rk3288 Kconfig and checked in rk808.c so that compilation will fail if the mainboard Kconfig does not override it. Originally, PMIC_BUS was only used by mainboard code as an argument to RK808 PMIC functions. To conform to the generic RTC API, however, the RK808 code needs to have the bus number globally defined somewhere since the rtc_get() and rtc_set() functions don't take any args. Since CONFIG_PMIC_BUS is globally visible, we no longer need to pass bus number to the PMIC functions. BUG=chrome-os-partner:34436 BRANCH=none TEST=built and booted on Pinky Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I73783878e507b2e7b1526dd2f81cfbdf8f1e2a55 Reviewed-on: https://chromium-review.googlesource.com/240203 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9642 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15rk3288: Implement support for CRYPTO module and use it in vboot hashingJulius Werner
This patch implements support for the CRYPTO module in RK3288 and ties it into the new vboot vb2ex_hwcrypto API. We only implement SHA256 for now, since the engine doesn't support SHA512 and it's very unlikely that we'll ever use SHA1 for anything again. BRANCH=None BUG=chrome-os-partner:32987 TEST=Booted Pinky, confirmed that it uses the hardware crypto engine and that firmware body hashing time dropped to about 1.5ms (from over 70ms). Change-Id: I91d0860b42b93d690d2fa083324d343efe7da5f1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e60d42cbffd0748e13bfe1a281877460ecde936b Original-Change-Id: I92510082b311a48a56224a4fc44b1bbce39b17ac Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236436 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/9641 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron: add H9CCNNN8GTMLAR sdram in speedyJiazi Yang
BRANCH=None TEST=emerge-veyron_speedy coreboot BUG=None Change-Id: Iab377e93472db0b7778df020afa84ee97f0e4079 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: fedf6ed7dc220d58ad10d49ac9ea02443746e77e Original-Change-Id: Id5024bfd32a0aa1fb00f3af8dc337ccccaf40729 Original-Signed-off-by: Jiazi Yang <Tomato_Yang@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/237544 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Trybot-Ready: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9640 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron: Support Speedy v1 hardwarehuang lin
BUG=None TEST=emerge veyron_speedy and boot the Speedy board BRANCH=None Change-Id: Ida5fd6d839a2e704760a90e9c723c1b688ea6a84 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 42c0d11c3ec65874986c06ca4d7b34f5987f9409 Original-Change-Id: I2f0cff74517a8c031eabb64f4f82d455195c8dd1 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234715 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9639 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15Brain: Apply differences between Jerry and BrainDavid Hendricks
This applies the differences between Jerry and Brain: - No EC - No SD card - Minor changes to GPIOs (no lid, power button active low) - No variations between board IDs (yet) - No backlight/display attached, but we do have some HDMI and VOP configuration (need to double check that it's right). BUG=none BRANCH=none TEST=built and booted on Brain (requires follow-up CL to get into depthcharge) Change-Id: Idbbc19856e05a145637c28d87c3e19855d13f03b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 67151129c28ca7dd83464e5a5c183d006299293c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I3c761d3d4d186a6208a772c05193bdcbd4a5c105 Original-Reviewed-on: https://chromium-review.googlesource.com/235921 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9638 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15Brain: Initial mainboard importDavid Hendricks
This adds a directory with files copied over from Jerry, in addition to build system related changes (configs/* and Kconfig stuff) necessary to emerge-veyron_brain coreboot. The next patch will account for differences between Jerry and Brain. BUG=none BRANCH=none TEST=emerge-veyron_brain coreboot works Change-Id: Ib0da9caf80f46991b96bcb5756f807237f0902e1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9509d6277dae25a78062c1301054a39f704b33fe Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I972f2623d9b0a43e3ea5312b3c4cd34ab44edc36 Original-Reviewed-on: https://chromium-review.googlesource.com/236989 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9637 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15blaze: add new Micron 2GB BCTNeil Chen
This BCT table is the same as "ramcode == 1", and has been pass the stress test with this new Micron type. -Micron MT41K256M16LY-107:N, ramcode = 4 BUG=chrome-os-partner:32071 TEST=emerged coreboot, booted successfully into kernel. Change-Id: I80990fec6faf5dd2b8090658d865cc8dde31b753 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: bce2bf1fd518077e06d70d78a65d58ddef7b7bc6 Original-Change-Id: I2c0b28fdafb5299784519e641aa4edb53d0c36b2 Original-Signed-off-by: Neil Chen <neilc@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/236514 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron: Fix TPM I2C initialization and sync boardsJulius Werner
Due to a missing i2c_init(), we were actually running our TPM with default divisors at 660KHz. Oops. While it's commendable that both the TPM and our controller seem to have been running fine all this time at more than 1.5 times the maximum frequency they support, we should probably still get that fixed. Also sync Speedy back up to the other Veyron boards since it seems to have missed a recent SDMMC patch. BRANCH=None BUG=None TEST=Booted Pinky. Change-Id: I255c66624b21bf48b12f950208ba2c401a75c4e4 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f2bd7c8579cd90d2f800c777c1981557d81a9b49 Original-Change-Id: I43e6b5fe02aca605a5b243c5b876bd44b90b2bf9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236580 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9634 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron_*: Use common CBFS wrapperDavid Hendricks
This switches all the rk3288 platforms to use the common CBFS wrapper instead of implementing its own CBFS media driver. It also happens that veyron_* platforms use Gigadevice SPI flash (at least for now). As we use more SPI-related stuff, for example eventlog and vboot data in Brain's case, we will need to use more of the SPI API anyway. This prevents us from having to duplicate pieces of it for rk3288. BUG=none BRANCH=none TEST=built and booted on Pinky Change-Id: Ie462456814646fdc277485d9e2d8c901fd4936e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2d6df2fe6d78bc8eee8689019b9aaf29c82b6b30 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id307bd5fb6cc8f79411d8c66e1370e80c58d017b Original-Reviewed-on: https://chromium-review.googlesource.com/235882 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9678 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-15veyron: Support Mighty v1 hardwarehuang lin
BUG=None TEST=emerge veyron_mighty and boot the Mighty board BRANCH=None Change-Id: I0047569c9eed7a3881500ba3b05e6726ba8d7b8f Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 49366e5bb3ecdec38c898c936392e5d77a91cd53 Original-Change-Id: I3fcdc837e8d7e62c145850f549662d8260aa1120 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234714 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9633 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron: Support Jerry v3 hardwarehuang lin
BUG=None TEST=emerge veyron_jerry and boot the Jerry board BRANCH=None Change-Id: I38cb0106694ada431e6ab6194fce7ba1822bcbcf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6a061072860f74874f0098062806c01bdcb447bd Original-Change-Id: I6eb0900516bcd95159c472749c54d356448d2344 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234713 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9632 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron: Support Pinky v4 hardwarehuang lin
BUG=None TEST=emerge veyron_pinky and boot the Pinky board BRANCH=None Change-Id: I75bc1b7681c9a3d7dc2868a2b260884538587dbd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 66069927618924af02a4e17503fa49ae2c31fdfc Original-Change-Id: I06242ade0cabbba56b16b3832a1b4b09bec6f06b Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234712 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9631 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron: Move backlight gpio control to mainboard.chuang lin
We use the devicetree to pass the backlight control gpio before, but if there have different board version, and it uses different io to control backlight, it will hard to distinguish it. So, we move the backlight control to mainboard, and use board_id to distinguish the backlight control. BUG=None TEST=emerge veyron_pinky and Boot the pinky board BRANCH=None Change-Id: Ifa81eb2455296f4b4285b681208f4393f266fb34 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 2ff7f65134dcf97f97757750eab41dcf8c7765d3 Original-Change-Id: I1ec8e04f4982c3a8c7e31d8dc2c75311b7199ffc Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234711 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9630 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron: Trigger hard reset (via GPIO) if last reboot was caused by watchdogJulius Werner
Like Nyan, Veyron boards use a GPIO to reset the system so that we can make the accompanying TPM reset secure and unforgeable. The normal kernel reboot driver knows that, but the SoC-internal watchdog doesn't. This patch implements a check for the global reset status register in the early bootblock and triggers a hard_reset() when it matches "first global watchdog reset" or "second global watchdog reset". Seems that the difference between the two is is a choice controlled by wdt_glb_srst_ctrl (unconfirmed), and we want this code to run in both cases. BRANCH=None BUG=chrome-os-partner:33141 TEST=Run 'mem w 0xff800000 0x9' from the command line, watch how you end up in recovery without this patch but can boot normally with it. Change-Id: Ice79648831e1e97d22325711da9e82bbf6bf3c75 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 5d7cb52b2c2dcb2fff0bf83fc168439dade4b1b7 Original-Change-Id: I2581bde84f0445c15896060544e9acb60de91c8c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/231734 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9629 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron_speedy: Support Samsung-4GB and Lynix-4GB LPDDRhuang lin
Add the Samsung-4GB and Hynix-4GB LPDDR inc files. Use ram_id 1000 correspond to Samsung-4GB LPDDR and use ram_id 1001 correspond to Hynix-4GB LPDDR. BUG=chrome-os-partner:33269 TEST=Boot veyron_speedy normal BRANCH=None Change-Id: I21983c48e1e99aa70ae9bb3fb6550ae9af472015 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d34b19dc9b57b4f31dc1b28581f3f8fc0fcc7e6b Original-Change-Id: I55b6968c642df8c1f579e518232ab5d278e7e12f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233859 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9628 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron: Add veyron_speedy boardhuang lin
Essentially a copy of veyron_jerry for now BUG=chrome-os-partner:33269 TEST=emerge-veyron_speedy coreboot BRANCH=None Change-Id: If8f32122e301df1766bca68b11efd8afe8be5e87 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f49a151e1dd956ed2cf3ba0b1f9307442b61e639 Original-Change-Id: Ife457db4fd67fe69bcd4082694b3372eccfb304b Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/233822 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9627 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron: Turn off SD card power in romstageJulius Werner
The only way to reliably reset an SD card in an unknown state is by power-cycling. Since a kernel may crash and reboot at any point, SD cards may be left in one of them fancy high-throughput modes that depthcharge (or, in fact, a newly booting kernel without prior knowledge) doesn't support, so we need to reset the card on every boot. This patch adds support to turn off an RK808 regulator completely and uses that to turn off SD card power rails in early romstage. The time until configure_sdmmc() in ramstage turns them back on should be more than enough to drain the power rail for an effective power-cycle. BRANCH=None BUG=chrome-os-partner:34289 TEST=Booted a Pinky from SD card, noticed that it works before and after this patch. Change-Id: Iaa5f7adaa59da69a964785c5e369ad73c6620224 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 95fba21907f1f3f686cb5a95b993736247db8f96 Original-Change-Id: I904b2d23ca35f765c000f9bee7637044f674eff9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/233713 Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Original-Tested-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9626 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15rk3288: implement spi_crop_chunk()Patrick Georgi
This function was added in upstream but was missing in Chromium OS Change-Id: I35debf65153e5f280343eebfe91438ecf665ba22 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9677 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15Kconfig: Fix incorrect CONFIG_STACK_SIZE values for X86 and ARM64Julius Werner
Commit 54229a7 (arm: Fix checkstack() to use correct stack size) didn't quite hit the mark. Due to the crazy way our Kconfig includes work, It accidentally set CONFIG_STACK_SIZE to 0 even on architectures that need it. This patch fixes the issue by moving everything back to a single entry in src/Kconfig, making sure we end up with the intended numbers on all architectures. BRANCH=None BUG=chrome-os-partner:34750 TEST=Built for Pinky, Urara, Falco and Ryu. Confirmed that the generated .config contained CONFIG_STACK_SIZE=0x0 for the former two, and CONFIG_STACK_SIZE=0x1000 for the latter. Original-Change-Id: Ib18561925aafe7c74e6c4f0b10b55000a785e144 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236753 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit c64b127e163f98162f3f7195b6ed09bd5a4b77c4) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I2c747b04760bc97f43523596640bfb15317e5730 Reviewed-on: http://review.coreboot.org/9696 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-04-14Add console wrapper for UART driverVadim Bendebury
Coreboot is designed to have a single serial console at most, on top of that it may have a CBMEM (virtual) console. Matters are complicated by the fact that console interface is different between bootblock and later stages. A linker list of console driver descriptors is used to allow to determine the set and type of console drivers at compile time. Even though the upstream seems to have done away with this approach, which does not seem the best idea. As an alternative this patch introduces a common wrapper which different UART drivers can plug in into. The driver exports a single API which can be used both directly (in bootblock) and through the wrapper (in later stages). The existing drivers can be adjusted to fit this scheme one by one. The common UART driver API also aligns fine with the upstream approach. BUG=chrome-os-partner:27784 TEST=none yet Original-Change-Id: Id1fe73d29f2a3c722bd77180beebaedb9bf7d6a1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196660 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 94a36ad79a96f83d283c0fd073b05f98ae48820c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id1fe73d29f2a3c722bd77180beebaedb9bf7d6a1 Reviewed-on: http://review.coreboot.org/7872 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14storm: do not enable the ethernet switch by defaultVadim Bendebury
The ethernet switch, as soon as it is taken out of reset comes up in default (bridging) mode, which allows traffic to flow freely across the ports. Let's keep it in reset such that there is no cross port traffic happening while the device boots up. BRANCH=storm BUG=chrome-os-partner:32646 TEST=verified that the switch is held in reset during boot. Change-Id: Ia1dbb47d892d564145da17425a596bf9bad40d29 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 50551d8c9a44d1b63e0948070f6573adf7729d37 Original-Change-Id: I6bf698beddc98ce18fee6b3b39622e356c8cfbad Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224989 Original-Reviewed-by: Toshi Kikuchi <toshik@chromium.org> Reviewed-on: http://review.coreboot.org/9465 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14samus: Declare TPM in devicetree.cb and include ACPI deviceDuncan Laurie
This adds the TPM device to the devicetree and configures an active high edge triggered interrupt at IRQ10 and adds the ACPI Device for the TPM into the DSDT. It also cleans up the EC PNP ID to use the EISAID for an EC since there are now two PNP devices declared, and removes the unused ENABLE_TPM define at the top of the DSDT. BUG=chrome-os-partner:33385 BRANCH=samus TEST=build and boot on samus, ensure TPM is functional at IRQ10 CQ-DEPEND=CL:226661 Change-Id: I4b9b016014d136fbf9a37003003632821ae93a53 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0420e27b05d0f1568efa9beb849e0e8ff5995c86 Original-Change-Id: I2660cb30ac535da0b255603a619b9c09681ca947 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226663 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14broadwell: Remove TPM device from lpc.aslDuncan Laurie
This is not a standard feature so it should be included by the mainboard if it is actually present in a system. BUG=chrome-os-partner:33385 BRANCH=samus,auron TEST=build and boot on samus CQ-DEPEND=CL:226663, CL:226664 Change-Id: Id4d0e5ed243dcb95e64fb8c848667f651b75aa4e Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 8909913f5c11c5805c77a3373859634b02a301e2 Original-Change-Id: Ib7c171a5a007a2dddfb3d80341c6dc488e383e99 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/226662 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14wtm2/samus: fix coreboot compilation error with tpmp removedHarry Pan
Since CL:226662, all TPMP accessing should be removed as well, else it will cause wtm2 coreboot failed on build. BUG=none BRANCH=none TEST=./setup_board --board=fox_wtm2 && emerge-fox_wtm2 coreboot CQ-DEPEND=CL:226662 Change-Id: Ib25f2d32997ef82b0ebf049803f2c5002a0a3abf Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: c99456bf42544518e2a36b6e0bbfe7f4ee1b4aff Original-Change-Id: Ia0eebb1924bbb23979c880f7d05600a0cf1e4ca3 Original-Signed-off-by: Harry Pan <harry.pan@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/232165 Original-Reviewed-by: Wei Shun Chang <wei.shun.chang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9477 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14urara: increase drive strength for SPIM1 MFIOsIonela Voinescu
This change is made only to make sure there is a good signal strength on the SPIM lines. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works properly BRANCH=none Change-Id: I5b9427b14a407746fb5b707fa3b07a1a6774bfb1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e9d953283a5b43bf967128ca73db0e90c2df32df Original-Change-Id: Ia589134cf0557613697d49fb0bdb1848af66f0e8 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/249732 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14urara: setup I2C0 clock and MFIOsIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works properly BRANCH=none Change-Id: Ic805311d3aaf40da601c88cd05a73254088374bd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: ad9427c069ed34ab91e93df59ec3361499b54982 Original-Change-Id: If8e142273afd2d591a975f4e7e34aa73e8d71b0c Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250451 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9674 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14pistachio: implement clock setup for I2C0Ionela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; I2C0 clock is set up properly. BRANCH=none Change-Id: I15ffc5f7d8e8aadfc3cd249284bc492d0d13d9a1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6404ab6ad12ea1579eaf5ae55a9eddd9bd9f96e2 Original-Change-Id: Iafdf492291b47f0088f3b5e621d630b8d21ab106 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250450 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9673 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14urara: Reduce MIPS PLL jitterIonela Voinescu
The current MIPS PLL is configured in such a way that there is excessive jitter. Correct this by applying new PLL settings. The resultant frequency is 546MHz instead of 550MHz. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board as part of the JTAG loading script; BRANCH=none Change-Id: Ica1bfff29e01819b86cd2bb8b18d8adc9dfa3260 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0c04354b49b73d234492521d81b6600d487175b0 Original-Change-Id: I28b41b1e82dbdf9da21bf0ab74f9722cdad923f1 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245620 Original-Reviewed-by: James Hartley <james.hartley@imgtec.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-on: http://review.coreboot.org/9671 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 13:30:50 +0000