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2015-11-05mainboard: Remove last_boot NVRAM optionTimothy Pearson
The last_boot NVRAM option was deprecated and removed in commit 3bfd7cc6. Remove the last_boot option from all affected mainboards to eliminate user confusion. Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12316 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-11-05src/amd: Increase maximum blootblock execution countTimothy Pearson
Most AMD hardware requires at minimum two warm resets when booting from S5 (power off). This is uncomfortably close to the maximum bootblock execution count, and has resulted in unstable normal/fallback operation on some machines. Increase the default max bootblock execution count before fallback to 6. This translates to roughly 2 - 3 failed boots before fallback mode will engage, with an absolute worst case of pushing the reset button 5 times to engage fallback mode in the absence of a dedicated recovery jumper. Change-Id: I1911f1b77f168835b516e6a915d5b6949f47219a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12317 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-04nb/intel/sandybridge: Add ACPI DMAR tableNico Huber
Add a DMAR table to advertise IOMMU and IRQ remapping capabilities to the OS. Tested with kontron/ktqm77. Under Linux, the table is detected and interrupt remapping is enabled automatically. Change-Id: Id6ee601a0a8543ed09c6bb8d308a3a3549fc34e5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12195 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04nb/intel/sandybridge: Enable basic IOMMU supportNico Huber
Sandy Bridge and Ivy Bridge processors have two IOMMU units. One for the integrated graphics controller and one for all other PCI devices. Assign resources for both IOMMUs and apply some quirks. Tested with kontron/ktqm77 and a Muen based system that makes use of the IOMMUs. Not tested on Sandy Bridge, but register dumps show the same settings that are applied here. Change-Id: I43b5e20b750e7529f448acac35de173185678fd9 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12194 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04sb/intel/bd82x6x: Assign unique bus/dev/fn for I/O APIC + HPETsNico Huber
Assign unique bus/dev/fn values for the I/O APIC and each HPET. The values are taken from an example DMAR table. They are used as source-id for MSI requests and as completer-id for reads from the device' MMIO space [1, 2]. The former is usefull for source-id verfication during interrupt remapping. [1] Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet Document-Number: 324645 [2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) Datasheet Document-Number: 326776 Change-Id: Ib46f8cfb7d966dd1cf2b026f671bc45ffcc43d25 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12193 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04mainboard/asus: Increase reboot count on boards with recovery jumperTimothy Pearson
On server boards with a recovery jumper, having the fallback path less sensitive to power fluctuations or BMC issues makes sense. Increase the maximum number of boot attempts before automatic fallback to 10 on these boards. Change-Id: Iabe0b0cbf332686db8e9380a8b65a1477173599c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12320 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-04ACPI: Add functions for DMAR I/O-APIC and HPET entriesNico Huber
Refactor acpi_create_dmar_drhd_ds_pci() and add similar functions for I/O-APICs and MSI capable HPETs. We violate the spec [1] here, which talks about 16-bit source-ids spread over start_bus and path entries. Intel actually uses bus/dev/fn identification for those devices too, and so do we. [1] Intel Virtualization Technology for Directed I/O Architecture Specification Document-Number: D51397 Change-Id: I0fce075961762610d44b5552b71e010511871fc2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12192 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04ACPI: Make DMAR flags settableNico Huber
Add a parameter to acpi_create_dmar() for the flags field and define flags given by the spec [1]. [1] Intel Virtualization Technology for Directed I/O Architecture Specification Document-Number: D51397 Change-Id: I03ae32f13bb0061bd3b9bef607db175d9b0bc5e1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12191 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04Drop SuperIO smsc/fdc37m60xStefan Reinauer
All boards using this SuperIO have been removed from the tree already. Change-Id: I52847bc2fc16b27ac0de0bc7c847221b1e5cb744 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12245 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-03arch/x86/bootblock_normal: Fix failure to buildTimothy Pearson
Fix a function call in the normal path using the original function name and arguments in code that was changed in commit 3bfd7cc6 (drivers/pc80: Rework normal / fallback selector code) This commit reworked most of the fallback / normal code, however the normal code paths were not fully tested by Jenkins, so this was missed. Change-Id: Ied66334977272a13b7a7307ff4d9f34eb22040aa Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12315 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-11-03drivers/pc80: Rework normal / fallback selector codeTimothy Pearson
Per IRC and Gerrit discussion, the normal / fallback selector code is a rather weak spot in coreboot, and did not function correctly for certain use cases. Rework the selector to more clearly indicate proper operation, and also remove dead code. Also tentatively abandon use of RTC bit 385; a follow-up patch will remove said bit from all affected mainboards. The correct operation of the fallback code selector approximates that of a power line recloser, with a user option to attempt normal boot that can be cleared by firmware, but never set by firmware. Additionally, if cleared by user, the fallback path should always be used on the next reboot. Change-Id: I753ae9f0710c524875a85354ac2547df0c305569 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12289 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-03cpu/amd/model_fxx: Backport PowerNow! core count fix from Family 10hTimothy Pearson
The K8 PowerNow! state generator does not generate _PSS objects for nodes other than the first CPU package. This patch backports the PowerNow! core count fixes for Family 10h to the K8 CPUs. Change-Id: I7b411ab75155dfb4bf51ae04301aa16fb2ae89f3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12286 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-03via/cx700: remove unused #definePatrick Georgi
Change-Id: I0180e0ae2aeeffcef46a97892356f1955f581efd Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/12295 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-03cbmem: add coreboot table records for each cbmem entryAaron Durbin
In order to not expose the cbmem data structures to userland that are used by coreboot internally add each of the cbmem entries to a coreboot table record. The payload ABI uses coreboot tables so this just provides a shortcut for cbmem entries which were manually added previously by doing the work on behalf of all entries. A cursor structure and associated functions are added to the imd code for walking the entries in order to be placed in the coreboot tables. Additionally a struct lb_cbmem_entry is added that lists the base address, size, and id of the cbmem entry. BUG=chrome-os-partner:43731 BRANCH=None TEST=Booted glados. View coreboot table entries with cbmem. Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11757 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
TEST: Booted ASUS KGPE-D16 with single Opteron 6380 * Unbuffered DDR3 DIMMs tested and working * Suspend to RAM (S3) tested and working Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02cpu/amd/family_10h-family_15h: Use correct label for break stateTimothy Pearson
Change-Id: I07e517f239807cbe76037308f0beff80c9a6f2ba Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12101 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2015-11-02cpu/amd: Move model_10xxx to family_10h-family_15hTimothy Pearson
Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02northbridge/amd/amdmct/mct_ddr3: Fix S3 suspend overrunning the stack size limitTimothy Pearson
Change-Id: Id7441dacef2e46e283d1fc99d5e5fa3f20e0d097 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11959 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02mainboard/asus/kgpe-d16: Set DDR3 memory voltage based on SPD dataTimothy Pearson
Change-Id: I21777283ce0fd3c607951204a63ff67dc656c8cc Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11956 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02northbridge/amd/amdfam10: Set DIMM voltage based on SPD dataTimothy Pearson
Change-Id: I67a76cf0e4ebc33fbd7dd151bb68dce1fc6ba680 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11957 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-02amd/olivehillplus: Tidy up devicetreeKyösti Mälkki
Some comments and leftover static USB devices whose function numbers changed. Change-Id: I4d7c7499fe436588ef7e5ae030212c2638a4505f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12263 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02asrock/e350m1: Add ACPI S3 supportKyösti Mälkki
To store memory configuration in SPI flash currently adds some 150 ms delay in ramstage, visible in timestamps listing at 75:cbmem post. Change-Id: I1160259054b58e9a8df2a105c730e0f4140be1f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12215 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-02asrock/e350m1: Match super-io GPIO configuration with vendorKyösti Mälkki
Disables mouse ps2 data/clock signals, not connected in hardware. Purpose of other GPIOs is not really known, but match them with superiotool dump taken from vendor bios. Change-Id: I7b549fbd7dd3fa4cbd507d76882b60bc324a4bd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12214 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-02superio/nuvoton/nct5572d: Add missing logical devicesKyösti Mälkki
While the actual pins behind these devices are not exposed on the chip, the enable registers are implemented in hardware. Allow to turn these LDNs off, like the vendor bios for asrock/e350m1 does. Change-Id: I4d6d5a8de12b09095138cacbad62b2dfbbe54028 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/12213 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-02mainboard/asus/kfsn4-dre_k8: Fix ramstage using Family 10h structsTimothy Pearson
Several ramstage files were inadvertently using Family 10h-specfic structures, causing unstable operation. Use the K8-specific structures instead. Change-Id: I64066dfdca83557393499b77726051e25b814381 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12290 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-31northbridge/amd/amdfam10: Correct S3_DATA_POS type from int to hexTimothy Pearson
This resolves a Kconfig warning. Change-Id: Ic77c8bf89613c116dfdc73572709aeb354e33b2a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12287 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-10-31mainboard/asus/kgpe-d16: Add initial Suspend to RAM (S3) supportTimothy Pearson
Change-Id: I7da84b064287a445fd75a947e2f96ce1ae30d3de Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11954 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-10-31northbridge/amd/amdfam10: Update RAM speed table with DDR3 valuesTimothy Pearson
Change-Id: I8ab7b2cd9bf36d53b744a11d32dd40c750149567 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31southbridge/amd/sb700: Remove acpi_get_sleep_type for early CBMEMTimothy Pearson
The acpi_get_sleep_type function in SB700 ramstage is only needed for boards / CPUs that require late CBMEM initialization. Providing this function in early CBMEM-compatible boards breaks building of the ACPI S3 code due to multiple definitions of acpi_get_sleep_type. Change-Id: Ieebc2640a586812e3e2bfd410987205d64147314 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12267 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31intel/gma: Return success for Intel int15 VGA set panel type hookKonstantin Aladyshev
One of the interrupts in intel_vga_int15_handler lacks positive return status. Write correct status to avoid error messages in log. TEST=With this change `int15 call returned error` is not shown anymore on a custom board with Intel Atom CPU, i945GME northbridge and i82801gx southbridge. Change-Id: I740b2df9bd6a7d261d89bef74b924edbb64354aa Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/12255 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package supportTimothy Pearson
The existing KFSN4-DRE support hung during ramstage while initializing AP #3 if a second CPU package was installed. After analyzing the Sun Ultra 40 M2 support code it became apparent that the K8 code cannot function correctly if sequential RAM training is disabled, and that there were a few other missing calls. This patch adds the missing calls, adjust the CAR space to an appropriate level, and explicitly defines the link numbers and connections in devicetree.cb TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed. Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12285 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-31arch/x86: avoid race condition on build.hPatrick Georgi
Change-Id: I15375ac1247b7cc8d80d910a767c7f3e67eb8739 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-31sandybridge: Disable parallel CPU initializationNico Huber
Disable the parallel CPU initialization for model_206ax, that is Sandy Bridge and Ivy Bridge processors. We never did it the way that Intel recommends and it became unreliable with the introduction of SMM_MODULES in commit a3e41c0 Migrate 206ax to SMM_MODULES. Tested by booting kontron/ktqm77 2.6k times into Linux user space. No issues so far. Change-Id: Idffc352341419f22a36bf772534a5e11e711edf1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-30cpu: port amd/pi to 64bitStefan Reinauer
Change-Id: I66ef081fa1a520f0199366587800783ea1ef8719 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11023 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2015-10-30Drop SuperIO nuvoton/nct6779dStefan Reinauer
All boards using this SuperIO have been removed from the tree already. Change-Id: I57eacf2a88077d0d0bffdcf44b3c2ecbd301e625 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12242 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop SuperIO ite/it8661fStefan Reinauer
All boards using this SuperIO have been removed from the tree already. Change-Id: Ifca91ae44ab222371808ff1e0027a7cbd4646b0a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12243 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop SuperIO nuvoton/nct6776Stefan Reinauer
All boards using this SuperIO have been removed from the tree already. Change-Id: Ic5604c75de249b945dca58aa904edec86558d3ec Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12241 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop SuperIO nsc/pc97307Stefan Reinauer
All boards using this SuperIO have been removed already. Change-Id: I667a8d15a2d16671115f62de656b1c5c6a8259b9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12240 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop SuperIO nsc/pc8374Stefan Reinauer
All boards using this SuperIO have been removed from the tree. Change-Id: I1d13ec7c5f27e82523612af7f07fca3176953600 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12239 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop southbridge intel/esb6300Stefan Reinauer
All mainboards using this southbridge have been removed from the tree already. Change-Id: I4398ef1e270bd0f36c5dd1c6ec3bfec6c2c091e6 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12238 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop southbridge intel/i82801cxStefan Reinauer
All boards using this southbridge have been removed from the tree already. Change-Id: I08269931d845d1f57b34174238bcce245ad77894 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12237 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop northbridge/i440lxStefan Reinauer
All boards using it have been deleted a long time ago. Change-Id: Ib1c4018ab6ec27868c0e2fdbf9c91323ead076fb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12236 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30wakeup: Switch back to 32bit mode firstStefan Reinauer
On x86_64 we need to leave long mode before we can switch to 16bit mode. Oh joy! When's my 64bit resume pointer coming? Why didn't this get caught earlier? Seems the Asrock E350M2 didn't do Suspend/Resume? Yes, I know it's Intel syntax. Will be converted to AT&T syntax as soon as the whole thing actually works.. 8) Change-Id: Ic51869cf67d842041f8842cd9964d72a024c335f Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11106 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop geode_post_code.hStefan Reinauer
It's unused and empty. Change-Id: Ieb9225083cb779b7b94ca47488dad4d7beb30a94 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12235 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30smm: 64bit fixesStefan Reinauer
Change-Id: I35dab4e66514948aafa912d993fb8d42c5a520a0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11089 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30Drop unused code from gcc-intrin.hStefan Reinauer
Change-Id: I3df66320d0bc18221f947b47e7f09533daafabad Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11108 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30AMD mainboards: Fix 64bit BiosCallOuts.cStefan Reinauer
Change-Id: I0f3297dff47dfb44da034ac6f305dcf1981b9de1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30cpu/amd: Fix cbtypes.h to match UINTN conventionStefan Reinauer
There are some inconsistencies in AMDs APIs between the coreboot code and the vendorcode code. Unify the API. UINTN maps to uintptr_t in UEFI land. Do the same here. Also switch the other UEFI types to map to fixed size types. Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Scott Duplichan <scott@notabs.org> Reviewed-on: http://review.coreboot.org/10601 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30vendorcode/amd: 64bit fixesStefan Reinauer
Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11081 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 03:09:39 +0000