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2018-09-02mainboard/google/kahlee/var/liara: Enable Synaptics touchpad deviceCrystal Lin
Enable Synaptics touchpad device for liara BUG=b:113309346 BRANCH=master TEST=Verify touchpad on liara works with this change Change-Id: Icdafe34a00fd55d5338fa07ffa304e48e7b85e7b Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-31google/cheza: Adjust FMAP to fit new requirementsJulius Werner
This patch overhauls the Cheza FMAP, removing some sections we don't seem to need (RW_CDT, the two RW_XBL_BUFFERs, and the second copy of RW_DDR_TRAINING), and adding new sections we're going to need soon or should have had anyway (RO_DDR_TRAINING, RO_FSG, RW_LEGACY). Make more use of implicit offsets and sizes, because we can and because it should make future adjustments easier. Change-Id: I0bd9e59e9cfa162c478c4bd1f048fcac61ad5062 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: T Michael Turney <mturney@codeaurora.org>
2018-08-31mb/google/kahlee/variants/liara: Update Audio/H1/TP i2c timingsChris Zhou
After adjustment on Liara Proto Audio: 399.2 KHz H1: 398.3 KHz TP: 399.0 KHz BUG=b:113319200 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage measure by scope Change-Id: Ibba8c823ed8451a804cf731d49e7568a94ac7c6b Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-31siemens/mc_apl1: Correct the Tx signal from SATA interfaceMario Scheithauer
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-08-30mb/google/poppy/variants/nautilus: Set grip sensor thresholdSeunghwan Kim
Set threshold parameter for grip sensor STH9321 .ProxCtrl6: 75 .ProxCtrl7: 99 BUG=b:113303916 BRANCH=poppy TEST=Built and verified parameter passed to driver Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Enrico Granata <egranata@chromium.org>
2018-08-30soc/intel/cannonlake: Fix comment errors for SMBUSLijian Zhao
On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4, previous comment in southbridge.asl mention it as Function 3 that was a mistake. BUG=N/A TEST=N/A Change-Id: I29786457379809b6fcb592e1136ff612539e24dc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-30riscv: update the definition of intptr_t/uintptr_tXiang Wang
These RISC-V ABIs defined by GCC : ilp32 ilp32d ilp32f lp64 lp64d lp64f. Through this we know that the length of the long's bit is equal to pointer. So update this code. This's more flexible. Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27768 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()Richard Spiegel
Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL, which was deprecated in favor of a public PCI register (though only the bits to enable debug port became public) 0x90. Therefore code needs to be updated. BUG=b:69231009 TEST=Build and boot grunt. Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-30mb/google/octopus: Add missing IOstandy settings.Shamile Khan
Also removed internal pull ups for CX_PREQ_L and CX_PREQ_L signals as they have external pull ups. BUG=b:110654510 TEST=On Yorp Proto 2, flashed image and verified that it boots to OS. Checked Wake-on-Wifi works with both cnvi and pcie modules. Also executed a few suspend resume cycles. Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/28328 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30soc/intel/cannonlake: Update PMC base address for CNP H and LPMaulik V Vaghela
PMC base address is different for CNP LP pch and CNP H pch. Added logic to determine PMC base addrress dynamically based on PCH ID. BUG=none BRANCH=none TEST=Boot Coffeelake U RVP board and check if PMC base address is determined correctly. Change-Id: I833395260e8fb631823bd03192a092df323250fa Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27523 Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-30drivers/intel/gma: Fix OpRegion Mailbox3 backlight changeNico Huber
We should always update BCLP, no matter if the driver is ready yet to process the request. This way it will hold the current value when the driver initializes. Change-Id: I4b091d744f95da39abe542966f0a8589a187573b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-30drivers/intel/gma: store uint8_t brightness values in mailbox3Alexander Couzens
The _BCM function requires a percentage value. While the brightness in mailbox3 requires a value in uint8_t. Meaning 255 = 100%. Previous implementation stored the percentage brightness value resulting in limiting the brightness to ~40% of it's maximum power. Only affects brightness control using mailbox3. Fixes: 6838aaebf9ec ("drvs/intel/gma/acpi: Add methods to use MBOX3") Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/28345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-29mainboard/google/kahlee: Enable EC firmware update screenMartin Roth
Grunt takes a few seconds to update the EC, so display a notification screen while that's happening. BUG=b:113286040 TEST=Boot Grunt with old EC firmware, see update screen Change-Id: I95fc4d3430bac66c09f57a4d34abde08752e5f0e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-28lib/gpio.c: Validate num_gpioRichard Spiegel
In function _gpio_base3_value(), if num_gpio is 0 it'll cause the return of an undefined value, as no for loop will be executed. Assert that it's not 0. BUG=b:112253891 TEST=Build and boot grunt. Change-Id: I2b6537900fa41ebbee0171959f3ce236d360bc80 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28mb/google/octopus/variants/meep: Add weida touchscreen supportTony Huang
Add weida touchscreen support BUG=none BRANCH=master TEST=emerge-octopus coreboot, and verified that touchscreen works on meep. Change-Id: I4352322820237e4c2289410af6643e15109060a1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-28soc/intel/cannonlake: Change LPDDR4 to MEMCFGLijian Zhao
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to make the infrasturture to handle both LPDDR4 and DDR4 cases in the future. Consider the case of reading SPD from SMBus other than providing SPD pointer directly. BUG=N/A TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28248 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28acpi: Hide Chrome and coreboot specific devicesDavid Wu
Some ACPI interfaces introduced by Chrome or coreboot do not need drivers outside ChromeOS, for example Chrome EC or coreboot table; or will be probed by direct ACPI calls (instead of trying to find drivers by device IDs). These interfaces should be set to hidden so non-ChromeOS systems, for example Windows, won't have problem finding driver. Interfaces changed: - coreboot (BOOT0000), only used by Chrome OS / Linux kernel. - Chrome OS EC - Chrome OS EC PD - Chrome OS TBMC - Chrome OS RAMoops BUG=b:72200466 BRANCH=eve TEST=Boot into non-ChromeOS systems (for example Windows) and checked ACPI devices on UI. Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1078211 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Trybot-Ready: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28eve: Specify a unique ID for PS2 devicesLucas Chen
Windows certification tests will fail if the PS2 devices are using Plug and Play ID (PNP0303). For all Chromebooks we should use GOOG000A. BRANCH=eve BUG=b:110066056 TEST=AltOS certification test verify. Change-Id: I479471fdb3102e3b492612a4e6ad07612273083a Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1098874 Reviewed-by: Matt Delco <delco@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Trybot-Ready: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28334 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28fsp/fsp2_0/coffeelake: Update CFL FSP headersLijian Zhao
Coffeelake FSP headers had been updated to version 7.0.3D.60. Original file location from https://github.com/IntelFsp/FSP/tree/master/ CoffeeLakeFspBinPkg/Include . BUG=N/A TEST=Build and flash, able to boot up into OS on whiskeylake rvp platform. Change-Id: I656da83e9042642576b785643e423ba47da8dd73 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28286 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28google/kukui: Init SPI bus for ECTristan Shieh
Set EC SPI bus config and init SPI bus according to the config. BUG=b:80501386 BRANCH=none TEST=EC is not working yet. This makes depthcharge go forward a little. Change-Id: Id9209b6429417430cfcf7f5a5a1659e7e4bc7866 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28251 Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28google/kukui: Set up GPIOs for ChromeOSTristan Shieh
Set up EC interrupt GPIO to boot depthcharge. Without this patch, depthcharge will fail to detect EC interrupt GPIO. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and see in logs, that depthcharge detects EC interrupt GPIO. Change-Id: I0ec2c70c189a059219954e0384aaf98995285728 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-28siemens/mc_apl1: Extend circuit life by clock gating and power gatingMario Scheithauer
The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 - Disable I/O UART driver Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-28vendorcode/amd/pi/00670F00: Remove IDS headersRichard Spiegel
Only Ids.h had definitions still in use, and they were removed or moved to AGESA.h. Now Ids.h, IdsPerf.h and IdsLib.h can be safely removed. BUG=b:112885948 TEST=Build grunt Change-Id: I031ae8eb5f34fee801365fc89ea11a881211e726 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28299 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28vendorcode/amd/pi/00670F00: Transfer TP_Perf_STRUCT to AGESA.hRichard Spiegel
Google is creating code to measure AGESA performance, which needs structure TP_Perf_STRUCT and associated definitions. In preparation to remove IDS headers, move the necessary definitions to AGESA.h. BUG=b:112885948 TEST=Build grunt Change-Id: I941a67a8889a9dbf35c9fd511c7f670623204134 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHzKevin Chiu
Bayhub eMMC controller default runs SD base 50MHz at the first power on. After boot into OS, mmc kernel driver will config controller to HS200/208MHz and send MMC CMD21 (tuning block). But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear after system warm reset. So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge. It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) to fail to load kernel and trap in 0x5B error (No bootable kernel found on disk). BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-28src/drivers/pc80/pc: Remove unneeded includeElyes HAOUAS
Change-Id: Ic238181d5c26ab8cf549137824a7c5e6c6d80ab1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-27drivers/intel/wifi: Make WIFI_SAR_CBFS user visibleFurquan Shaikh
This change makes WIFI_SAR_CBFS user selectable option so that it can be enabled/disabled from menuconfig along with the SAR filepath. BUG=b:112425861 Change-Id: Idf6feaefe68e7ebf6786c2c36e92a054fba4483c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-27vendorcode/amd/pi/00670F00: Transfer IDS_CALLOUT to AGESA.hRichard Spiegel
Currently, IDS_CALLOUT macros are only used in stoneyridge callout. In preparation to remove IDS headers, move the definitions to AGESA.h. BUG=b:112885948 TEST=Build grunt Change-Id: Ia9717eb68fed2e568eaf169157c2837bb8232b7e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-27mb/google/poppy/variants/atlas: Update DPTF parametersTodd Broch
Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:113101335 BRANCH=atlas TEST=manual performance/power testing on nocturne. No longer see messages like below in syslog, 'CPU0: Package temperature above threshold' Change-Id: I2dc9d157b54500bae29e123978bb8ad6e05ef619 Reviewed-on: https://review.coreboot.org/28325 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27mb/google/poppy/variants/nocturne: Update DPTF parametersTodd Broch
Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:67459049 BRANCH=nocturne TEST=manual performance/power testing on nocturne. No longer see messages like below in syslog, 'CPU3: Package temperature above threshold' Change-Id: Ic20c718fd3a496db7c7192feec4f230d924cc458 Reviewed-on: https://review.coreboot.org/28324 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27vendorcode/amd/pi/00670F00/Include/Ids.h: Remove IDS_ERROR_TRAPRichard Spiegel
The macro IDS_ERROR_TRAP is only defined, and never used. Also, IDSOPT_ERROR_TRAP_ENABLED is defined FALSE, so the macro would translate to nothing. Remove the macro and IDSOPT_ERROR_TRAP_ENABLED. BUG=b:112885948 TEST=Build grunt Change-Id: I2c3ca4b0a4a1f96f245ba2f4902fd0051dda77ef Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-27vendorcode/amd/pi/00670F00/Lib/AmdLib.c: Remove IdsErrorStopRichard Spiegel
Function IdsErrorStop() is only used within AmdLib.c function LibAmdMsrRead(), which in turn is only used once within PspBaseLib.c and three times inside AmdLib.c, all with well defined MSR addresses. IdsErrorStop() is used as a trap if MSR address is 0 or 0xFFFFFFFF, which clearly it's not. Therefore it can be safely removed from AmdLib.c. BUG=b:112885948 TEST=Build grunt Change-Id: I47ffcbd4fbae28b6d711a340f0ac3f3b007e8e4f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-08-27mb/google/octopus/variants/baseboard: Update DPTF parametersSumeet Pawnikar
Update TSR1 trip point from 48C to 50C. Also, change power limit2 minimum value from 8W to 10W. These are the values as per recent thermal tuning. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I33a9d2dc3e0e5566d95b1f1e46d3922dc8965b2b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28187 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27lib/nhlt: Use common function to set NHLT versionMarc Jones
Set NHLT version with get_acpi_revision(NHLT) to keep all table versions in sync. Change-Id: I4ea9d511142e4ea68e651e58c2c985e739c032d9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28279 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27mb/google/kahlee: Fix I2C bus 0 timing for GruntAkshu Agrawal
This commit fixes the values and thus fixes the issue of audio device not getting detected on random reboots. Change-Id: I34a4f62815d192005c3324d4f71b0aba377fe738 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/28280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-08-27mb/supermicro/h8qme_fam10: Use common pnp_{enter,exit} functionsElyes HAOUAS
Change-Id: Ie3ee4acfd272991133f02a56df6e23aa6071d3e9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-27mb/kontron/986lcd-m: Use common pnp_{enter,exit} functionsElyes HAOUAS
Some unneeded includes are also removed. Change-Id: Icd518c46d8503d11d24466c30840d7e514e9a05d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-27intel: Use common HPET table revision functionMarc Jones
Use get_acpi_table_revision(HPET) to keep all table versions in sync. Change-Id: Idb5e8ccd49ec27f87a290f33c62df3c177645669 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27x86/acpi: Update MADT table versionMarc Jones
Update the MADT table version to sync with the FADT table version. All current coreboot FADT tables are set to ACPI_FADT_REV_ACPI_3_0 and the MADT should be set to match. This error was found by running FWTS: FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead. BUG=b:112476331 TEST-Run FWTS Change-Id: If5ef53794ff80dd21f13c247d17c2a0e9f9068f2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27update all FADT version 3.0 to use the get tables functionMarc Jones
Most FADT report using ACPIv3 FADT table. Using the get revision function keeps the table versions in sync. Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27x86/acpi: Add ACPI table revision functionMarc Jones
Use a single function to set ACPI table versions. This allows us to keep revisions synced to the correct levels for coreboot. This is a partial fix for the bug: FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0 instead. BUG=b:112476331 TEST-Run FWTS Change-Id: Ie9a486380e72b1754677c3cdf8190e3ceff9412b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28276 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27vendorcode/amd/cimx/sb*: Rename RSDP headerMarc Jones
Rename RSDP to RSDP_HEADER to match other AMD vendorcode and to not pollute the namespace. We will use RSDP in a future patch. Change-Id: I3b66135ae1732b86b5ebfcdc01a850a0d9d3eb50 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27siemens/mc_apl1: Disable PCI clock outputs on XIO bridgeMario Scheithauer
This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridge. Change-Id: I0b9cf51a713f4ab46e71d250397486d136c26177 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-27mb/google/octopus: add Digitizer and Synaptics Touchpad for bobbaPan Sheng-Liang
add device "WCOM Digitizer" and "Synaptics Touchpad" for bobba BUG=none BRANCH=master TEST=emerge-octopus coreboot Change-Id: Ie0bf8ebab6d9cb9c8fe42a500efaa3d11ae359db Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-25mb/intel/coffeelake_rvp: Remove superfluous header fileArthur Heymans
TEST: same sha256sum with BUILD_TIMELESS=1. Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-08-25Revert "drivers/spi/spi_flash: don't allocate unbounded stack memory"Patrick Georgi
This reverts commit c5ee35ff861fe4447fd80119f645fba7bfd3a184. Reason for revert: breaks boards, uncertain if it _really_ works. Change-Id: I9ba2ba877b9a391306f89295c0c1d0e2d011c5ea Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28338 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jean Lucas <jean@4ray.co> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-24siemens/mc_apl1: Select DDR50 mode for eMMCMario Scheithauer
To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed to DDR50 mode. Change-Id: I40658b44a99e6600ed00950a1a177961f0055e7a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-24soc/intel/apollolake: Make eMMC max speed configurableMario Scheithauer
The eMMC maximum speed is set to HS400 mode per default. To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed. Change-Id: I6fa5eb56a0593e24269ef143645c506232879889 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28282 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-24soc/cn81xx: Add vboot supportPhilipp Deppenwiese
* Add VERSTAGE and VBOOT_WORK to memlayout. * Add hard and soft reset. * Add missing makefile and kconfig includes. Change-Id: I0d7e3c220f5c2c50c4ffe59ac929cb865bfac0ad Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/28022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-24soc/cavium/cn81xx: Don't directly manipulate devicetree dataPatrick Rudolph
As preparation to constify devicetree data, do it the right way. Change-Id: I5081de020bb73c56aa8bdf7bb17fe6b2913d0ffe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-12 05:39:45 +0000