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2020-05-01soc/intel/common: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01cpu/x86/mtrr/earlymtrr: Validate MTRR argumentsRaul E Rangel
The AMD64 Architecture Programmer's Manual, Volume 2: Systems Programming says the following about variable MTRRs: Variable Range Size and Alignment. The size and alignment of variable memory-ranges (MTRRs) and I/O ranges (IORRs) are restricted as follows: * The boundary on which a variable range is aligned must be equal to the range size. For example, a memory range of 16 Mbytes must be aligned on a 16-Mbyte boundary (i.e., naturally aligned). * The range size must be a power of 2 (2^n , 52 > n > 11), with a minimum allowable size of 4 Kbytes. For example, 4 Mbytes and 8 Mbytes are allowable memory range sizes, but 6 Mbytes is not allowable. Print out errors if these conditions are violated. I didn't assert since `set_var_mtrr` can be used in boot block before the serial console is enabled. BUG=b:147042464 TEST=Boot trembyle and see MTRR errors: MTRR Error: base 0xcc800000 must be aligned to size 0x1000000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8b8c734c7599bd89cf9f212ed43c2dd5b2c8ba7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40762 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01sb/intel/i82801gx: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I11b8743234cb1292db8c930edecf8fb5c47d63fd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-01mb/google/dedede: Fix crossystem wpsw_cur errorSubrata Banik
Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community zero. TEST=Build coreboot, flash, boot to and log into kernel, execute "wp enable" in console, execute "crossystem" at kernel prompt and verify that "wpsw_cur" shows as being "1", Execute "wp disable" in console, execute "crossystem" at kernel prompt and verify "wpsw_cur" is 0. Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/amd/picasso: initialize i2c controllers in SoC flowAaron Durbin
BUG=b:153642124 TEST=Saw I2C communication Change-Id: I31f8b97d1ff7b687d7e078d5b594d1ad73c815e7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145457 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01soc/amd/picasso/bootblock: Remove duplicate sb_reset_i2c_slavesRaul E Rangel
sb_reset_i2c_slaves is called in fch_pre_init. BUG=b:153675916 TEST=Builds on trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I157e473984257d633ceb3ef9df45c71a31c5c00b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-01soc/amd/picasso/bootblock/bootblock: Remove duplicate i2c initRaul E Rangel
fch_early_init already calls i2c_soc_early_init(). BUG=b:153675916 TEST=Boot trembyle and only see 1 i2c initialization message Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I689616fb617904df1781be3abe9d1dc580608173 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-01soc/amd/picasso: Allow mainboard to provide pci ddi descriptorsAaron Durbin
Mainboards must provide their DDI descriptors. BUG=b:153502861 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146443 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146438 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145453 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145454 Change-Id: Ib3f115711e74d0e6eb5b063b3dccb36b265779af Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01ec/google/chromeec: Fix incorrect diag messageVictor Ding
The expected error code observed in clear_pending_events() should be EC_RES_UNAVAILABLE(9), not EC_RES_INVALID_COMMAND(1). BUG=b:153896701 Change-Id: I609490ceef675267760d34b5e9775211da93347c Signed-off-by: Victor Ding <victording@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/google/deltaur: Add BT reset gpioEric Lai
Harrison Peak (HrP) 9560 module needs a reset pin for BT power sequence. BUG=b:155248677 TEST=Boot into OS and check BT is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I55ed1b095ba53c414c44088f4a6e7720b970e2f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-01soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better ↵Subrata Banik
understanding BIT 1 -> DEBUG_INTERFACE_UART_8250IO BIT 4 -> DEBUG_INTERFACE_LPSS_SERIAL_IO Change-Id: I566b9dc82b2289af42e58705ebeee51179886f1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-01mb/google/deltaur: Update USB/WWAN configIvy Jian
Update USB3 ports configuration as schematics design. BUG=b:155026295 TEST=Boot into OS and check WWAN device detected by lsusb. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40818 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01acpi_device: Make integer array input variable constDuncan Laurie
An array of 64bit integers is passed to acpi_dp_add_integer_array() but it is not const so can't take a const array without a compiler error. The function does not modify the array so it can be made const without breaking anything and allowing a const array to be passed in the future. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I98ecdaef5ddfa2026390e2812f5ea841ee51f073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40882 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01arch/x86/acpi: Add define for generic container HIDDuncan Laurie
The generic container HID is defined in ACPI specification as PNP0A05. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I3632e77533a47f22b92259b469b03e63f51687e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01arch/x86/acpi_device: Allow empty child referencesDuncan Laurie
Currently if a child table is created and added to a property list without adding any properties to that child it will generate an empty package. For example: struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); struct acpi_dp *prop = acpi_dp_new_table("PROP"); acpi_dp_add_child(dsd, "dsd-prop", prop); acpi_dp_write(dsd); Results in an empty PROP package: Name (_DSD, Package (2) { ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b") Package (1) { Package (2) { "dsd-prop", "PROP" } } } Name (PROP, Package (0) { } Empty packages don't seem to be explicitly forbidden, but they don't serve a purpose with device properties. Instead, if packages without any properties or children are skipped then this empty package is not written and the added child property can refer to another property that is already defined. This allows creating property references to existing tables, which can save duplication and namespace collision issues with nested properties. BUG=b:146482091 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I9fee2ceb8a4496b90c7210533eee8c2b186cdfff Reviewed-on: https://review.coreboot.org/c/coreboot/+/40880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01soc/intel/jasperlake: fix args of dimm_info_fill() for dram_part_numMarco Chen
BUG=b:152019429 BRANCH=None TEST=1. provision dram_part_num field of CBI 2. modify mainboard - dedede to report DRAM part number from CBI 3. check DRAM part number is correct in SMBIOS for memory device Change-Id: I509d06a81bd005c5afe6e74a2da2ca408dee7b29 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01mainboard/google/kahlee: move specific setting to variantKevin Chiu
Separate specific setting to variant from baseboard. baseboard/romstage.c in current release is only utilized by careena, we could remove it from the rest of variant build. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I658526e44aadc47bdc5538f506a1bfe2e5f20f63 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-01soc/intel/cannonlake/bootblock: Fix FSP CARPatrick Rudolph
Fix FSP CAR on platforms that have ROM_SIZE of 32MiB. CodeRegionSize must be smaller than or equal to 16MiB to not overlap with LAPIC or the CAR area at 0xfef00000. Tested on Intel CFL, the new code allows to boot using FSP-T. Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01mb/google/octopus/variants/bobba: Disable XHCI LFPS power managementSheng-Liang Pan
LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:146768983 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-05-01mb/google/volteer/malefor: Enable touch screenWilliam Wei
Enable Goodix touch screen and ensure it works properly. BUG=b:154191288 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the Goodix touch screen function. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: I236ac56dd0a1817092151bae93e699115ba88e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40598 Reviewed-by: Alex Levin <levinale@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01vc/eltan/security/verified_boot/vboot_check.c: Increase wb_buffer sizeFrans Hendriks
Running commit aee0baf0690681fae85d24e6887d6cbb9209de83 on Facebook fbg1701 results in an error: VB2:vb2_rsa_verify_digest() ERROR - vboot2 work buffer too small! ERROR: HASH table verification failed! The actual vboot structures require more space. Workbuffer size needs to be increased. We didn't determine the commit causing the issue because this change fixes the issue. BUG=N/A TEST=Build and boot Facebook fbg1701 Change-Id: I5caebc643eb493f4285c2f2fc164ff3a5d35e24e Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-01soc/amd/common/block/graphics/graphics: Add missing const to fill_ssdtRaul E Rangel
BUG=none TEST=Made sure trembyle builds Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9df70fd5c41a9a68edc7be3c2e920c4dc94d5af9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40871 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/purism/librem_skl: Use ACPI backlight controlsBenjamin Doron
Enables ACPI backlight controls. Change-Id: Iccf50f427b7555ee1a3ef9cc11a89d532789ac54 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-05-01soc/amd/picasso: Enable cache in bootblockFelix Held
Unlike prior AMD devices, picasso cannot rely on the cache-as-RAM setup code to properly enable MTRRs. Add that capability to the bootblock_c_entry() function. In addition, enable an MTRR to cache (WP) the flash boot device and another for WB of the non-XIP bootblock running in DRAM. BUG=b:147042464 TEST=Boot trembyle to payload and make sure bootblock isn't abnormally slow. Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38691 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01security/vboot: Convert reboot-related errors to vboot2-styleYu-Ping Wu
Error codes are renamed as follows: VBERROR_SHUTDOWN_REQUESTED --> VB2_REQUEST_SHUTDOWN VBERROR_REBOOT_REQUIRED --> VB2_REQUEST_REBOOT VBERROR_EC_REBOOT_TO_SWITCH_RW --> VB2_REQUEST_REBOOT_EC_SWITCH_RW VBERROR_EC_REBOOT_TO_RO_REQUIRED --> VB2_REQUEST_REBOOT_EC_TO_RO BRANCH=none BUG=b:124141368, chromium:988410 TEST=emerge-nami coreboot Cq-Depend: chromium:2143030 Change-Id: Id82cf85f49dfb63a9c3d41aacd3969786bffcac7 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40749 Reviewed-by: Joel Kitching <kitching@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetreeMeera Ravindranath
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-01mb/google/hatch/vr/puff: Add psys_pmax calculationTim Chen
This patch adds psys_pmax calculation. There are two types of power sources. One is barrel jack and the other is USB TYPE-C. The voltage level is fixed for a barrel jack while TYPE-C may vary depending on power ratings. We need to get voltage information from EC and calculate correct psys_pmax value. The psys_pmax needs to be set before FSP-S since FSP-S will handle the setting passing to pcode, so move the routine ahead to variant_ramstage_init. BUG=b:151972149 TEST=emerge-puff coreboot chromeos-bootimage check firmware log and ensure psys_pmax is passed to FSP check the data from dump_intel_rapl_consumption in the OS and ensure the power data is close to an external power meter. Change-Id: Iff767d4b44a01e766258345545438a54a16d1af5 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-01sb/common/smihandler: Fix 16-bit read/write to PCI_COMMAND registerElyes HAOUAS
Change-Id: Ib403f5a231f86bdc60b956e72a4ae631aa6a3899 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-01mb/google/dedede: Enable USB port for camera supportIan Feng
Support USB Chicony user facing camera. BUG=b:155109736 BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using user facing camera. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I7580a58086977e239dca49c1def4f03583831662 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01sb/intel/i82801jx: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: If39cdfb21fec307141593f2482e014e146d4f1f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01sb/intel/i82801ix: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I5a07a00e1183ef834d97c11268935617cfe17faa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01sb/intel/lynxpoint: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I81b740e0cfcf0e1bf096427b45ffba06d357fee6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01sb/intel/ibexpeak: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I212ef304a03d068232f50a71c318e2b468336339 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-01soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-05-01mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device treeMeera Ravindranath
This CL selects the PcieRpClkReqDetect for the required root ports which is needed to allow proper clksrc gpio configuration. Also, sets the unused PcieClkSrcUsage to 0xFF. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-01soc/intel/jasperlake: Fill PcieRpClkReqDetect from devicetreeMeera Ravindranath
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Iad0b394fea019223a5b98fff0cb4a2bd1d2a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-05-01src: Remove not used 'include <smbios.h>'Elyes HAOUAS
Change-Id: I12345a5b6c9ce94ca9f8b555154b2278a8ff97bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01include/device/device.h: Include <smbios.h>Elyes HAOUAS
smbios_slot_{type,data_width,length,designation} used for smbios_type_9 needs "smbios.h" Also use already defined 'smbios_type11' in "smbios.h". This will also include <smbios.h> in "static.c" file, this we can remove indirect includes of <smbios.h> in "chip.h" Change-Id: Id412a504da2fd75648636febd150356569e07935 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40310 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/google/dedede: Remove pad termination for RAM_STRAP_4Karthikeyan Ramasubramanian
The stuffed resistor straps are weaker compared to the internal pull-up. This can cause the GPIO to read '1' always. Remove the internal pull-up. Also read the GPIO only on the boards where the board version is populated. BUG=b:154301008 TEST=Build and boot the mainboard. Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01Helios: Update DPTF settings for smooth fan speed controlSumeet R Pawnikar
Update DPTF settings for smooth fan speed control. BRANCH=firmware-hatch-12672.B BUG=b:154074920 TEST=Built and test on Helios system Change-Id: I3f4d9fd9e17541dd5fb7982a8b43a039c41cba87 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-01mb/google/dedede: Enable camera support for waddledooPandya, Varshit B
BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: I51dcf96a82535fc1e0b9247fd52af919885575e5 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01mb/google/dedede: Add ACPI support for cameraPandya, Varshit B
1. Add support as per the schematics 2. Add 2 Ports and 2 Endpoints 3. Add support for OTVI8856 and OTVI5676 4. Add ON and OFF logic as Power Rails are same for both sensor BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: Ic8687bce4896d9fc17b2190b8d11618af3515cc1 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01sb/intel/common/{madt,rcba_pirq}.c: Convert to 96 characters line lengthElyes HAOUAS
Change-Id: I62a213013d9008d8a4a22b5908b7fc7d1b663c4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01mb/google/dedede: add new variant for wheeliePeichao Wang
Add initial support for wheelie variant board. BUG=b:154664137 BRANCH=None TEST=build Change-Id: Id638e987f45c247dae824f221a38ccf32626572f Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01mb/google/nightfury: Tune the usb2_port[0] strengthSeunghwan Kim
Update usb2 port strength parameter for usb2_port[0] to improve SI. BUG=b:154668734 BRANCH=firmware-hatch-12672.B TEST=Built and checked SI margin of USB2 ports Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-01soc/intel/jasperlake: Add support to generate ACPI GPIO operationsKarthikeyan Ramasubramanian
Add support to generate ACPI operations to get/set/clear RX/TX GPIOs. BUG=b:152936541 TEST=Build and boot the mainboard. Ensure that there are no errors in the coreboot logs regarding unsupported ACPI GPIO operations. Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-01mb/ocp/tiogapass: Update UPD IIO bifurcation at run-timeJohnny Lin
Update UPD IIO bifurcation at run-time according to different Riser cards. For detail please reference Facebook Server Intel Motherboard v4.0, Sec. 10.1.2 Riser card types. With the engineering build FSP, it can only configure IIO for one socket so my local test needs to remove all socket1 elements from tp_iio_bifur_table. This change relies on [1] and need to add GPP_C15 and GPP_C16 to early_gpio_table for gpio configuration in bootblock. [1] https://review.coreboot.org/c/coreboot/+/39427/ Tested=OCP Tioga Pass can see socket0 IIO being updated with an engineering build FSP. Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-30mb/cedarisland_crb: rework GPIOs configuration using macrosMaxim Polyakov
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40736 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 21:43:21 +0000