summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2020-02-12soc/intel/{skl, common}: Move ME Firmware SKU Types to common codeSridhar Siricilla
1. Move ME firmware SKU types into common code. 2. Define ME_HFS3_FW_SKU_CUSTOM SKU. TEST=Verified on hatch & soraka. Change-Id: Iaa4cf8d5b41c1008da1e7aa63b5a6960bb9a727b Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-11vendorcode/intel: Remove Ice Lake FSP BindingsJohanna Schander
By updating the FSP submodule we now got all FSP headers from within that repo. This commit changes the default paths to use these and fixes some include paths to allow the usage of vendorcode/intel/edk2/UDK2017 together with the official Intel distribution. We are also adding back the CHANNEL_PRESENT enum, that is missing in the official headers. This was tested on the Razer Blade Stealth (late 2019). Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37579 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11mb/google/volteer: use new Tiger Lake memory configNick Vaccaro
Some of the common memory code that was being performed in mainboard has moved into the soc to reduce redundant code. This change adapts volteer to use Tiger Lake's new common code. BUG=b:145642089, b:145238504, b:145564831 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, boot to kernel, "cat /proc/meminfo" and verify it reports "MemTotal: 8038196 kB". Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-11arch/x86/acpi: Change message in acpi_write_dbg2_pci_uart to BIOS_DEBUGWim Vervoorn
When acpi_write_dbg2_pci_uart is called and no pci uart is available the function prints "Device not found" as an error. This is not correct. Change the error level to BIOS_DEBUG so coreboot reports the device is not available but doesn't flag this as an error. BUG=N/A TEST=build Change-Id: I14567bcfcf5a6ff427e418d15bc2675ae7a28f53 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-11mb/facebook/monolith: Enable the 2nd EC UART at 0x2f8Wim Vervoorn
BUG=N/A TEST=tested on facebook monolith Change-Id: I36e652e66c66eeb770a5a5d987bb57c7eaa11382 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38749 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11soc/intel/common/block/lpc: Add lpc_get_fixed_io_decodeWim Vervoorn
Add function to return the fixed io decode ranges contained in register 0x80 of the LPC interface. BUG=N/A TEST=build Change-Id: Ie46d7c9d7a399a8489c030d906f75ba61db19cc4 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38745 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11sb/intel/lynxpoint: Don't use_ADR and _HIDElyes HAOUAS
To be compliant with ACPI specification, device object requires either a _HID or _ADR, but not both. Change-Id: I45cf2b8d455aa4d288de1ac53cf9ae801f758a9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38351 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11mb/lenovo/x201/acpi_tables: Default to lid openPeter Lemenkov
It's really hard to power up this laptop with the lid closed so let's make it open by default, as done on many other laptops. Change-Id: I5bb2f716865c2bb569a4735f135842526043713c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-11Kconfig: Add CONFIG_PCI dependency for CONFIG_MINIMAL_PCI_SCANNINGSubrata Banik
Make sure MINIMAL_PCI_SCANNING has right dependency over PCI kconfig symbol. Change-Id: I30b18345976e5d21ccedf8906985ff71e7d2815c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38801 Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-11Kconfig: Guard CONFIGURABLE_RAMSTAGESubrata Banik
This patch guards CONFIGURABLE_RAMSTAGE symbol (which is default enable for all x86 systems) with another Kconfig that can be selected by platform that actually planning to use it. TEST=CONFIG_CONFIGURABLE_RAMSTAGE is not enabled by default. Change-Id: I2113445d507294df59fbc7fb1373793b47c6c31c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-10vboot: correct workbuf size when VBOOT_STARTS_IN_ROMSTAGEJoel Kitching
Part of the design of vboot persistent context is that the workbuf gets placed in CBMEM and stays there for depthcharge to use in kernel verification. As such, the space allocated in CBMEM needs to be at least VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE. In the VBOOT_STARTS_IN_ROMSTAGE case, prior to this CL, vboot_get_context() would get invoked for the first time after CBMEM comes up, and it would only allocate VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE. Initialize the workbuf directly in vboot_setup_cbmem() instead with the correct VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE. BUG=b:124141368, chromium:994060 TEST=make clean && make test-abuild TEST=boot on GOOGLE_EVE with VBOOT_STARTS_IN_ROMSTAGE set BRANCH=none Change-Id: Ie09c39f960b3f14f3a64c648eee6ca3f23214d9a Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38778 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09intel/stm: Add platform opt-in KconfigNico Huber
Selecting STM on an arbitrary platform would likely result in a brick, so let's hide the prompt by default. Change-Id: I50f2106ac05c3efb7f92fccb1e6edfbf961b68b8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: <cedarhouse1@comcast.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-09cpu/intel: Drop unused fileElyes HAOUAS
Change-Id: I1b41ddc5e99838f0585089974e995f3de7be1791 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37161 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/lenovo/t400: Configure panel-power sequencingNico Huber
If the panel-power sequencer is not configured, libgfxinit falls back to very conservative defaults (210ms before EDID is probed). This results in a boot penalty of >100ms (depending on how long it takes to probe other ports). Values are taken from the VBTs already checked in. Untested. Change-Id: I189776ce8684b4c3c01acd6d2fc433ca33a050d5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09mb/lenovo/t400: Correct display port list for R500 variantNico Huber
The second digital display connector is unused, but strapped as if it were used. Versions with a discrete GPU seem to use PM45 (i.e. no IGD), so we can ignore these. Based on schematics only, not tested. Change-Id: Ibb47fdeef2adb9c574b7f3ec8e2b1d61d28f21da Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-02-09mb/lenovo/t400: Correct display port list for [TW]500 variantsNico Huber
T500 and W500 (Coronado-5) use both digital display connectors. Both with the DP AUX channel implemented, so add DP2 to the list. Versions with a discrete GPU don't use external, digital connectors but seem to have the straps correctly configured. So we hopefully won't have to handle these specifically. Based on schematics only, not tested. Change-Id: I31e1415eff2d5d00c4a231906e3d861d2a59b629 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09mb/lenovo/t400: Correct display port list for [RT]400 variantsNico Huber
The first digital display connector is unused, but strapped as if it were on later revisions. The DP AUX channel of the second connector is implemented, though, so add DP2 to the list. Versions with a discrete GPU don't use external, digital connectors but seem to have the straps correctly configured. So we hopefully won't have to handle these specifically. Based on schematics only, not tested. Change-Id: I7d3e8b3a2123ddc407bb5a0cce86a3634b575f4a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09mb/lenovo/t400: Move `gma-mainboard.ads` to variantsNico Huber
Some board revisions have the straps for display port detection wrongly configured. So with a single list covering all variants' possible outputs, we make libgfxinit probe unimplemented ports which may stall the GMBUS controller and delay the boot for some hundred milliseconds. This just copies the list to the various variants with different display ports, so we can test the actual changes individually. Change-Id: I48cdea1d71d9553b6bdbce432eae986996329239 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-02-09sb/amd/{agesa,pi}/hudson/Kconfig: Change default SATA mode to AHCIPiotr Kleinschmidt
The attempt to install pfSense on hard disk on PC Engines apu2 board ended up in a SATA driver error. The problem is related only to BSD and didn't occur with Linux kernel. Changing SATA mode from IDE to AHCI solved the problem. Additionally AHCI is faster than IDE so it speeds up the installation. Since AHCI works perfectly with SeaBIOS, Linux and BSD, make it a default choice for all Hudson southbridges. Change-Id: I1b0322392712d797dd5a8931150c8d0ff1b60940 Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35891 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/octopus/variants/lick: Increase TCC offset to 15Hash.Hung
Change tcc offset from 0 to 15 degree celsius for lick. BUG=b:147198431 BRANCH=octopus TEST=Build, and verify test result by thermal team. Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com> Change-Id: Ife6b02321145837e05c82f979998466b83317f86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38506 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/dedede: Add initial configuration for serial IO portsKarthikeyan Ramasubramanian
Add initial configuration for GSPI, I2C and UART ports and leave them in disabled state. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-02-09mb/google/dedede: Turn on ESPI device in devicetreeKarthikeyan Ramasubramanian
BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38739 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/dedede: Add GPE configurationKarthikeyan Ramasubramanian
Configure the GPIO groups to be routed to the GPE0 block. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/google/dedede: Add Compute & PCH Global device IDsKarthikeyan Ramasubramanian
Add compute and PCH Global device IDs with the concerned devices turned off. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09soc/intel/tigerlake: add memory configuration supportNick Vaccaro
Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward. BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB. Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/google/volteer: add volteer mainboard initial supportNick Vaccaro
Created a new Google baseboard named volteer from scratch. BUG=b:142961277 BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/google/drallion: Add new SPD files for drallionIan Feng
Add new SPD files for drallion: 1. Hynix H5AN8G6NDJR-XNC 2. Samung K4AAG165WA-BCWE 3. Samung K4A8G165WC-BCWE BUG=b:148642500 TEST=Compile successfully and check SPD info in cbmem log. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0e9b444f6f1e0c7e1da197fbd2e70e686568ab47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38731 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/drallion: Tuning WWAN power sequenceEric Lai
Change GPP_C10 from pltrst to deep to meet the warmboot power sequence. BUG=b:146935222 TEST=measure WWAN power sequence is meet spec Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia1513ed38fbc1c99a10a5fa531a78cc92a3ebfc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-09mb/google/dedede: Log mainboard events to elogKarthikeyan Ramasubramanian
BUG=b:148410914 TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7dffa5c021787dca75786ead42164bd29ba56828 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09mb/lenovo/t440p: Enable dGPU on Lenovo T440PChris Morgan
Enable the dGPU on the Lenovo T440P. It uses the same code (roughly) of the T430S. By default, it is set to be disabled however it can be enabled via the nvram option enable_dual_graphics. Removed hybrid graphics options too as they are not valid for the T440p. Tested on a T440P with Ubuntu 18.04.4 with Kernel 5.3.0-29 (successful). Tested on same machine with Windows 10 1909 (machine check exception bluescreen). Change-Id: Idf8c2c0d1ae34bda8736448d3e350396e3cf7a93 Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-09mb/google/octopus: Override VBT selection for BloogTony Huang
Since most of Bloog series SKUs need to disable DRRS support. If Bloog and Unprovisioned SKUs then return vbt.bin to enable DRRS support, return vbt_blooguard.bin for other SKUs to disable DRRS support. Bipship follow blooguard to disable DRRS support. BUG=b:148892903, b:147021309 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage check i915_drrs_status shows DRRS supported NO when SKU ID is bipship. Change-Id: I61f12d4ddea17a05255751fde2a5ce822dd2e782 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-02-09soc/intel/{cnl,icl,skl,tgl,common}: Make changes to ↵Sridhar Siricilla
send_heci_reset_req_message() Below changes have been implemented in send_heci_reset_req_message(): 1. Modify return values to align with other functions in the same file. 2. Add additional logging. 3. Replace macro definitions of reset types with ENUM. 4. Make changes to caller functions to sync with new return values. 5. Rename send_heci_reset_req_message() to cse_request_global_reset(). Test=Verified on hatch board. Change-Id: I979b169a5bb3a5d4028ef030bcef2b8eeffe86e3 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37584 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09soc/intel/common: Add description to HMRFPO statusSridhar Siricilla
Below changes are implemented: 1. Fix typos. 2. Rename 'padding' field of hmrfpo_get_status_resp struct to 'reserved' to match with ME BWG Guide. 3. Add documentation for HMRFPO Status. TEST=Build and boot hatch Change-Id: I4db9bdf7386c48e17ed0373cf334ccff358d1951 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09soc/intel/common: Rename functions for consistent namingSridhar Siricilla
Below changes are done: 1. Rename below functions to have consistent naming: set_host_ready() -> cse_set_host_ready() wait_cse_sec_override_mode() -> cse_wait_sec_override_mode() send_hmrfpo_enable_msg() -> cse_hmrfpo_enable() send_hmrfpo_get_status_msg() -> cse_hmrfpo_get_status() 2. Additional debug messages are added in cse_wait_sec_override_mode(). TEST=Build and Boot hatch board. Change-Id: Icfcf1631cc37faacdea9ad84be55f5710104bad5 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoCSridhar Siricilla
Below changes are implemented: 1. Move HFSTS1 register definition to SoC since HFSTS1 register definition is specific to a SoC. Moving structure back to SoC specific to avoid unnecessay SoC specific macros in the common code. 2. Define a set of APIs in common code since CSE operation modes and working states are same across SoCs. cse_is_hfs1_com_normal(void) cse_is_hfs1_com_secover_mei_msg(void) cse_is_hfs1_com_soft_temp_disable(void) cse_is_hfs1_cws_normal(void) 3. Modify existing code to use callbacks to get data of me_hfs1 structure. TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09cpu/x86/smm: Add overflow checkNico Huber
Rather bail out than run into undefined behavior. Change-Id: Ife26a0abed0ce6bcafe1e7cd8f499618631c4df4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: <cedarhouse1@comcast.net>
2020-02-09superio/nuvoton/nct5539d/acpi: fix # comment in superio.aslPavel Sayekat
Change-Id: Ic2ba1f9b744014f97d318671bf86468f4d6c6469 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-08Add configurable ramstage support for minimal PCI scanningRonald G. Minnich
This CL has changes that allow us to enable a configurable ramstage, and one change that allows us to minimize PCI scanning. Minimal scanning is a frequently requested feature. To enable it, we add two new variables to src/Kconfig CONFIGURABLE_RAMSTAGE is the overall variable controlling other options for minimizing the ramstage. MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal PCI scanning. Some devices must be scanned in all cases, such as 0:0.0. To indicate which devices we must scan, we add a new mandatory keyword to sconfig It is used in place of on, off, or hidden, and indicates a device is enabled and mandatory. Mandatory devices are always scanned. When MINIMAL_PCI_SCANNING is enabled, ONLY mandatory devices are scanned. We further add support in src/device/pci_device.c to manage both MINIMAL_PCI_SCANNING and mandatory devices. Finally, to show how this works in practice, we add mandatory keywords to 3 devices on the qemu-q35. TEST= 1. This is tested and working on the qemu-q35 target. 2. On CML-Hatch Before CL: Total Boot time: ~685ms After CL: Total Boot time: ~615ms Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2020-02-07sc7180: clock: Fix QUP DFSR configuration for perf levelsTaniya Das
Update the QUP DFSR cmd to clear the SW control and also update the perf registers when M is set. While at it also update the d_2 values. Tested: validated DFSR clock configuration and M/N/D values. Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-07security/vboot: relocate vb2ex_abort and vb2ex_printfJoel Kitching
Enabling an assertion in vb2_member_of() results in coreboot linking vb2ex_abort() and vb2ex_printf() in ramstage. Move these two functions from vboot_logic.c to vboot_lib.c, which is should be enabled in all stages if CONFIG_VBOOT_LIB is enabled. Note that CONFIG_VBOOT_LIB is implied by CONFIG_VBOOT. Relevant vboot_reference commit: CL:2037263. BUG=b:124141368, chromium:1005700 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ica0103c5684b3d50ba7dc1b4c39559cb192efa81 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-07mainboard/hatch: Fix puff DP output on cold bootsEdward O'Callaghan
Wait for HPD DP unless HDMI is plugged. Some Type-C monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Similar to that of b:72387533 however our DP&HDMI are beind a MST. See commit d182b63347c744c on how this was done for mainboard/fizz. BUG=b:147992492 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I19d40056e58f1737f87fd07d62b07a723a63d610 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2020-02-06nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev)Chris Morgan
The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board to enable the dGPU. Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2 Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38722 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-06cpu/x86: Put guard around align for smm_save_state_sizeEugene Myers
The STM support aligns the smm_save_state_size. However, this creates issue for some platforms because of this value being hard coded to 0x400 Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Change-Id: Ia584f7e9b86405a12eb6cbedc3a2615a8727f69e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38734 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-06mb/pcengines/apu2: use AGESA 1.0.0.4 with adjusted AGESA headerPiotr Kleinschmidt
PC Engines apu2 platform uses AGESA 1.0.0.4, because upstream AGESA 1.0.0.A doesn't work on apu2 - the platform doesn't boot. To properly utilize AGESA 1.0.0.4 we need to adjust AGESA header to state, which is compatible with AGESA 1.0.0.4 version. Cut out the changes introduced in CB:11225 exclusively for apu2 board. TEST=boot PC Engines apu2 and launch Debian Linux Change-Id: I3d85ee14e35dae8079e8d552b6530a3867f65876 Signed-off-by: Piotr Kleinschmidt <piotr.kleins@gmail.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-06mb/google/hatch: Add noise mitigation setting for dratini/jinlonWisley Chen
Enable acoustic noise mitigation, the slow slew rates are fast time divided by 8 and disable Fast PKG C State Ramp (IA, GT, SA). BRANCH=hatch BUG=b:143501884 TEST=build and verify that noise reduce. Change-Id: I65f47288a7b1da98296fdba87ab5ca0c3a567aaf Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38212 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-05security/intel/stm: Add STM supportEugene Myers
This update is a combination of all four of the patches so that the commit can be done without breaking parts of coreboot. This possible breakage is because of the cross-dependencies between the original separate patches would cause failure because of data structure changes. security/intel/stm This directory contains the functions that check and move the STM to the MSEG, create its page tables, and create the BIOS resource list. The STM page tables is a six page region located in the MSEG and are pointed to by the CR3 Offset field in the MSEG header. The initial page tables will identity map all memory between 0-4G. The STM starts in IA32e mode, which requires page tables to exist at startup. The BIOS resource list defines the resources that the SMI Handler is allowed to access. This includes the SMM memory area where the SMI handler resides and other resources such as I/O devices. The STM uses the BIOS resource list to restrict the SMI handler's accesses. The BIOS resource list is currently located in the same area as the SMI handler. This location is shown in the comment section before smm_load_module in smm_module_loader.c Note: The files within security/intel/stm come directly from their Tianocore counterparts. Unnecessary code has been removed and the remaining code has been converted to meet coreboot coding requirements. For more information see: SMI Transfer Monitor (STM) User Guide, Intel Corp., August 2015, Rev 1.0, can be found at firmware.intel.com include/cpu/x86: Addtions to include/cpu/x86 for STM support. cpu/x86: STM Set up - The STM needs to be loaded into the MSEG during BIOS initialization and the SMM Monitor Control MSR be set to indicate that an STM is in the system. cpu/x86/smm: SMI module loader modifications needed to set up the SMM descriptors used by the STM during its initialization Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-02-05mb/google/drallion: Fine tune touch screen power sequenceEric Lai
Follow HW change to use GPP_D15 as TS_RST. And change GPP_B21 from pltrst to deep in order to met power off timing. BUG=b:143733039 TEST=Check touch screen is functional in s0 and resume from s0ix Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/38665 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-05mb/google/hatch: Correct PCIe ports setting for mushuAmanda Huang
1. Enable PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to port 7 BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci. Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38399 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-05mb/intel/tglrvp: pin mux for ISHWonkyu Kim
TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable, PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c. Pin mux for ISH for TGLRVP ISHUART0: GPP_D13, GPP_D14 as NF1 ISHI2C0: GPP_B5, GPP_B6 as NF1 ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1 BUG=none BRANCH=none TEST=Build and boot to OS and check pinctl driver to check pin mux. Check ISHUART0, ISHI2C0, ISHGPIO0-7 native function setting. They should be NF1. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-02-05pciexp: Add support for allocating PCI express hotplug resourcesJeremy Soller
This change adds support for allocating resources for PCI express hotplug bridges when PCIEXP_HOTPLUG is selected. By default, this will add 32 PCI subordinate numbers (buses), 256 MiB of prefetchable memory, 8 MiB of non-prefetchable memory, and 8 KiB of I/O space to any device with the PCI_EXP_SLTCAP_HPC bit set in the PCI_EXP_SLTCAP register, which indicates hot-plugging capability. The resource allocation is configurable, please see the PCIEXP_HOTPLUG_* variables in src/device/Kconfig. In order to support the allocation of hotplugged PCI buses, a new field is added to struct device called hotplug_buses. This is defaulted to zero, but when set, it adds the hotplug_buses value to the subordinate value of the PCI bridge. This allows devices to be plugged in and unplugged after boot. This code was tested on the System76 Darter Pro (darp6). Before this change, there are not enough resources allocated to the Thunderbolt PCI bridge to allow plugging in new devices after boot. This can be worked around in the Linux kernel by passing a boot param such as: pci=assign-busses,hpbussize=32,realloc This change makes it possible to use Thunderbolt hotplugging without kernel parameters, and attempts to match closely what our motherboard manufacturer's firmware does by default. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I500191626584b83e6a8ae38417fd324b5e803afc Reviewed-on: https://review.coreboot.org/c/coreboot/+/35946 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-12 21:32:25 +0000