coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2017-11-14	mb/google/eve: Remove ACPI control of touchscreen power	Duncan Laurie
2017-11-14	mb/amd/gardenia: Remove direct AGESA header includes	Martin Roth
2017-11-14	soc/amd/stoneyridge: Remove direct AGESA header includes	Martin Roth
2017-11-14	soc/amd/common: Remove direct AGESA header includes	Martin Roth
2017-11-14	mb/google/kahlee: Remove direct AGESA header includes	Martin Roth
2017-11-14	AMD Stoney Ridge: Add agesa_headers.h	Martin Roth
2017-11-14	ec/lenovo/h8/acpi/ec: Add registers	Patrick Rudolph
2017-11-14	amd/common/spi: Update flash driver usage	Marshall Dawson
2017-11-14	soc/amd/stoneyridge: Load SMU fimware using PSP	Marshall Dawson
2017-11-14	amd/stoneyridge: Add generic IMC sleep and wakeup	Marshall Dawson
2017-11-14	amd/stoneyridge: Replace BIT(n) in southbridge	Marshall Dawson
2017-11-14	amd/stoneyridge: Define bits for AcpiConfig	Marshall Dawson
2017-11-13	mb/google/kahlee: Add getter function for GPIO array	Martin Roth
2017-11-13	mb/google/kahlee: Remove mainboard.h	Martin Roth
2017-11-13	mainboard/google/kahlee: Add Grunt variant framework	Martin Roth
2017-11-13	mainboard/google/kahlee: Add baseboard framework	Martin Roth
2017-11-13	soc/intel/common: Add error print in common i2c	Lijian Zhao
2017-11-13	soc/intel/cannonlake: Define default LPSS clock	Lijian Zhao
2017-11-13	soc/amd/stoneyridge: Add CPU PPKG ASL	Marc Jones
2017-11-13	soc/amd/stoneyridge: Add GNVS variables for thermal control	Marc Jones
2017-11-13	amd/gardenia: Add globalnvs.asl	Marc Jones
2017-11-13	soc/amd/stoneyridge: Fix DRAM clear check	Marshall Dawson
2017-11-13	google/chell: add missing SPD hex files	Matt DeVillier
2017-11-11	intel/fsp: Update cannonlake FSP header	Lijian Zhao
2017-11-11	vendorcode/amd/pi/00670f00: Set ModuleIdentifier to be 8 bytes	Martin Roth
2017-11-11	soc/intel/apollolake: Make use of Intel SPI common block	Subrata Banik
2017-11-11	soc/intel/apollolake: Add support for SPI device	Subrata Banik
2017-11-11	soc/intel/cannonlake: Make use of Intel SPI common block	Subrata Banik
2017-11-11	soc/intel/skylake: Make use of Intel SPI common block	Subrata Banik
2017-11-11	soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routine	Subrata Banik
2017-11-11	soc/intel/common/block: Add Intel common SPI support	Subrata Banik
2017-11-10	google/kahlee: Use devicetree register values for UMA	Marshall Dawson
2017-11-10	soc/amd/stoneyridge: Add UMA settings to devicetree	Aaron Durbin
2017-11-10	amd/stoneyridge: Implement vboot_platform_is_resuming	Marshall Dawson
2017-11-10	amd/stoneyridge: Add function to find Pm1EvtBlk base	Marshall Dawson
2017-11-10	amd/stoneyridge: Remove dead southbridge definitions	Marshall Dawson
2017-11-10	amd/stoneyridge: Add more ACPI register definitions	Marshall Dawson
2017-11-10	amd/stoneyridge: Use the new generic acpi_sleep_from_pm1	Marshall Dawson
2017-11-10	amd/stoneyridge: Select AMD common sleep states	Marshall Dawson
2017-11-10	arch/x86: Add common AMD ACPI hardware definitions	Marshall Dawson
2017-11-10	soc/amd/stoneyridge: Use uint8_t as type for SPD address	Richard Spiegel
2017-11-10	soc/amd/stoneyridge: Simplify and fix SMBUS code	Richard Spiegel
2017-11-10	google/kahlee: Add defines in OemCustomize.c	Marshall Dawson
2017-11-10	google/kahlee: Move DRAM clear override to devicetree	Marshall Dawson
2017-11-10	soc/amd/common: Add DRAM clear option to northbridge.c	Richard Spiegel
2017-11-10	soc/intel/cannonlake: Remove structure variable initialization with 0	Subrata Banik
2017-11-10	soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake	Subrata Banik
2017-11-10	soc/intel/apollolake: Include HECI BAR0 address inside iomap.h	Subrata Banik
2017-11-10	src/soc/amd/stoneyridge/southbridge.h: Fix prototypes	Richard Spiegel
2017-11-10	mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5	Ben Chan