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2021-03-22soc/amd/common/block/i2c: Move SoC agnostic parts into commonKarthikeyan Ramasubramanian
The logic behind I2C bus initialization, I2C MMIO base address getter and setter, I2C bus ACPI name resolution are identical for all the AMD SoCs. Hence moving all the SoC agnotic parts of the driver into the common driver and just configure the SoC specific parts into individual I2C drivers. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. Verify some I2C peripheral functionality like trackpad and touchscreen. Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22soc/amd/common: Introduce I2C driver common to all AMD SoCsKarthikeyan Ramasubramanian
I2C driver is replicated in each generation of AMD SoCs. Introduce a common I2C driver that can be used across all the AMD SoCs. To begin with, peripheral reset functionality is moved into this common driver. SoC specific I2C driver passes the SCL pin configuration in order for the common driver to reset the peripherals. More functionality can be moved here in subsequent changes. Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as an effort towards using inclusive language. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. localhost ~ # i2cdetect -y 0 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- -- 60: 70: localhost ~ # i2cdetect -y 1 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22soc/mediatek/mt8192: devapc: Add SCP domain settingTinghan Shen
Configure SCP domain from 0 to 3 and lock it to prevent changing it unexpectedly. BUG=b:163300760 TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Idccb001f0cf58492f7f1655203106470637b9b82 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-20soc/intel/xeon_sp/cpx: Set PCU locksMarc Jones
Set the PCU locks as indicated by the BWG. Lock the following: P_STATE_LIMITS PACKAGE_RAPL_LIMIT SAPMCTL DRAM_PLANE_POWER_LIMIT CONFIG_TDP_CONTROL Change-Id: I5f44d83e2dd8411358a83b5641ddb4c370eb4e84 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51505 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20soc/intel/xeon_sp/: Fix SMI_LOCK settingMarc Jones
Move the SMI_LOCK to post SMM setup. Also, use the correct access method for SMI_LOCK. GEN_PMCON_A is in PCI config space and not in MMIO space on this PCH. Change-Id: Ibbb183ef61ca7330198c1243ecfc2d4df51e652b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51452 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mainboard/: Register chipset_lockdown on xeon_sp mainboardsMarc Jones
Set chipset_lockdown in devicetree for recommended security settings. Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20soc/intel: Drop unused `GPIO_NUM_GROUPS` macroAngel Pons
This macro is unused and its value is often wrong. Drop it. Change-Id: Id3cfaa4d2eef49eddc02833efbe14e0c5c816263 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51662 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20mb/purism/librem_cnl: Add new board/variant Librem 14Matt DeVillier
Add support for the CometLake-U based Librem 14 laptop. Change-Id: I24a2a92091cc272638ecaf8ea23a896cab8a7153 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51549 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20google/trogdor: Add new variant MarzipanKevin Chiu
This patch adds a new variant called Marzipan that is identical to Lazor for now. BUG=b:182181519,b:182018606 BRANCH=master TEST=make Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20mb/google/trogdor: Add support for SPI_FLASH_GIGADEVICExuxinxiong
Add support SPI_FLASH_GIGADEVICE for some project. BUG=b:182246432 BRANCH=trogdor TEST=emerge-strongbad and test with power on. Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: I6ab948909f4e17b4b992be6d699646f7a62bef7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-19mb/lenovo/x200: Fix boot-time docking stateKevin Keijzer
The X200 would undock itself when waking up from S3, requiring a physical reconnection before the dock would work again. Similar to 4611ad8, this reintroduces h8_mb_init() for the X200. A hook function h8_mb_init() will be called at the end of h8_enable(), in place of the ancient h8_mainboard_init_dock(). This should fix the regression the X201 and T410 also suffered from for the X200. Change-Id: Icb6dd145e56b90e0e04133810c5e9ac7b641ad68 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51123 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/scaleway/tagada: Don't change FIAMUX when Security Override is setJulien Viard de Galbert
This will not enable M.2 SATA drive if the ME config was lost (For instance after flashing a full flash factory image) This is required so that the system can boot without FIA MUX error during flash update procedure. Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19security/intel/cbnt: Make CBNT compatible with CMOS option tableArthur Heymans
Make sure the bytes in RTC cmos used by CBNT don't collide with the option table. This depends on what is set up in the BPM, Boot Policy Manifest. When the BPM is provided as a binary the Kconfig needs to be adapted accordingly. A later patch will use this when generating the BPM. Change-Id: I246ada8a64ad5f831705a4293d87ab7adc5ef3aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/x86/mp_init.c: Drop unnecessary preprocessor usageArthur Heymans
Change-Id: If67bcbf0c8ffbd041e2e4cab8496f4634de26552 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init.c: Don't overwrite the global variable per CPUArthur Heymans
Global variables are located in .bss and not on the CPU stack. Overwriting them a per CPU case is bound to cause race conditions. In this case it is even just plainly wrong. Note: This variable is set up in the get_smm_info() function. Change-Id: Iaef26fa996f7e30b6e4c4941683026b8a29a5fd1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_module_loaderv2.c: Remove noop stack size checkArthur Heymans
The argument provided to the function was always the same as the one computed inside the function so drop the argument. Change-Id: I14abf400dce1bd9b03e401b6619a0500a650fa0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init: Allow stub sizes larger than the save state sizeArthur Heymans
The permanent handler module argument 'save_state_size' now holds the meaning of the real save state size which is then substracted from the CPUs save state 'top' to get the save state base. TESTED with qemu Q35 on x86_64 where the stub size exceeds the AMD64 save state size. Change-Id: I55d7611a17b6d0a39aee1c56318539232a9bb781 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_loaderv2: Remove unused variablesArthur Heymans
Remove variables that are either constants or are just assigned but not used. Change-Id: I5d291a3464f30fc5d9f4b7233bde575010275973 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm/smm_module_loaderv2.c: Constify setup_stub()Arthur Heymans
Change-Id: I6648d0710bc0ba71cfbaaf4db7a8c1f33bbc9b35 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_module_hander: Set up a save state mapArthur Heymans
With the smm_module_loaderv2 the save state map is not linear so copy a map from ramstage into the smihandler. TESTED on QEMU q35: Both SMMLOADER V1 and V2 handle save states properly. Change-Id: I31c57b59559ad4ee98500d83969424e5345881ee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/smm_loaderv2: Fix when only 1 CPU is presentArthur Heymans
Move out smm_create_map as this was not run if concurrent_save_states is 1. The cpus struct array is used in the smm_get_cpu_smbase() callback so it is necessary to create this. TEST: run qemu/q35 with -smp 1 (or no -smp argument) Change-Id: I07a98bbc9ff6dce548171ee6cd0c303db94087aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19cpu/x86/smm_stub.S: Drop smm_runtime from the stubArthur Heymans
The parameters that the permanent handler requires are pushed directly to the permanent handlers relocatable module params. The paremeters that the relocation handler requires are not passed on via arguments but are copied inside the ramstage. This is ok as the relocation handler calls into ramstage. Change-Id: Ice311d05e2eb0e95122312511d83683d7f0dee58 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/x86/smm.h: Remove smm runtime pointer from smm_loader_paramsArthur Heymans
struct smm_loader_params is a struct that is passed around in the ramstage code to set up either the relocation handler or the permanent handler. At the moment no parameters in the stub 'smm_runtime' are referenced so it can be dropped. The purpose is to drop the smm_runtime struct from the stub as it is already located in the permanent handler. Change-Id: I09c1b649b5991f55b5ccf57f22e4a3ad4c9e4f03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/x86/mp_init.c: Copy the stub parameter start32_offset into ramstageArthur Heymans
Keep a copy of start32_offset into ramstage to avoid needing to pass arguments, calling from assembly. Doing this in C code is better than assembly. Change-Id: Iac04358e377026f45293bbee03e30d792df407fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50765 Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19cpu/x86/smm_module_handler: Add relocatable module paramsArthur Heymans
Instead of passing on parameters from the stub to the permanent handler, add them directly to the permanent handler. The parameters in the stub will be removed in a later patch. Change-Id: Ib3bde78dd9e0c02dd1d86e03665fa9c65e3d07eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19cpu/intel/fit: Reserve the FIT pointer using a .c fileArthur Heymans
No need to do this assembly anymore. Change-Id: I69b42c31e495530fe96030a5a25209775f9d4dca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-03-19cpu/intel/fit: Add the FIT table as a separate CBFS fileArthur Heymans
With CBnT a digest needs to be made of the IBB, Initial BootBlock, in this case the bootblock. After that a pointer to the BPM, Boot Policy Manifest, containing the IBB digest needs to be added to the FIT table. If the fit table is inside the IBB, updating it with a pointer to the BPM, would make the digest invalid. The proper solution is to move the FIT table out of the bootblock. The FIT table itself does not need to be covered by the digest as it just contains pointers to structures that can by verified by the hardware itself, such as microcode and ACMs (Authenticated Code Modules). Change-Id: I352e11d5f7717147a877be16a87e9ae35ae14856 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50926 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19soc/amd/picasso/soc_util.c: Fix typo in macro nameAngel Pons
Change-Id: I3225fa4e53a75c2bf6fe0dcea85db57efe489482 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51615 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/google/volteer/var/elemi: Config GPP_B7/GPP_B8 as NCWisley Chen
elemi does not use the GPP_B7/GPP_B8, so config to NC. Currently, there is no functional impact. BUG=b:182981460 TEST=emerge-volteer coreboot, boot into OS, and suspend/resume successfully. Change-Id: I7b491fd595b0e77e6dcce08e3172dbe592f63c37 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnableDerek Huang
PmcUsb2PhySusPgEnable is enabled by default. Expose devicetree parameter to disable Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Change-Id: Ibd54a10c57d39bb8762b705ef0d6ff4cd47f0d89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19mb/purism/librem_cnl: drop MAX_CPUS from KconfigMatt DeVillier
No need to restrict this further than the platform default, and will be problematic with the addition of the upcoming 6C/12T Librem 14 board. Change-Id: I1913992ec12578e1ad3bf6bf679d1a35a46d7370 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19mb/{clevo/cml-u,system76/lemp9}: Clarify `gen2_dec` useAngel Pons
This I/O range is for a PM channel on the EC, not the PCH PMC. Change-Id: I64422e537c1edcd0673cf87f16139fb117b10e75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51604 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19nb/intel/haswell: Consolidate memory-down SPD handlingAngel Pons
Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to a struct instead of an array, and update all the mainboards accordingly. Currently, the only board with memory-down in the tree is google/slippy. Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts the channel population accordingly. Then, northbridge code reads the SPD file and uses the index that was read in `mb_get_spd_map`, and copies it to channel 0 slot 0 unconditionally. MRC only uses the first position of the `spd_data` array, and ignores the other positions. In coreboot code, `setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has to account for this. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19mb/google/slippy: Correct memory-down SPD handlingAngel Pons
MRC only uses the SPD data for the first index, and ignores the rest. Moreover, index 1 corresponds to the second DIMM on the first channel, which does not exist on ULT (only one DIMM per channel is supported). Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge code to retrieve the serial number from the correct SPD data block. Tested on Google Wolf, both channels are still correctly detected. Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-18mb/google/brya: Implement SLP_S0_GATE signalTim Wawrzynczak
The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to provide an indication to the rest of the platform when the system is entering its software-initiated low-power state (i.e. S0ix). This lets the platform distinguish between opportunistic S0ix entry and the runtime suspend mechanism. BUG=b:180401723 TEST=abuild Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18vc/google/chromeos/acpi: Add type to OIPG declarationRaul E Rangel
OIPG is a Package. Define the type so it doesn't default to UnknwonObj. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I068ed4ae95967aa884506c4971ee2e2dba7b5e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51537 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/amd/majolica: Generate OIPG PackageRaul E Rangel
This fixes the unknown reference errors for OIPG. Since Majolica doesn't actually have any of the GPIOs ChromeOS uses, we leave the arrays empty. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifeae84e0ccab187a4e7131cd6ea9e1336d79df67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51536 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Add eSPI GPIO back to init tableMathew King
GPIOs should be configured in ramstage even if they are configured in an earlier stage. BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I9896db41dbe2812856357510bc4420482e73ab3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51547 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/guybrush: Configure UART0 gpio in early stageMathew King
BUG=b:180721208 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8aa54acf1fa9295b27c33a0066432665e6e3755c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-18soc/amd/common: Make fch_spi_config_modes staticMathew King
It is currently only used in this translation unit. Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib779a38306fb45320f3e4eb71f63630023d59906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51535 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/ocp/deltalake: Initialize VPD 'coreboot_uart_io' with default value 1Johnny Lin
In case the VPD variable cannot be read. Change-Id: I79fae6f4b4aad91a4040387ca6ddee8dfcc34d90 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51559 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18mb/google/mancomb: Configure eSPI GPIOs in early stageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifa51705b3b5aab16f9cd2c11084220aafacd2774 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Configure early GPIOs in earliest stageEric Lai
Configure early GPIOs in verstage if it is run in PSP otherwise configure them in bootblock. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic1faeea59462319c1652c69034b4dde01669e13b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Enable internal graphics deviceEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0f5026b77513118a6c21eca78c9788c0bdc7ec6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/mancomb: Enable verstageEric Lai
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic07a3ac556637919742fcbe899ee3fdfac38bb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18mb/google/zork/var/shuboz: adjust telemetry settingsKane Chen
According to stardust test tracking report to adjust telemetry setting. VDD Slope : 30518 -> 30595 VDD Offset: 435 -> 77 SOC Slope : 22965 -> 24063 SOC Offset: 165 -> 105 BUG=b:182399760 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ie7e6af77bdaad6cc964ac206a69ccb854aae869f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-18mb/prodrive/hermes: Disable HDA codec Port E by default on R04+Angel Pons
If the board settings aren't valid, Port E uses the settings for earlier board revisions, which is undesired. Disable Port E by default on R04+. Change-Id: I03bd50b915a2120283b77179debaa735bb7ef027 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51529 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18cpu/x86/mp_init.c: Calculate perm_smbase from ramstage dataArthur Heymans
The data needed to compute the permanent smbase for a core, when relocating, is present in the ramstage data which the stub located at DEFAULT_SMBASE (0x30000) calls back to. There is no need to fetch this from via the stub params. Change-Id: I3894c39ec8cae3ecc46b469a0fdddcad2a8f26c4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18cpu/x86/smm: Move apic_id_to_cpu map to smm_stub paramsArthur Heymans
This is only consumed by the stub and not by the relocation handler or the permanent handler, so move it out of the runtime struct. Change-Id: I01ed0a412c23c8a82d88408be058a27e55d0dc4d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-18cpu/x86/smm_stub.S: Drop unused module_handler parameterArthur Heymans
Change-Id: I15b433483c36cce04816e8895789997d91702484 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-23 11:38:05 +0000