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2018-05-04mainboard/google: Comment variant names in KconfigMartin Roth
It's very confusing trying to find the google platform names, because they seem all unsorted in Kconfig. They're actually sorted according to the variant name, but previously, that was impossible to tell. - Add a comment to the top of variants in Kconfig.name - Inset each variant name. If you start a prompt with whitespace, it gets ignored, so after trying various ways to indent, the arrow was the option I thought looked the best. It now looks like this: *** Beltino *** -> Mccloud (Acer Chromebox CXI) -> Monroe (LG Chromebase 22CV241 & 22CB25S) -> Panther (ASUS Chromebox CN60) -> Tricky (Dell Chromebox 3010) -> Zako (HP Chromebox G1) Butterfly (HP Pavilion Chromebook 14) Chell (HP Chromebook 13 G1) Cheza *** Cyan *** Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-03mainboard/google/kahlee: Update grunt touchscreen in devicetreeMartin Roth
- Add raydium controller - Update elan controller with reset and enable GPIOs. - Enable 'probed' so Linux will check which controller is being used. BUG=b:78929054 TEST=Both elan and raydium touchscreen controllers work Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03vendorcode/amd/agesa: Fix variable length array declarationKyösti Mälkki
Fix (assumed) regression with commit ac63b41 vendorcode/amd/agesa: Fix variable length array declaration The code used sizeof() on the struct where array length was previously adjusted, but only f14 case was fixed accordingly. Change-Id: Ib83660d5e102e13b4ffad19fb78f695ac4a871dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26036 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03pci: Add dummy file for ARM64Patrick Rudolph
Add stub files to support compiling the PCI driver on ARCH_ARM64. Change-Id: Iaff20463375d1e3ec573d9486a859a0514b0b390 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-03pci: Fix function prototypePatrick Rudolph
Fix a function prototype to support PCI on non x86. The function itself does have the correct argument already. Change-Id: I564fcfe9b85ed4f841a48fe17a3f5bf80e16560b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-03vendorcode/amd/agesa: Fix variable length array declarationPaul Menzel
Definition of S_PSTATE only allowed PStateStruct[0], while it is effectively used as a flexible array. Since sizeof(S_PSTATE) is reduced here by sizeof(S_PSTATE_VALUES), we have to account for that when calculating PStateLevelingSizeOfBytes. In S_PSTATE context, PStateStruct[PStateMaxValue] is valid reference. GCC 7.2.0 warns about an out of bounds array subscript. ``` CC libagesa/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.o src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c: In function 'PStateLevelingMain': src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c:524:65: error: array subscript is above array bounds [-Werror=array-bounds] PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html Change-Id: If9598a951c6b882432689b677a956c44650c7083 Found-by: gcc (Debian 7.2.0-2) 7.2.0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21297 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03cpu/x86: Add infinite timeout support into run_ap_work() functionSubrata Banik
There might be certain requirement in user function where user might not want to pass any timeout value, in those cases run_ap_work() should consider infinity as timeout and perform all APs initialization as per specification. Set expire_us <= 0 to specify an infinite timeout. BRANCH=none BUG=b:74436746 TEST=run_ap_work() is running successfully with 0 expire_us. Change-Id: Iacd67768c8a120f6a01baaa6817468f6b9a3b764 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25622 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03mainboard/winent: Remove unnecessary braces {}Elyes HAOUAS
Fix coding style Change-Id: I48a7bd4bd98d1a9d7b0ce4c12e09284fa4be6c7a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03southbridge/broadcom: Remove spaces before/after parenthesisElyes HAOUAS
Change-Id: Ic43b5ddaa395658ab7c34cdd004516884a20b005 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03mainboard/msi/ms9185: Fix coding style and remove commented codeElyes HAOUAS
Change-Id: I3cca4adbf04edfd88a9b8ae52cf4d62d429e6c45 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03mainboard/hp/dl145_g1: Fix coding styleElyes HAOUAS
Change-Id: I8cfddbf49b3042d46956985425990360f0903b1f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03arch/x86: Relocate GDT in verstage, romstage, and postcarHannah Williams
In each stage keep GDT in the code region. This accommodates platforms, such as glk, that are executing out of CAR. The gdt is small and loading it is trivial so just do it unconditionally instead of introducing another Kconfig. BUG=b:78656686 Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-05-03arch/x86: reduce complexity in assembly_entry.SAaron Durbin
Now that VBOOT_STARTS_IN_BOOTBLOCK depends on C_ENVIRONMENT_BOOTBLOCK, remove the complications in assembly_entry.S. There's no platform utilizing romcc bootblock and needing to handle verified boot after bootblock as well as not using verified boot. That combination makes things very complicated. Clean up the complication as it's not a combination that needs to be supported. BUG=b:78656686 Change-Id: Ie2960790d60ccb8d5b75dab507fe70a6563b3d34 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25968 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03security/vboot: make vboot starts in bootblock depend on c envAaron Durbin
coreboot on skylake originally did ship with romcc bootblock and verstage running after it. However, that configuration makes boot flows very complicated. No platform in the current code base uses this combination. Make VBOOT_STARTS_IN_BOOTBLOCK depend on C_ENVIRONMENT_BOOTBLOCK. BUG=b:78656686 Change-Id: Ia9446f209521f71c91b83d579b9e2d89744292bc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-05-03ec/google/chromeec: Update Tablet event callMartin Roth
The tablet event handler method TPET is defined as an extern, then defined again in skylake, the only platform that supports it. In newer versions of IASL, this generates an error, as the method is defined in two places. Remove the extern and the CondRefOf check. That's not needed if we only set the EC_ENABLE_TABLET_EVENT define on platforms that have a TPET handler. Change-Id: I8bee069fc95637446593dfaaae1254e931421517 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-05-03mainboard/google/reef: Remove tablet mode switch supportMartin Roth
The _SB.DPTF.TPET ACPI code attached to EC_ENABLE_TABLET_EVENT doesn't exist in the apollo lake code. Remove it from reef as part of the cleanup to update to the new version of IASL. This was in commit 4f803ac28f4 (mainboards/google/reef: Add support for tablet mode switch.) Change-Id: Ic10c418ddc708c1aed87ad4a9861f04d32445116 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02google/kahlee: Set SPI 100 MHz and SPI Dual Read IO modeMarc Jones
Set SPI Fast Read to 100MHz and Dual Read IO mode to speed up the boot process by over a half second. Also, increase the Normal Read speed to 33MHz as supported by the W25Q128FW. BUG=b:70558952 TEST=Run cbmem -t to get boot times. Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-02soc/amd/stoneyridge: remove sb_set_readspeed functionMarc Jones
The sb_set_readspeed() was touching the wrong register and the read speed settings are handled by sb_set_spi100(). Nothing was using the function, so remove it. Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-02mb/google/kahlee/variants/grunt: Enable BayHub720 driverSimon Glass
Enable this driver along with power saving. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02drivers/generic/bayhub: Add driver for BayHub BH720Simon Glass
Add a driver which puts the device into power-saving mode. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: Idbfb114f3782c9386ce9b487c3abdb0afbc4a0d9 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02mb/google/poppy/variants/nami: Enable touchscreen through ACPIShelley Chen
Currently, we've set TOUCHSCREEN_DIS gpio to disabled. Enabling through ACPI. Set reset/enable/stop_off_ms variables to get timings of power off sequence correct. BUG=b:78311818 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: Ib1543f41f24cbe8c33aeb02e6aa43fd3dd977ed4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-05-02src/drivers: Add reset/enable/stop_off_ms variables to ACPI devicesShelley Chen
Some touchscreens need to adhere to certain timings during the power off sequence as well as during the power on sequence. Adding reset_off_delay_ms, enable_off_delay_ms, and stop_off_delay_ms to accommodate these devices. BUG=b:78311818 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: Idb4a5dbe56eee4749d2f2b514e92c28fb2c6078f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-02intel/common: compress VBTPatrick Georgi
It's pretty well compressible which helps when space is tight. The code encodes the assumption that the VBT is 8kb or less. Haven't seen a larger one yet. BUG=b:77971803,b:78541692 TEST=build, see that vbt.bin is compressed, boot, check log that the reported VBT size is correct. Change-Id: Ie25bca21d9edc408f441a292bbe2ab0459948ec4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/25927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02mb/sapphire/pureplatinumh61: Use custom SPI OPMENUNicola Corna
The SPI chip in this board needs a custom OPMENU, otherwise flashrom fails halfway during the write. From the default OPMENU, Block Erase (0xd8) has been replaced by AAI write (0xad) and Fast Read (0x0b) by Write Disable (0x04). Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320 Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/25551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-02mb/lenovo/x201: Add Lenvovo X201i to the list of X201 variantsMatthias Gazzari
The X201 coreboot image is working well on the X201i. Besides, the X201i seems to be almost identical to the X201 except for the CPU. Change-Id: Iecc84faf78e7de34fb1add63c20904a5a28c5e9b Signed-off-by: Matthias Gazzari <mail@qtux.eu> Reviewed-on: https://review.coreboot.org/25971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-02intel/ibexpeak: Fix missing ACPI PIRQ entriesKyösti Mälkki
Fix regression after commit 7f5efd9 intel/bd82x6x: Use generated ACPI PIRQ The call to inject generated PIRQ entry was not added when the static entries as default_irq_route.asl file was removed from boards using intel/nehalem southbridge. Change-Id: I8097c1ab729d1eb91a6d547ef13948c1e21eca10 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/25965 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matthias Gazzari <mail@qtux.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02src/device: Fix discarded-qualifiers compilation issueSubrata Banik
coreboot build is broken due to CL: I6830a65bc9cea2907f4209bb97a53ccebcbf248d This patch ensures to build coreboot successfully. Change-Id: I4c9dfc9b19ce159ce1abcfbb287be4ce273cbaf1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-02mb/google/octopus: Configure pins to reflect delta w.r.t yorpShamile Khan
Changes in pin usage between yorp and bip - LTE_OFF_ODL pin moved from GPIO_161 to GPIO_66 - I2S0 interface is not used in bip. It was used in yorp for DMIC Wake on Voice through Nuvoton EC. Also fix both bip and yorp pin settings for LTE_OFF_ODL (Enable LTE and add an internal pull up). Internal pull up can be removed later when sub-board (which will have an external pull up for this signal) is available. BUG=b:77869623 BRANCH=none TEST=Build coreboot for octopus. Change-Id: I8907bd63a43c4bc51ca991c3ec7c1cae9e39e2d1 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-02lib/cbfs.c: fix typoPatrick Georgi
Change-Id: I39c12ab3f28b5448fa4f46958cf23f2623a92378 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/25928 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02pci: Fix MMCONF_SUPPORT on non x86Patrick Rudolph
Move x86 specific pci_bus_default_ops into arch/x86 folder. Fixes compilation on platforms that do neither have MMCONF_SUPPORT nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI. Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02arch/x86: Print CPU Index and APIC ID in case of exceptionSubrata Banik
BUG=b:74436746 BRANCH=none TEST=Able to get APIC ID number for debug. Change-Id: I2d3776c9259747197a5f2410032f9b03786407fb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-02software_i2c: Improve error behaviorJulius Werner
This patch fixes a bug in the software_i2c (bitbang) framework where it would previously not return an error when receiving a NACK on a write transaction (deviating behavior from our hardware I2C drivers). It also adds explicit error codes to be returned for the different kinds of failure conditions so they are more useful for debugging when dumped. Change-Id: Ie63bf35123d89dcd99a1f9c079d4cae6a33b0b09 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-05-01sdm845: Add Timer supportT Michael Turney
Frequency set to 19.2 MHz TEST=build Change-Id: I56e57156df8a74cf629f7ada86cf5a5fcd5ad3c4 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-01asrock/b75pro3-m: fix the HDMI portIru Cai
At the time I ported coreboot to this board, the HDMI port of my board was broken, so I couldn't test libgfxinit on HDMI. Change-Id: Ibb8a4ef55bd97fd2d0baacdbc72863c0985d3d76 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/25820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-01mb/google/poppy: Add variant for nocturneNick Vaccaro
Add a new variant of poppy for the nocturne board. Key differences from baseboard include: - GPIO changes - devicetree.cb changes - memory stuffing option changes BUG=b:78122599 BRANCH=none TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I11c7829041b3c45407c17f71b08cc7fc17f717e8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/25803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-01mb/google/poppy/variants/nami: Enable Synaptics touchpadivy_jian
BUG=b:74595037 TEST= 1. emerge-nami coreboot chromeos-bootimage 2. check touchpad function 3. evtest /dev/input/event5: PNP0C50:00 06CB:CD84 Change-Id: I47cb1b13881f0d52860f0afe4bbca7483409de54 Signed-off-by: ivy_jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25913 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01nb/intel/x4x: Change memory layout to improve MTRRArthur Heymans
This change also makes sure that the sum the uma regions (TSEG, GSM, GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between 2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR setup for ramstage. At least tianocore requires this and fails to boot without it. Better MTRR are achieved by making the memory 'hole' till 4GiB exactly 2Gib. This code mimics how it is done in nb/intel/gm45 and achieves similar results. TSEG is enabled and set to 8M since this makes it easier to reuse the common smm setup / parallel mp code and makes it possible to cache the ramstage in there like how it's done on newer targets. TESTED on Intel DG43GT. Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-01nb/intel/x4x: Fix programming CxDRBArthur Heymans
Programming CxDRB should be cumulative as explained in "Intel ® 4 Series Chipset Family datasheet". This does not seem to have any real impact but better do according to the documentation and what vendor firmware does. This also removes some dead code. Change-Id: I7ff3264824c843f84b9eb6c06a06aa3f151fe4b3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22911 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01nb/intel/x4x: Implement both read and write trainingArthur Heymans
This training find the optimal write DQ delay and read DQS delay settings. It does so on all lanes at the same time, like vendor (training each lane individually has poor results). The results are stored in the sysinfo struct and restored on next boots and S3 resume. This potentially increases stability as optimal settings are chosen and is more necessary for DDR3 raminit where the write DQS delays are leveled/variable due to the flyby topology. TESTED on Intel DG43GT with (2G + 1G) on each channel, see that the results are quite close to the safe original ones (that previous worked fine) and tested with memtest86+. Change-Id: Iacdc63b91b4705d1a80437314bfe55385ea5b6c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-01mainboard/hp/dl145_g3: Fix coding styleElyes HAOUAS
Change-Id: I78b43cbc052e6d243d67ca8cdd86b242e477a2c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23532 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01Fix freeze during chipset lockdown on NehalemMatthias Gazzari
Remove locking of PCI device 00:00.0 registers (nehalem/finalize.c) and remove setting the zeroth bit of the MSR_LT_LOCK_MEMORY = 0x2e7 MSR register (model_2065x/finalize.c) to fix a frozen boot and S3 resume issue which became apparent with commit d533b16669a3bacb19b2824e6b4bc76a2a18c92a. More detailed, either setting the LSB of the 32 bit register at 0x98 of the PCI device 00:00.0 (in the intel_nehalem_finalize_smm function) or setting the LSB of the the MSR register MSR_LT_LOCK_MEMORY = 0x2e7 (in the intel_model_2065x_finalize_smm function) indepentenly causes a freeze during bootup or a complete session loss on resuming from S3 as described here: https://mail.coreboot.org/pipermail/coreboot/2018-April/086564.html It seems like Nehalem CPUs do not have a MSR_LT_LOCK_MEMORY register. Additionally, the "Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series, Datasheet Volume Two" indicates that registers of the PCI device 00:00.0 cannot be locked manually. Instead, they can only be locked by TXT, VT-d, CMD.LOCK.MEMCONFIG, ME_SM_LOCK or D_LCK. Finally, the addresses and sizes of these registers were partially wrong. Tested on Lenovo X201i with a Core i3 330M (no AES-NI, no VT-d and no TXT support compared to the Core i5 and Core i7 processors of a X201). Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b Signed-off-by: Matthias Gazzari <mail@qtux.eu> Reviewed-on: https://review.coreboot.org/25914 Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01chromeec platforms: Update ACPI thermal event handler callMartin Roth
Currently the thermal event handler method TEVT is defined as an extern, then defined again in platforms with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-01drivers/intel/fsp2_0: Include MP services header for UDK2017 supported platformSubrata Banik
BRANCH=none BUG=b:74436746 TEST=Able to include EFI_MP_SERVICES_PPI without any error. Change-Id: I5add8e533dfd3f6d03abf7b2ca1a83f81f1c5920 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-30southbridge/intel: Remove space before/after parenthesisElyes HAOUAS
Change-Id: Id1bc0c88aeecc3f1d12964346326e5b087a2985e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25880 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-30lib/bootmem: Introduce custom bootmem tagsPatrick Rudolph
Introduce bootmem custom memory tags and use them instead of reusing LB_MEM tags. Use asserts in bootmem_add_range to verify parameters. Tested with uImage payload on Cavium SoC. Change-Id: I7be8fa792fc7933ca218ecd43d250d3a9c55caa6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30lib/devicetree: Integrate flattened devicetree supportPatrick Rudolph
* Adapt to coreboot coding style. * Use coreboot's endian conversion functions. * Fix header and header guards. * Get rid of unused functions. * Add Kconfig to build it on ramstage. * Replace size32 with ALIGN_UP and DIV_ROUND_UP. * Add NULL pointer checks * Convert constants to defines Required for Cavium's BDK and uImage FIT support. Change-Id: I6e6cd9f78fb402bd54d684097326d26eb78d552a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30lib: Raw import FDT devicetree from depthchargePatrick Rudolph
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge Required for general devicetree patching and FIT support. Coding style and coreboot integration will be done in a separate commit. Change-Id: Ida75d4786eae38d84bfc71bf53573dafca8eda40 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-04-30mb/lenovo/x220: Allow optional use of the mrc.binArthur Heymans
Besides the FSP codepath, Sandy Bridge has two codepaths, one native and one in the form of a binary. This allows the use of the binary. This can be useful to find flaws in the native raminit. The native raminit is still selected by default. Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-04-30asrock/b75pro3-m: use the ASPM blacklist driverIru Cai
After commit 2188f57a (src/device: Update LTR configuration scheme) coreboot will hang when reading resources on the ASMedia SATA controller, although there is already an ASPM config override. So use the ASPM blacklist driver instead of setting the ASPM override in the devicetree. Change-Id: I807d9bd4deef8c1528dff96c7646240ef75e1953 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/25819 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-30nb/intel/fsp_rangeley: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I0b969a5109276d108e6140bad338c74786b967f3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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