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2020-12-28drivers/intel/gma: drop unused register to resolve name conflictMichael Niewöhner
The register `ESR` conflicts with the `Exception syndrome register` in UDK2017. To resolve the conflict, drop the unused `ESR` register from gma registers. It can be readded and prefixed or renamed if it's required at a later point. Change-Id: Icfdd834aea59ae69639a180221f5e97170fbac15 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28drivers/libgfxinit: Add Comet Lake to supported platformsFelix Singer
Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I002ade555c0544e4ef738c1ad45ee3d8aa38e03e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-283rdparty/libgfxinit: Update for Cannon Point supportNico Huber
We missed that Cannon Point, the PCH usually paired with Coffee, Whiskey and Comet Lake, differs a bit from its predecessors. Hence, libgfxinit now has a new Kconfig setting for the PCH. Change-Id: I1c02c0d9abb7340aabe94185ee5e17ef4c2b0d36 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28mb/kontron/bsl6: Remove disabled devices from devicetreesFelix Singer
All known on-chip PCI devices are documented in chipset devicetree now and default to disabled. There is no need to keep disabled PCI devices in the mainboard's devicetree. Thus, remove them. Change-Id: I0f78dadd9e55a8f002394dc07ab514ca13f4e963 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-28soc/intel/apl: Fix indentsFelix Singer
Change-Id: Ide10889ad01ec6d31ee83158182876625a68a5da Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48888 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28soc/intel/xeon_sp: Lock PAM and SMRAM registersArthur Heymans
The CedarIsland FSP Integration recommends locking down some things. Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47168 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28soc/intel/xeon_sp: Lock down IIO DFX Global registersArthur Heymans
This is required for CbNT. Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28soc/intel/xeon_sp: Lock down DMI3 PCI registersArthur Heymans
This is required for CBnT. Change-Id: If5637eb8dd7de406b24b92100b68c5fa11c16854 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28soc/mediatek/mt8192: add rtc MT6359P driverYuchen Huang
Add rtc MT6359P driver for rtc init and rtc eosc calibration. Refactor mt8173 and mt8183 code by extracting common API. Move rtc_read and rtc_write to each SoC folder, because mt8173 and mt8183 access rtc via pmic wrapper, while mt8192 accesses it via pmif. Reference datasheet: Document No: RH-D-2018-0101. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28soc/mediatek/mt8192: devapc: add basic devapc driversNina Wu
Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. Change-Id: I2ad47c86b88047c76854a6f8a67b251b6a9d4013 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28soc/mediatek/mt8192: Do dramc pre-settings before calibrationHuayang Duan
Before calibration, dramc resets the delay of each PHY IO, calculates TX path and sets CKE to be rank independent. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28kconfig: remove non-existent sourceJack Rosenthal
src/northbridge/amd/pi/00660F01/Kconfig does not exist. Remove the source statement. Also, no kconfig files under src/soc/intel/common/basecode/. Clean that up. Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-28soc/intel/skylake: Enable CHAP device depending on devicetreeBenjamin Doron
Now that CHAP device is declared in chipset devicetree, hook it up to devicetree configuration. Change-Id: Icc51f7b9cda32d5058dce958e386921b6d3d8ffb Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48323 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28sb/amd/pi/hudson: Enable use of common GPIO APIKyösti Mälkki
The code in soc/amd/common has an implementation of GPIO register space that is compatible with the hardware sb/amd/pi/hudson supports. Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-27mb/siemens/chili/base: Add SMBIOS slot descriptionsFelix Singer
Add SMBIOS slot descriptions for M.2 ports and remove duplicate comments. Change-Id: Ieff03ad3167aec054cdc6b67ddc20fc64394e347 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-27vpd: Add vpd_get_int() functionNico Huber
Change-Id: I1c1b5710a5236fe4a3bdda1fc978393e636e9817 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45773 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-27src/superio: trim and move Makefile.inc, instead use wildcard matchesIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: If77d59485451c77dcea752bc4fe0dfadba8fec45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25cpu/intel/model_206ax: Add more CPU steppingsAngel Pons
The Sandy Bridge steppings appear in the BWG, and Ivy Bridge steppings appear in reference code. Add them for the sake of completeness. Change-Id: I7d17cdd04a771ca319c908fc757f868e95ea7944 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-25nb/intel/sandybridge: Move steppings to CPU headerAngel Pons
The steppings correspond to the CPUID bits 3:0, so move them to the CPU scope, and include the CPU header from files using the stepping macros. Change-Id: Idf8fba4911f98953bb909777aea57295774d8400 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48409 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25nb/intel/sandybridge: Rewrite constant valuesAngel Pons
Rewrite some constants to make their meaning somewhat clearer. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I321f5e61d7c695ae77e61b84728e34930f69d400 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-25nb/intel/sandybridge: Allow to ignore XMP voltageAngel Pons
Native raminit only supports 1.5V operation, but there are DIMMs which request 1.65V operation in XMP profiles. Add an option to force XMP to be used when the requested voltage isn't supported, which will run the DIMMs at 1.5V with XMP timings. Consider this to be overclocking. Change-Id: I64bfac8f72dadf662ceadfc7998daf26edf5a710 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-25ACPI: Allocate GNVS early in ramstageKyösti Mälkki
We need this to happen prior to SMM module loader. If there is some debugging output it's better they do not appear in the middle of CPU bringup. Change-Id: I45b4b5c0c5bf8bee258a465d1e364bfe98190e44 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-25ACPI: Fix some GNVS field commentsKyösti Mälkki
Change-Id: I0d1e7b86d5b98da85bf539a4a3ec23e0eeaa4dfc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-25sb,soc/intel: Fix GNVS OperationRegionKyösti Mälkki
Structure with chromeos_acpi_t is expected to have size 0x1000. Only ones with device_nvs_t have size 0x2000. Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-25mb/google/dedede: Update galtic device treeFrankChu
Update galtic device tree override to match schematics. BUG=b:170913840 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/48656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-25soc/intel/common/gfx: rename and guard graphics_soc_init()Matt DeVillier
Rename to graphics_soc_panel_init, to more accurately convey operations performed by the function. Guard execution so we don't attempt to reconfigure the panel after FSP has already done so. This fixes FSP/GOP display init on APL/GLK, which was broken by attempting to configure the panel after FSP had already done so. Change-Id: I8e68a16b2efb59965077735578b1cc6ffd5a58f0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48884 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25drivers/ipmi: Add Supermicro OEM commandsPatrick Rudolph
Add a new driver for OEM commands and select it from x11-lga1151-series. The driver communicates the BIOS version and date to the BMC using OEM commands. The command should be supported on all X11 series mainboards, but might work with older BMC, too. Tested on X11SSH-TF: The BIOS version strings are updated on boot and are visible in the BMC web UI. Change-Id: I51c22f83383affb70abb0efbcdc33ea925b5ff9f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-24mb/prodrive/hermes: Drop EEPROM address function parametersAngel Pons
Only one EEPROM is used to store the board settings, and its I2C address is constant. Thus, there's no need to pass its address as a parameter. In addition, reduce the scope of the `I2C_ADDR_EEPROM` definition, since using it outside of eeprom.c would bypass the API's abstraction layer. Change-Id: I958304e6ed6df05af923139d44ff4fd1de204738 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24mb/prodrive/hermes: Use already-defined SMBus macrosAngel Pons
Drop chipset register definitions in mainboard code in favor of existing definitions in a header. These definitions are not mainboard-specific. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I29d6f35ec27bff43cf52ae697e905b6a7b48a8d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24mb/supermicro/x11-lga1151-series: Select DRIVERS_UART_8250IOPatrick Rudolph
Change-Id: I0251d1193bb36ae73d592a0d17f580b7edaddbf6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48853 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24mb/google/volteer/variant/lindar: Add SSD D3 cold supportKevin Chang
This patch add SSD D3 cold support for lindar. BUG=b:172405687 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ie343bbff3bde4ff2a7e89bd384d5661af372b560 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-24mb/google/volteer/var/voema: Disable PCIe 7 and 8 for WLAN and SD cardDavid Wu
Based on latest schematic, disable PCIe 7 and 8 for WLAN and SD card. BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2a4658a382c094c2a5b16b7acaf464f54e9897b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-24mb/google/volteer/var/voema: Enable RTD3 for the NVMe deviceDavid Wu
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state. BUG=b:169356808 TEST=tested on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48848 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24soc/intel/xeon_sp/cpx: Disable isoch operation for performanceJohnny Lin
Isochronous operation negatively impacts memory performance, as per Intel MLC (Memory Latency Checker) benchmark results. Thus, disable isochronous operation, like analogous UEFI firmware does. The MLC results after disabling isoch: "--max_bandwidth" ALL Reads : 106948.17 3:1 Reads-Writes : 101580.46 2:1 Reads-Writes : 100523.26 1:1 Reads-Writes : 99059.44 Stream-triad like : 97762.47 "--peak_injection_bandwidth" ALL Reads : 105724.3 3:1 Reads-Writes : 100655.8 2:1 Reads-Writes : 99463 1:1 Reads-Writes : 98708 Stream-triad like : 91515 The MLC results before disabling isoch: "--max_bandwidth" ALL Reads : 88824.96 3:1 Reads-Writes : 94820.81 2:1 Reads-Writes : 94867.53 1:1 Reads-Writes : 92567.36 Stream-triad like : 91900.43 "--peak_injection_bandwidth" ALL Reads : 88859.6 3:1 Reads-Writes : 94064 2:1 Reads-Writes : 94186.2 1:1 Reads-Writes : 92516.1 Stream-triad like : 85147.4 TEST=On OCP Delta Lake, verify that MLC benchmark results have improved. Change-Id: I08c22ee001b601e607452b3f23fad969ecb484b4 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48738 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-24mb/google/kukui: Add a new config 'Katsu'Sunway
A new board introduced to Kukui family. BUG=b:176206134 TEST=make # select Katsu BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I09fe2b8f6922dfd2af6424830568466fb98f7aee Reviewed-on: https://review.coreboot.org/c/coreboot/+/48874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-23soc/intel/common: Remove unused SOC_INTEL_COMMON_ACPIMarc Jones
Remove the unused SOC_INTEL_COMMON_ACPI Kconfig option. Change-Id: Id62cd44e0f7e4175ae65c9388569231d5c8c1fbc Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-23src/soc/intel/xeon_sp/acpi.c: Remove unnecessary .hMarc Jones
Remove the unnecessary header file includes. Change-Id: I0d849cb236f304b87332aa64b2f10c73cad2d4dd Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-12-23nb/intel/sandybridge: Refactor ODT stretch table codeAngel Pons
Leverage existing `ch_dimms` value and use constants for brevity. Change-Id: I4e08166c8e9fbd15ff1dcd266abb0689e4b159f7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-23nb/intel/sandybridge: Refactor `dram_find_spds_ddr3`Angel Pons
Pointers to structs can be very useful, especially when they point to an array element. In this case, changing one pointer allows the function to be rewritten more concisely, since most redundancy can be eliminated. Tested on Asus P8Z77-V LX2, still boots. No functional difference. Change-Id: I7f0c37ea49db640f197162f371165a6f8e9c1b9c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-23nb/intel/sandybridge: Always wait for IOSAV after starting itAngel Pons
Ensure that IOSAV is finished before continuing. This might solve some random failures on the I/O and roundtrip latency training algorithm. Tested on Asus P8Z77-V LX2, still boots. Change-Id: Ic08a40346b6c60e372bada10f9c4ee42eb974f9f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48403 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23nb/intel/sandybridge: Introduce `iosav_run_once_and_wait`Angel Pons
Most ofte, `iosav_run_once` precedes a `wait_for_iosav` call. Add a helper function to reduce clutter. The cases where `iosav_run_once` isn't followed by `wait_for_iosav` will be handled in a follow-up. Tested on Asus P8Z77-V LX2, still boots. Change-Id: Ic76f53c2db41512287f41b696a0c4df42a5e0f12 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48402 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23nb/intel/sandybridge: Remove unnecessary commentsAngel Pons
These comments were helpful before the massive IOSAV refactoring, but they are no longer needed since the function names are clear enough. Change-Id: Ieb9bdf3f7fc72f63a8978f2b98e0bc8228c55868 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48401 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23nb/intel/sandybridge: Print delays in decimalAngel Pons
Print delay values in a suitable format for human consumption. Change-Id: I0d86187d3e458ee2cb3fd11ec896ac363b8d3249 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48400 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23nb/intel/sandybridge: Add comment to TC_RWP writeAngel Pons
Change-Id: I164daa59696f2fe8de3a4b3e7da46c7c723778eb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48602 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23nb/intel/sandybridge: Use proper names to refer to training stepsAngel Pons
Now that the purpose of each training algorithm is clear, replace the last instances of the original names in comments and print statements with the current, correct names. Also, print which channel has failed command training, for completeness and consistency with other errors. Change-Id: I9cc5c4b04499297825ca004c6bd1648a68449d2c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48601 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23nb/intel/sandybridge: Add comments about I/O and RT latencyAngel Pons
Document the algorithm to adjust I/O and roundtrip latencies. Change-Id: Ic8b9aed54a34bb3252c457e87e81387fd410e305 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48397 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23nb/intel/sandybridge: Rename I/O data timingsAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: I147ba0ade8a5317a0fe76e9ea84947fd91d794b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47773 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23nb/intel/sandybridge: Use bitfields for I/O data timingsAngel Pons
Refactor in preparation to split up `program_timings`. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I68410165f397d8b4f662e40e88fb6a58ab1c5cff Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47772 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23nb/intel/sandybridge: Compute data timings independentlyAngel Pons
Use absolute values for the Rx and Tx bus timings instead of values relative to the CA (Command/Address) bus timing. This makes the calculations more accurate, less complex and less error-prone. Tested on Asus P8H61-M PRO, still boots. Training results do not seem to be affected by this patch, and the margins roughly have the same shape. Change-Id: I28ff1bdaadf1fcbca6a5e5ccdd456de683206410 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47771 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23Makefile: Add $(xcompile) to specify where to write xcompileRaul E Rangel
This file was being written to the root src directory. It is the only file being written to src during a normal build, while all others are being written to $(obj). I added a new variable to allow specifying the xcompile path. This allows generating a single file if building multiple boards. I also moved the default location into $(obj) so we don't pollute the src directory by default. I also cleaned up the generation of xcompile by removing the unnecessary eval and NOCOMPILE check. I also left .xcompile in distclean so it cleans up stale files. Since .xcompile is written into $(obj), `make clean` will now remove it. The tegra Makefiles are outside of the normal build process, so I just updated those Makefiles to point to the default xcompile location of a normal build. The what-jenkins-does target had to be updated to support these special targets. We generate an xcompile specifically for these targets and pass it into the Makefile. Ideally we should get these targets added to the main build. BUG=b:112267918 TEST=ran `emerge-grunt coreboot` and `make what-jenkins-does` Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia83f234447b977efa824751c9674154b77d606b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/28101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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