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2014-05-10Replace SERIAL_CPU_INIT with PARALLEL_CPU_INITKyösti Mälkki
Lines with 'select SERIAL_CPU_INIT' where redundant with the default being yes. Since there is no 'unselect SERIAL_CPU_INIT' possibility, invert the default and rename option. This squelches Kconfig warnings about unmet dependencies. Change-Id: Iae546c56006278489ebae10f2daa627af48abe94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5700 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-10mainboard/jetway/nf81-t56n-lf: Toggle WDT and CIR in devicetree.cbEdward O'Callaghan
Turn on WDT support in the devicetree. Turn off CIR support. Dispense with old commentary. Change-Id: Icf0c0e12a0ed7ce6c3b6176653e076ffc2ba937e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5698 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10superio/fintek/f71869ad: Fix incorrect LDN'sEdward O'Callaghan
Turns out there are a few minor differences of the LDN's in the AD rev. of this Fintek chip. 0x07 is in fact the WDT so renaming and remove the now incorrect io mask. Add missing CIR LDN functionality and touch up src inline doc. Change-Id: I440aebad71d62d199d3283dd061933e76b21dda5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5696 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: cache reference code for S3 resumeAaron Durbin
In order to use the same reference code on S3 resume that was booted the program needs to be cached. Piggy back on the ramstage cache to save the loaded reference code program. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Noted locations of reference code caching and load addresses in console. Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179777 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5013 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: allow ramstage_cache_location() usage in ramstageAaron Durbin
To prepare for caching reference code for S3 resume the ramstage cache needs to be accesible in ramstage as well. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179776 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5012 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10ramstage_cache: allow ramstage usage add valid helperAaron Durbin
Allow ramstage cache to be used from ramstage proper. Also add a helper function for checking validity of ramstage cache structure. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179775 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5011 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: note S3 resume status earlierAaron Durbin
Certain code paths want to know if S3 resume is happening. However, the current baytrail code doesn't note S3 resume early enough. Therefore, mark S3 resume just after pattr setup. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179774 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5010 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: utilize reg_script_run_on_dev()Aaron Durbin
The inclusion of reg_script_run_on_dev() allows for removing some of the chained reg_scripts just to set up the device context. Use the new reg_script function in those cases. BUG=None BRANCH=None TEST=Built and booted. Didn't see any bizarre dmesg or coreboot console output. Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438 Signed-off-by: Aaron Durbin <adurbin@chromium.og> Reviewed-on: https://chromium-review.googlesource.com/179541 Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5009 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: initialize perf/power registersAaron Durbin
According to the reference code all these registers need to be set to their best known values. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Suspend and wake. No idea about observable impact yet. Change-Id: I0e31505a165eee1d177e5d726edcfa6947430476 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179749 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5008 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: add more iosf access functionsAaron Durbin
There's a slew of ports required to initialize baytrail's perf and power values. Therefore, add the necessary functionality in the iosf module as well as the reg_script library. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Change-Id: Id45def82f9b173abeba0e67e4055f21853e62772 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179748 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5007 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: remove verbosity in iosfAaron Durbin
The iosf access functions already use some common code, however there is a duplication for setting up the proper control register for port and opcode. Introduce macros to remove this verbosity. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Suspend and wake. Change-Id: I5bad7e2a11fa8e8bd4a3d7fa53d917b2565644f8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179747 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5006 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10reg_script: add reg_script_run_on_dev()Aaron Durbin
The reg_script library has proven to be useful. It's also shown that many scripts operate on devices. However, certain code paths run the same script on multiple, but different, devices. In order to make that easier introduce reg_script_run_on_dev() which takes a device as a parameter. That way, chained reg_scripts are not scrictly needed to run the same script on multiple devices. BUG=None BRANCH=None TEST=Built. Change-Id: I273499af4d303ebd7dc19e9b635ca23cf9bb2225 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179540 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5005 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: Add support for LPSS and SCC devices in ACPI modeDuncan Laurie
This adds the option to put LPSS and SCC devices into ACPI mode by saving their BAR0 and BAR1 base addresses in a new device NVS structure that is placed at offset 0x1000 within the global NVS table. The Chrome NVS strcture is padded out to 0xf00 bytes so there is a clean offset to work with as it will need to be used by depthcharge to know what addresses devices live at. A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and the EMMC 4.5 IRQ is changed to 44. New ACPI code is provided to instantiate the LPSS and SCC devices with the magic HID values from Intel so the kernel drivers can locate and use them. The default is still for devices to be in PCI mode so this does not have any real effect without it being enabled in the mainboard devicetree. Note: this needs the updated IASL compiler which is in the CQ now because it uses the FixedDMA() ACPI operator. BUG=chrome-os-partner:23505,chrome-os-partner:24380 CQ-DEPEND=CL:179459,CL:179364 BRANCH=none TEST=manual tests on rambi device: 1) build and boot with devices still in PCI mode and ensure that nothing is changed 2) enable lpss_acpi_mode and see I2C devices detected by the kernel in ACPI mode. Note that by itself this breaks trackpad probing so that will need to be implemented before it is enabled. 3) enable scc_acpi_mode and see EMMC and SDCard devices detected by the kernel in ACPI mode. Note that this breaks depthcharge use of the EMMC because it is not longer discoverable as a PCI device. Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179481 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5004 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09cougar_canyon2: Switch CPU/NB/SB to the shared FSP codeMartin Roth
CPU - fsp_model_206ax: - Remove Kconfig options and mark this as using the FSP. - Use shared FSP cache_as_ram.inc file Mainboard - intel/cougar_canyon2: - Update to use the shared FSP header file. - Modify to call copy_and_run() directly instead of returning to cache_as_ram.inc. Northbridge - fsp_sandybridge: - remove mrccache, fsp_util.[ch] - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits. - Update to use the shared FSP header file. These changes were validated with FSP: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801 MD5: 24965382fbb832f7b184d3f24157abda Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09Intel FSP: add a shared set of functions for the FSPMartin Roth
- Move the non chipset-specific fsp pieces out of the chipset into a shared area. This is used by northbridge / southbrige / SOC code. It pulls in pieces from Kconfig, Makefile and FSP specific code. - Enabled in the CPU code with a Kconfig "select PLATFORM_USES_FSP" Change-Id: I7ffa934c1df09b71d48a876a56e3b888685870b8 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5635 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09superio/serverengines/pilot: Avoid .c includesEdward O'Callaghan
Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5439 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09Squelch some warnings from KconfigKyösti Mälkki
Overriding global config entries in mainboard directory Kconfig files often raise unnecessary warnings. Squelch some of those. Change-Id: Ib5127672ae068670028aa25c8ccb5366277622f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5699 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09rambi: Enable DPTFDuncan Laurie
This enables the DPTF framework, but it doesn't do much without some sort of kernel+user components to drive it. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: Icb632a6e70c3912bbdfa6ef3f5c87cd79d2b8a3a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179480 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5003 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09baytrail: Basic DPTF frameworkDuncan Laurie
This is not complete yet but it compiles and doesn't cause any issues by itself. It is tied into the EC pretty closely so that is part of the same commit. Once we have more of the EC support done it will need some more work to make use of those new interfaces properly. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: I4b27e38baae18627a275488d77944208950b98bd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179459 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5002 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09rambi: Set panel power timingsDuncan Laurie
These are the values that are seen with VBIOS and may need tweaked for derivative panels. BUG=chrome-os-partner:24367 BRANCH=none TEST=boot on rambi in normal mode and see the panel come up Change-Id: Ie3120ab3c5298135626e8534d3954acd263dc74b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179365 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5001 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09baytrail: Enable panel and set timingsDuncan Laurie
These need to be set before the kernel will work without running the VBIOS option rom. Also necessary is setting the PP_CONTROL register with the EDP_FORCE_VDD bit. BUG=chrome-os-partner:24367 BRANCH=none TEST=boot on rambi in normal mode and see the panel come up Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179364 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5000 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09rambi: change SD card pulls to 20KAaron Durbin
Now that the SD card controller is limited to the SD card 2.0 spec it's possible to use 20K pulls for the pads. BUG=chrome-os-partner:24423 BUG=chrome-os-partner:24312 BRANCH=None TEST=Built and booted. Able to dd to/from /dev/mmcblk1 without any errors. Change-Id: Id5396c55330a84bf7a09d227507d2bfcde66a1a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179423 Reviewed-on: http://review.coreboot.org/4999 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09rambi: limit SD card controller to 2.0 specAaron Durbin
The rambi board can only meet the SD card 2.0 specification. Therefore, the controller capabilities need to be overridden to match. BUG=chrome-os-partner:24423 BRANCH=None TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows high speed as maximum timing as well as 3.3V signal voltage. Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179415 Reviewed-on: http://review.coreboot.org/4998 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-09baytrail: allow SD card controller capabilities overridesAaron Durbin
The SD card controller can have the capabilities it supports to be overridden. Add two optional fields to the chip structure to allow the mainboard to override the SD card controller capabilities. BUG=chrome-os-partner:24423 BRANCH=None TEST=Built and booted. Noted capabilities override console output. Change-Id: Ibfef8f765b35eeec6da969dd05f5484f8672a7b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179414 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4997 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09baytrail: fix nvs offsetsAaron Durbin
The VDAT data was off by 2 bytes when reading it from the kernel. The reason is that the header did not line up correctly with actual ACPI code. BUG=chrome-os-partner:24440 BRANCH=None TEST=crossystem devsw_cur now returns either 0 or 1 depending on state. Change-Id: Ie78599f29cd5daf7da98db5e37fa276d24339f6a Signed-off-by: Aaron durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179372 Reviewed-on: http://review.coreboot.org/4996 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09rambi: export SPI write-protect GPIO correctlyAaron Durbin
Bay Trail has 3 banks of gpios. Therefore, in order to properly identify a gpio the specific bank number as well as the GPIO within that bank is needed. The SPI write-protect GPIO is GPIO 6 within the SUS bank (offset 0x2000). BUG=chrome-os-partner:24324 BUG=chrome-os-partner:24408 BRANCH=None TEST=Built and booted. Looked at GPIO sysfs in the chromeos_acpi directory. Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179195 Reviewed-on: http://review.coreboot.org/4995 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09baytrail: lpe audio device needs memory for its firmwareAaron Durbin
The LPE audio device needs 1MiB of memory for its firmware. It also has a requirement that the memory needs to be on a 512MiB boundary. Just take 1MiB @ 512MiB for the LPE device. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and analyzed console logs for resources. Also interrogated registres within the kernel. Change-Id: I4d9ad5c7b5a2f3eb627b30528d738289278b3a7b Reviewed-on: https://chromium-review.googlesource.com/179192 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4994 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08ChromeOS boards: Always build code for bootmode strapsKyösti Mälkki
Leave it under BOOTMODE_STRAPS to control whether these have any functional meaning on the build. Change-Id: Ieb59aa7ab4b1e8da6a1002e7a8e5462eb7988d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08ChromeOS boards: Fix includesKyösti Mälkki
Change-Id: Ib8448f3d36a23538cd9fea897f09da3ec4ad007a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5647 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08Declare get_write_protect_state() without ChromeOSKyösti Mälkki
Change-Id: I72471ac68088cd26f8277b27b75b7d44ad72cfc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08Rename from save_chromeos_gpios() to init_bootmode_straps()Kyösti Mälkki
This feature is no longer specific to ChromeOS builds. Change-Id: If27d4dc7caff8a551b5b325cdebdd05c079ec921 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08ChromeOS boards: Use explicit include of chromeos.cKyösti Mälkki
Change-Id: I7b3d044fad1d6973910e9bef347478a45c149a4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08superio/fintek/f71869ad: Make hwm devicetree configurableEdward O'Callaghan
Provision the configuration of the Fintek F71869AD Hardware Monitor's configuration by way of devicetree.cb. Make use of this in the jetway/nf81-t56n-lf board to properly control fan's. Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5580 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-08superio/fintek/f71869ad: Configure multi-func reg in devicetreeEdward O'Callaghan
Facilitate for the configuration of so called "Multi-function Select Registers" with devicetree.cb in ramstage. Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI mode. This allows the Fintek to correctly talk to the Southbridge over the SMBus for CPU temperature data as to control fans and so on. Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5576 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08mainboard/jetway/nf81-t56n-lf: Improve diags in romstageEdward O'Callaghan
romstage reports a completely unintelligible printf of "error level:", fix this and document meaning of the return values in source. Change-Id: Ia2fb9a6206e08822f6c2f62b69bf22cdae2ba819 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5465 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08rambi: Make ec_in_rw a legacy GPIOShawn Nematbakhsh
ec_in_rw needs to be read by depthcharge, which only supports legacy GPIOs. BUG=chrome-os-partner:24408 TEST=Manual on Rambi. Cold + warm boot device, verify that depthcharge detects the proper ec_in_ro state. BRANCH=None Change-Id: I25802b445c795eb85580c22d880efee8eeb21318 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179228 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4993 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-05-08baytrail: gpio: Make GPIO inputs MMIO by defaultShawn Nematbakhsh
The Linux kernel driver cannot handle Baytrail legacy GPIOs, so make the default input GPIO type MMIO. BUG=chrome-os-partner:24408 TEST=Manual on Rambi. Run "echo 169 > /sys/class/gpio/export; cat /sys/class/gpio/gpio169/value", verify GPIO value changes based upon mic jack status. BRANCH=None Change-Id: I27870ce8b7ecae9228e06e48c8759409c824c2eb Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179169 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4992 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08rambi: Change eMMC pin PUs to 2KShawn Nematbakhsh
Strengthen PUs on all eMMC pins to fix problems with eMMC not coming up on certain boards. BUG=chrome-os-partner:24353 TEST=Manual. Burn FW on board that previously failed to boot eMMC, verify chromeos can now install + boot from eMMC. BRANCH=none Change-Id: I7a9742968b8b8c2c42285ffc21de46aed9c87fb7 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178917 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4991 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08rambi: configure SD card signalsAaron Durbin
Rambi 1.5 boards use the native SD card controller on baytrail. Therefore, enable those signals. The CLK, D*, and CMD pins use 2K pulls as these were shown to not exhibit any errors when doing reads or writes to a DDR50 sd card. Note that if a servo is connected on needs to enable the sd_vref_sel rail to pp1800 as this causes issues with card detect if it is not set to pp1800. BUG=chrome-os-partner:24312 BRANCH=None TEST=Built and booted. Tested sd card read and write works in kernel. Also noted that write protect detection works as well. Change-Id: I520e2808acbd8494534fcb710411dbc0e12fc874 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178961 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4990 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08baytrail: enable lpe resources assigned to deviceAaron Durbin
The enable_resources callback was accidentally populated with NULL. Make that callback be the generic pci_dev_enable_resources. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted. Change-Id: I670b51bd9aff6764e9b549287a737b662572cdc7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178960 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4989 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08baytrail: Fix _CRS to build with new IASLDuncan Laurie
The new IASL is complaining about the PCI memory region not having consistent base/end/length values because they are placeholder that are fixed up in the method before returning. Put in some more valid placeholder values to make it happy. BUG=chromium:311294 BRANCH=none TEST=build and boot with IASL 20130117 on rambi Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178864 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@google.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4988 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08rambi: configure the LPE audio codec clockAaron Durbin
Rambi has the LPE audio codec connected to PMC_PLT_CLK[0]. Configure it for 25MHz. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted. Noted message in console output. Change-Id: I11297ba951149e5831c65ca70ac7bdbbed113098 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178781 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4987 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-08baytrail: add lpe codec clock configurationAaron Durbin
Add device tree option to determine if the LPE audio codec has a platform clock signal connected to it from the SoC. If a frequency is selected the platform clock number is used to enable the clock. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted rambi with 25MHz option. Probed pin to audio codec. Noted 25MHz clock. Change-Id: I67d0d034f30ae1c7ee8269c0aea43e8c92ff868c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178780 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4986 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08baytrail: Add ACPI code to describe GPIO controllerDuncan Laurie
There are 3 banks of GPIOs that need to be described with specific _UID and memory/interrupt values. BUG=chrome-os-partner:24314 BRANCH=none TEST=build and boot on rambi, check for probed driver: gpiochip_find_base: found new base at 154 gpiochip_add: registered GPIOs 154 to 255 on device: INT33FC:00 gpiochip_find_base: found new base at 126 gpiochip_add: registered GPIOs 126 to 153 on device: INT33FC:01 gpiochip_find_base: found new base at 82 gpiochip_add: registered GPIOs 82 to 125 on device: INT33FC:02 fed0c000-fed0cfff : INT33FC:00 fed0c000-fed0cfff : INT33FC:00 fed0d000-fed0dfff : INT33FC:01 fed0d000-fed0dfff : INT33FC:01 fed0e000-fed0efff : INT33FC:02 fed0e000-fed0efff : INT33FC:02 Change-Id: I9619e2af4e1ccdf3d7b2e4ae280aadf22e278aeb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178601 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4985 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08baytrail: Update to microcode 31E and fix C-state tableDuncan Laurie
With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS. BUG=chrome-os-partner:23505 BRANCH=none TEST=build and boot on rambi, check that C1/C2/C3 are all used now Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178461 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4984 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-07baytrail: minor stylePatrick Georgi
use IS_ENABLED() over #if brackets Change-Id: I101f99971c0f7b5311ef19cc9832713ab0696935 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5692 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-07rambi: Remove outdated commentPatrick Georgi
Change-Id: Ic555d23a9112677a784dd814601f8202d4d17261 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5691 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-07rambi: handle single channel configsAaron Durbin
Some 1.5 boards have a single channel ram configuration. Accomodate such configs. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built and booted ChromeOS. Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178340 Reviewed-by: Nick Sanders <nsanders@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: http://review.coreboot.org/4983 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07baytrail: romstage: Add config option to enable RMTShawn Nematbakhsh
Add config option to enable RMT in the MRC. BUG=chrome-os-partner:21807 TEST=Manual. Build w/ "USE=rmt", verify RMT print seen on FW console. Build w/o USE flag, verify no RMT print. BRANCH=None. CQ-DEPEND=CL:*148655 Change-Id: Ibd3da87317a3359e797d9b43bc437e7227a85048 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178095 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4982 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07baytrail: pcie: Root port initializationAaron Durbin
Add PCIe driver to initialize root ports. BUG=chrome-os-partner:24111 TEST=Manual on Rambi. Verify that PCIe Wifi card is detected and able to detect networks. BRANCH=None. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I3c68da5f27cd162e112add488bdf5ced192b7d12 Reviewed-on: https://chromium-review.googlesource.com/177652 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4981 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 18:15:19 +0000