Age | Commit message (Collapse) | Author |
|
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I02e6fdcd6685e0dd3fa7872b054ebe508157a0ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33758
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ib000e12cd568dd83b9533efe66e67878b806b3f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I02b279a2b625ecbdf827cb4643d772eb81ddfe70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
Remove the mailbox call to notify the PSP that DRAM is ready. This
is not supported on Family 17h.
Remove the selectable SMU firmware. This is a feature of the PSP
bootloader and the standard bootloader doesn't contain the ability.
Clean up additional mentions of PSP within picasso.
Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
The command line options for picasso will look different than
stoneyridge. Remove the fanned/fanless distinction to simplify
the makefile.
Picasso will use subprograms instead of fanned/fanless SKUs.
Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33753
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ie9cf361ed0caba9c73727453c4a503557edc854d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I9d0098082c224bbf5ab2b4f0f41eb8b5b729eec7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove
source that uses these. Remove USB devices from the AOAC registers.
Remove the D0/D3 support from ASL, including all supporting xHCI
firmware loading support. Remove xHCI firmware from amdfw.rom.
Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
Remove the hudson-style support for the Gigabit Ethernet Controller.
Change-Id: I2124b949a866148a97d9cd6e7fd418f7de8e2216
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
Convert all remaining stoneyridge names to picasso.
Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
|
To use fixed PCI bus numbers is always invalid.
Change-Id: Ia2ffdb1f5e0ff398674a016ad4cb94f622c057ff
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
It was never tested or injected.
Change-Id: I3fd82aaa11afc5adab212ec6709580b4bcc67ca3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34001
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Only (conditionally) used part was dump_pci_device()
and that was never particularly useful either.
Change-Id: Iaacfa511de1ce1e0bdbd2e8a74e41d336e505670
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This also corrects some CPU naming in comments.
Change-Id: I8b9fc3ba0d6dc6e0001b40518aae2d26c1184dc8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34000
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
garg 2A2C DB: SKU ID - 1
garg HDMI DB: SKU ID - 9
garg LTE DB: SKU ID - 17
For HDMI SKU9, GPIO needs to be overriden to enable
DDI1 DDC SDA/SCL.
BUG=b:134912735
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: I6ad8e5aa52f503121b10fe353e4bf4021aee2061
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
Enable EMR Pen Stylus function for Grob360S
BUG=b:135968368
BRANCH=octopus
TEST=EMR function working normally with HW reworked Fleex.
Change-Id: Ia220dc0d3051b79b110b4df66df108f701776478
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33802
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Google project name is Bloog.
Bloog is 12-inch LCD.
Blooguard is 14-inch LCD so would prefer to use a different SAR values instead.
Use sku-id to load the SAR values.
BUG=b:135078377
BRANCH=octopus
TEST=build and verify SAR load by sku-id
Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
When we added CONFIG_VBOOT_MIGRATE_WORKING_DATA, the idea was that on
some Arm platforms the original working data buffer was in SRAM, which
stays accessbile for the whole runtime of the system. There is no reason
to migrate it into CBMEM on those platforms because ramstage and the
payload could continue to access it in SRAM.
Now that we've had a couple of months of experience with this option, we
found that most of our Arm platforms have some issue that requires
migrating anyway, because BL31 often claims SRAM for itself and makes it
inaccessible to the payload. On the remaining platforms, accessing SRAM
from the payload is possible but still an issue, because libpayload
doesn't have enough memory layout information to set up proper page
tables for it, so we're accessing it uncached and at risk of alignment
errors.
Rather than having to figure out how to map the right SRAM range for
every platform in the payload, let's just get rid of the option.
memcpy()ing 12KB isn't worth this much hassle.
Change-Id: I1b94e01c998f723c8950be4d12cc8f02b363a1bf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Use literals KHz & MHz for kilohertz and megahertz frequency usages
in macro definition.
Change-Id: If1ca6e5e7b0603f93f3c980cc85af470fdcd54ba
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57c0bcfbe0d96aac106f771e8efb3bd471302c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33965
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
MMIO_BUS_RANGE_SHIFT is a numerical value and not a bit field.
Change it to simply 2. Otherwise its usage winds up evaluating
to BusRange << (1 << 1).
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I2a6ecfc9fbfd45f69194b8daef43ff84a1dfd5fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Also don't define the default as this results in spurious lines in the
.config.
The only difference in the generated config.h is that for most board
ARCH_RISCV_M goes from 1 to 0. This should not matter.
Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31311
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I877e19c014759e33b9cc48ff9ee27e898737aece
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: If50d9218119d5446d0ce98b8a9297b23bae65c72
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33816
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enhance elog wake source information with more details about which USB port
resulted in a wake from S3 or S0ix.
BUG=b:123429132
BRANCH=none
TEST=``FW_NAME=hatch emerge-hatch chromeos-ec depthcharge vboot_reference
libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch
coreboot chromeos-bootimage``
Ensure /build/hatch/firmware/image-hatch.serial.bin has been built.
Plug a keyboard into a USB port on the DUT.
Switch the DUT to the console (Ctrl-Alt-F2, or use the AP console via
servo).
On the console, run ``powerd_dbus_suspend``.
Wait for the DUT to enter low power mode.
Verify low power mode by issuing the ``powerinfo`` command on the EC
console (via servo). Expect to see ``power state 4 = S0ix``.
Press a key on the USB keyboard.
The DUT wakes up.
On the console, run ``mosys eventlog list`` and look for the wake source.
156 | 2019-06-26 09:46:07 | S0ix Enter
157 | 2019-06-26 12:14:05 | S0ix Exit
158 | 2019-06-26 12:14:05 | Wake Source | Internal PME | 0
159 | 2019-06-26 12:14:05 | Wake Source | GPE # | 109
Program image-hatch.serial.bin into the DUT using flashrom.
Repeat the ``powerd_dbus_suspend``, ``powerinfo``, ``mosys eventlog list``
sequence.
12 | 2019-06-26 14:52:23 | S0ix Enter
13 | 2019-06-26 14:53:07 | S0ix Exit
14 | 2019-06-26 14:53:07 | Wake Source | PME - XHCI (USB 2.0 port) | 3
15 | 2019-06-26 14:53:07 | Wake Source | GPE # | 109
Change-Id: Ie9ef870e219733dea9806c766f5351db25689b32
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
`cpuid_eax()` returns an unsigned integer.
Change-Id: Iebb6501130bc9ae333d45ae9d2e10c918245a6d1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for
trackpad interrupts due to ITSS not honoring the INVERT config. Now
that's fixed, we can configure trackpad wake and interrupts on GPP_A21
only.
BUG=b:130436471
BRANCH=None
TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad
2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure
through "mosys eventlog list" that the wake source is the trackpad.\
3. Run "echo mem > /sys/power/state", wait until device goes into S3,
click trackpad to ensure device wakes.
Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
Now that ITSS config is fixed, we can set the IOAPIC pad configs
correctly.
BUG=b:123967687
BRANCH=None
TEST=Make sure Hatch is booting and tested out trackpad to make
sure can move cursor and wake by clicking on the trackpad
after running powerd_dbus_suspend.
Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I7031b07ae105a14be3c5d4e52ecc1364956fd845
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33750
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove all Picasso bootblock support. CAR is not a supportable
feature, and the first code executed at the reset vector will be
a hybrid romstage. Details for this implementation may be found
in Documentation/soc/amd/picasso/family17h.md.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Update paths. There are still a few paths in Kconfig relating to PSP
and the firmware directory table. Those will be updated in a follow-on
commit.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I18f3d80dbeabd754ebcee6593864fd613fc2ef7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32412
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that the Makefile is updated, we can change the name back without
it affecting the Stoney build.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I18ee48865fb64265f38179560265827783d50820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ie466bc39ed6aa9d2a8651bd9290090b83cd97d74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32410
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Remove files that aren't needed for the picasso port.
Remove traces of AGESA v5 (includes binaryPI support files). Remove
SPD helper.
Picasso (and all AMD Family 17h processors) have a very different
boot flow from previous products. Memory is initialized by the PSP
before the x86 processor is released from reset. The SPD is read by
the PSP, so it's not needed in coreboot.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
So that everyone can see what's being updated from stoney, we're
starting with a direct copy of the stoney directory. There are
arguments both for and against doing it this way, but I believe
This the most transparent way. We've moved much of the duplicated
stoney code into the soc/amd/common directory and will continue
that work as it becomes obvious that we have unchanged code between
the SOCs.
Makefile.inc has been renamed as makefile.inc so that it won't
build in jenkins until the directory is updated.
Other than that change, this is an exact copy of the stoneyridge
SOC directory which will be updated in the follow-on commits in
the patch train.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Samsung K4F6E3S4HM-MGCJ density is 16Gb
BUG=b:121228792
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
MemTotal: 8041964kB in /proc/meminfo
Change-Id: Ie8ecd82b92d4e82d3955cf773febca30f6280a5e
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
For the PCI_VENDOR_ID_ATI case, we can rely on
pci_rom_acpi_fill_vfct() to make the call if necessary.
For hardware other than ATI, pci_rom_probe() was already
called from pci_rom_ssdt() and pci_dev_init(), so
PCI_ROM_ADDRESS BAR is already enabled, if requested so.
Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
|
|
The function pci_rom_probe() may be called multiple times
for a device. For cases where CBFS does not contain optionrom
file, only the first time probing for the on-board ROM
chip worked.
PCI_ROM_ADDRESS_ENABLE is set on the first run. Mask out all
the reserved bits of PCI_ROM_ADDRESS register to get correct
physical address for rom_header.
Change-Id: I14374954af09201494bf2f13e5a6e4dc640c05ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
|
|
* Add architecture independend way of clearing all DRAM
* Implemented in ramstage as MTRRs need to be set to speed up
clearing. Takes up to 15 seconds per GiB otherwise.
* Use memset_pae on x86
* Add quirks for FSP1.0
Tested on P8H61M-Pro:
* Clears 4GiB in less than 1 second
Tested on wedge100s:
* Clears 8GiB in 2 seconds
Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31550
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To clear all DRAM on x86_32, add a new method that uses PAE to access
more than 32bit of address space.
Add Documentation as well.
Required for clearing all system memory as part of security API.
Tested on wedge100s:
Takes less than 2 seconds to clear 8GiB of DRAM.
Tested on P8H61M-Pro:
Takes less than 1 second to clear 4GiB of DRAM.
Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I28c2beca4bc26ddb896e68886571ebdc82276b48
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I5b5b7bc61dd82fb1b866857d60926b057fae3715
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33445
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Since ttyS0 isn't used for UART0, configure ttyS4 as default
Change-Id: Ia0469226253b08328807d5401c05633296e43d22
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33785
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Instead of maintaining this in 3rdparty/blobs use the
3rdparty/intel-microcode which is maintained by Intel.
This allows for some finegrained control where family+model span
multiple targets.
Microcode updates present in
3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those
contain updates not present in the Intel repo. Those are presumably
early CPU samples that did not end up in products.
The following MCU are get a new revision:
old:
sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552
sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528
sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288
sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312
sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728
sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384
sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336
sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304
sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304
sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280
sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304
sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432
sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328
sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304
sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328
new:
sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552
sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504
sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288
sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336
sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728
sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408
sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360
sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328
sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304
sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328
sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456
sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352
sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328
sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352
Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
No message is reported in tlcl_lib_init() when tis_init() or tis_open()
returned an error value.
Add debug string.
BUG=N/A
TEST=Build binary and verified logging on Facebook FBG-1701
Change-Id: I522e488ddd3a1bd94a1a8c8470c757bd79c6d5c5
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Prior to commit
d731a24 src/cpu/intel: Set get_ia32_fsb function common
value of 200 was silently used as a default for fsp_rangeley
(model_406dx) in cpu/x86/lapic/apic_timer:set_timer_fsb().
After the commit, get_ia32_fsb() returns -2, eventually
resulting with divide-by-zero in timer_monotonic_get(), as
get_timer_fsb() returns 0.
Add Rangeley CPUID model 0x4d to get_ia32_fsb() as a fix,
using BCLK = 100 MHz based on the comments in
northbridge/intel/fsp_rangeley/udelay.c
Change-Id: I306f85dba9b1e91539fc0ecc9b2ae9d54f82be6c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
This patch makes CONFIG_RAMPAYLOAD default enable upon selection
of HAVE_RAMPAYLOAD kconfig from mainboard for x86 platform.
Without this CL, CONFIG_RAMPAYLOAD is still disabled although
mainboard has selected CONFIG_HAVE_RAMPAYLOAD.
Change-Id: I40308bbf970a0dbe5f7e2086ed8a7a70c2a3a32c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33859
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I4ac67d1577229e63424dd7fd0ff84d1acfe826c3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
It looks like in days gone by that these switches were once parts of
loops that incremented 'index' as they went along. However, we don't
have any loops anymore, so remove the needless increments and streamline
the rest of the assignments.
Change-Id: Iaabee984333c273af7810f9c11ed26bbb2a995d1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|